Cypress CY7C64215 User Manual
CY7C64215
enCoRe™ III Full Speed USB Controller
Features
enCoRe III Core
Block Diagram
■
Powerful Harvard Architecture Processor
❐
M8C Processor Speeds to 24 MHz
❐
Two 8x8 Mu lt i pl y, 32-bit Accumu la te
❐
3.0V to 5.25V Operating Voltage
❐
USB 2.0 USB-IF certified. TID# 40000110
❐
Operating Temperature Range: 0°C to +70°C
■
Advanced Peripherals (enCoRe™ III Blocks)
❐
6 Analog enCoRe III Blocks provide:
• Up to 14-bit Incremental and Delta-Sigma ADCs
❐
Programmable Threshold Comparator
❐
4 Digital enCoRe III Blocks provide:
• 8-bit and 16-bit PWMs, timers and counters
•I2C Master
• SPI Master or Slave
• Full Duplex UART
• CYFISNP and CYFISPI modules to talk to Cypress CYFI
radio
■
Complex Peripherals by Combining Blocks
■
Full-Speed USB (12 Mbps)
❐
Four Unidirectional Endpoints
❐
One Bidirectional Control Endpoint
❐
Dedicated 256 Byte Buffer
❐
No External Crystal Required
❐
Operational at 3.0V – 3.6V or 4.35V – 5.25V
■
Flexible On-Chip Memory
❐
16K Flash Program Storage 50,000 Erase/Write Cycles
❐
1K SRAM Data Storage
❐
In-System Serial Programming (ISSP)
❐
Partial Flash Updates
❐
Flexible Protection Modes
❐
EEPROM Emulation in Flash
■
Programmable Pin Configuratio n s
❐
25-mA Sink on all GPIO
❐
Pull up, Pull down, High- Z, Strong, or Open Drain Drive
Modes on all GPIO
❐
Configurable Interrupt on all GPIO
■
Precision, Programmable Clocking
❐
Internal ±4% 24 and 48 MHz Oscillator
❐
Internal Oscillator for Watchdog and Sleep
❐
0.25% Accuracy for USB with no External Components
■
Additional System Resources
❐
I2C™ Slave, Master, and Multi-Master to 400 kHz
❐
Watchdog and Sleep Timers
❐
User-Configurable Low Voltage Detection
❐
Integrated Supervisory Circuit
❐
On-Chip Precision Voltage Reference
■
Complete Development T ools
❐
Free Development Software (PSoC® Designer™)
❐
Full-Featured, In-Circuit Emulator and Programmer
❐
Full Speed Emulation
❐
Complex Breakpoint Structure
❐
128K Bytes Trace Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document 38-08036 Rev. *C Revised December 08, 2008
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CY7C64215
Applications
DIGITAL SYSTEM
To System Bus
D
i
g
i
t
a
l
C
l
o
c
k
s
F
r
o
m
C
o
r
e
Digital enCoRe III Block Array
To Analog
System
8
Row Inp ut
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 1
Port 0
Port 3
Port 2
Port 5
Port 4
Port 7
■
PC HID devices
❐
Mouse (Optomechanical, Optical, Trackball)
❐
Keyboards
❐
Joysticks
■
Gaming
❐
Game Pads
❐
Console Keyboards
■
General Purpose
❐
Barcode Scanners
❐
POS Terminal
❐
Consumer Electronics
❐
Toys
❐
Remote Controls
❐
USB to Serial
enCoRe III Functional Overview
The enCoRe III is based on flexible PSoC architecture and is a
full-featured, full-speed (12 Mbps) USB part. Configurable
analog, digital, and interconnect circuitry enable a high level of
integration in a host of consumer, and communication applications.
This architecture allows the user to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast CPU, Flash program memory,
SRAM data memory, and configurable IO are included in both
28-pin SSOP and 56-pin QFN packages.
The enCoRe III architecture, as illustrated in Figure , is
comprised of four main areas: enCoRe III Core, Digital System,
Analog System, and System Resources including a full-speed
USB port. Configurable global busing allows all the device
resources to combine into a complete custom system. The
enCoRe III CY7C64215 can have up to seven IO ports that
connect to the global digital and analog interconnects, providing
access to 4 digital blocks and 6 analog blocks.
communication. A low power 32 kHz ILO (internal low speed
oscillator) is provided for the Sleep timer and WDT. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the enCoRe III. In USB systems, the IMO
self-tunes to ±0.25% accuracy for USB communication.
enCoRe III GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
The Digital System
The Digital System is composed of four digital enCoRe III blocks.
Each block is an 8-bit resource that is used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references.
Figure 1. Digital System Block Diagram
enCoRe III Core
The enCoRe III Core is a powerful engine that supports a rich
feature set. The core includes a CPU, memory, clocks, and
configurable GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with up to 20
vectors, to simplify programming of real-time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory encompasses 16K of Flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
enCoRe III incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 8%
over temperature and voltage. The 24 MHz IMO is doubled to 48
MHz for use by the digital system, if needed. The 48 MHz clock
is required to clock the USB block and must be enabled for USB
Document 38-08036 Rev. *C Page 2 of 30
Digital configurations that can be built from the blocks include
those listed below.
■
PWMs, Timers and Counters (8-bit and 16-bit)
■
UART 8-bit with selectable parity
■
SPI master and slave
■
I2C Master
■
RF Interface: Interface to Cypress CYFI Radio
The digital blocks is connected to any GPIO through a series of
global buses that can route any signal to any pin. The buses also
allow for signal multiplexing and for performing logic operations.
This configurability frees your designs from the constraints of a
fixed peripheral controller.
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CY7C64215
The Analog System
ACB00 ACB01
Block
Ar r ay
Array Input
Configuration
ACI1[1:0]
ASD20
ACI0[1:0]
P0[6]
P0[4]
P0[2]
P0[0]
P2[2]
P2[0]
P2[6]
P2[4]
RefIn
AGNDIn
P0[7]
P0[5]
P0[3]
P0[1]
P2[3]
P2[1]
Reference
Generators
AGNDIn
RefIn
Bandgap
RefHi
RefLo
AGND
ASD11
ASC21
ASC10
Interface to
Di g it al System
M8C I n ter face (Addr ess B u s, D ata B us, Etc. )
Analog Reference
All IO
(Except Po r t 7)
Analog
Mux Bus
The Analog System is composed of six configurable blocks,
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and are
customized to support specific application requirements.
enCoRe III analog function supports the Analog-to-digital
converters (with 6 to 14-bit resolution, selectable as Incremental,
and Delta Sigma) and programmable threshold comparator).
Analog blocks are arranged in two columns of three, with each
column comprising one CT (Continuous Time - AC B00 or AC
B01) and two SC (Switched Capacitor - ASC10 and ASD20 or
ASD11 and ASC21) blocks, as shown in Figure 2.
Figure 2. Analog System Block Diagram
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin in ports 0–5.
Pins which are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis
with comparators and analog-to-digital converters. It is split into
two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Additional System Resources
System Resources provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power-on reset. Brief
statements describing the merits of each resource follow.
■
Full-Speed USB (12 Mbps) with five configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks are routed to
both the digital and analog systems.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
enCoRe III Device Characteristics
enCoRe III devices have four digital blocks and six analog
blocks. The following table lists the resources available for
specific enCoRe III device.
Table 1. enCoRe III Device Characteristics
Part
Number
CY7C64215
-28PVXC
CY7C64215
-56LFXC
up to 221 4 22 2 2 6 1K 16K
up to 501 4 48 2 2 6 1K 16K
Digital IODigital
Rows
Digital
Blocks
Inputs
Analog
Analog
Outputs
Blocks
Analog
Analog
Columns
Getting Started
The quickest path to understanding enCoRe III silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
Size
SRAM
Size
Flash
of the enCoRe III integrated circuit and presents specific pin,
register, and electrical specifications. enCoRe III is based on the
Document 38-08036 Rev. *C Page 3 of 30
architecture of the CY8C24794. For in-depth information, along
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CY7C64215
with detailed programming information, reference the PSoC™
Commands
Results
PSoC
TM
Designer
Core
Engine
PSoC
Configuration
Sheet
M a nufacturing
Inf ormation
File
Dev ice
Database
Importable
Des ign
Database
Dev ice
Programmer
Graphical Designer
Interface
Context
Sensitive
Help
Emulation
Pod
In- Circuit
Em ulator
Project
Database
Application
Database
User
Modules
Library
PSoC
TM
Designer
Mixed-Signal Array Technical Reference Manual.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest enCoRe III device data sheets
on the web at http://www.cypress.com.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
enCoRe III development. Go to the Cypress Online Store web
site at http://www.cypress.com, click the Online Store shopping
cart icon at the bottom of the web page, and click USB (Universal
Serial Bus) to view a current list of available items.
Development Tools
PSoC Designer is a Microsoft® Windows® based, integrated
development environment for enCoRe III. The PSoC Designer
IDE and application runs on Windows NT 4.0, Windows 2000,
Windows Millennium (Me), or Windows XP. (Refer to the PSoC
Designer Functional Flow diagram below).
PSoC Designer helps the customer to select an operating configuration for the enCoRe III, write application code that uses the
enCoRe III, and debug the application. This system provides
design database management by project, an integrated
debugger with In-Circuit Emulator, in-system programming
support, and the CYASM macro assembler for the CPUs. PSoC
Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the enCoRe III blocks. Examples of user modules are
ADCs, SPIM, UART, and PWMs.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time.
PSoC Designer sets up power-on initialization tables for selected
enCoRe III block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of enCoRe III block configurations at run
time. PSoC Designer can print out a configuration sheet for a
given project configuration for use during application
programming in conjunction with the Device Data Sheet. Once
the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible
to change the selected components and regenerate the
framework.
Document 38-08036 Rev. *C Page 4 of 30
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Application Editor
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
Assembler. The macro assembler allows the assembly code to
merge seamlessly with C code. The link libraries automatically
use absolute addressing or is compiled in relative mode, and
linked with other software modules to get absolute addressing.
C Language Compiler. A C language compiler is available that
supports the enCoRe III family of devices. Even if you have never
worked in the C language before, the product quickly allows you
to create complete C programs for the enCoRe III devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the enCoRe III architecture. It comes complete
with embedded libraries providing port and bus operations,
standard keypad and display support, and extended math
functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the enCoRe
III device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE Cube is available for development support. This hardware has the capability to program
single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal which operates with
all enCoRe III devices.
Designing with User Modules
The development process for the enCoRe III device differs from
that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the enCoRe III
architecture a unique flexibility that pays dividends in managing
specification change during development and by lowering
inventory costs. These configurable resources, called enCoRe
III Blocks, have the ability to implement a wide variety of
user-selectable functions. Each block has several registers that
determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles
permit you to adapt the hardware and software. This substantially lowers the risk of having to select a different part to meet
the final design requirements.
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral func tions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties.
The user module library contains the following digital and analog
module designs:
■
Analog Blocks
❐
Incremental ADC (ADCINC)
❐
Delta Sigma ADC (DelSig)
❐
Programmable Threshold Comparator (CMPPRG)
■
Digital Blocks
❐
Counters: 8-bit and 16-bit (Counter8 and Counter 16)
❐
PWMs: 8-bit and 16-bit (PWM8 and PWM16)
❐
Timers: 8-bit and 16-bit (Timer8 and Timer 16)
❐
I2C Master (I2Cm)
❐
SPI Master (SPIM)
❐
SPI Slave (SPIS)
❐
Full Duplex UART (UART)
❐
RF (CYFISNP and CYFISPI)
■
System Resources
❐
Protocols:
• USBFS
• I2C Bootheader (Boothdr I
• USB Bootheader (BoothdrUSBFS)
• USBUART
❐
Digital System Resources
•E2PROM
•LCD
•LED
• 7-segment LED (LED7SEG)
• Shadow Registers (SHADOWREG)
• Sleep Timer
2
C)
Document 38-08036 Rev. *C Page 5 of 30
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CY7C64215
Each user module establishes the basic register settings that
Debugger
Interface
to ICE
Application Editor
Device Editor
Project
M anage r
Source
Code
Editor
Storage
I nspector
User
Module
Selection
Placement
and
Parameter
-ization
Generate
Application
Build
All
Event &
Breakpoint
Manager
Build
Manager
Source
Code
Generator
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
of resolution. The user module parameters permit the desi gner
to establish the pulse width and duty cycle. User modules also
provide tested software to cut development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that is adapted as needed.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
The development process starts when you open a new project
and bring up the Device Editor/Chip Layout View, a graphical
user interface (GUI) for configuring the hardware. You pick the
user modules you need for your project and map them onto the
PSoC blocks with point-and-click simplicity. Next, you build
signal chains by interconnecting user modules to each other and
the IO pins. At this stage, you also configure the clock source
connections and enter parameter values directly or by selecting
values from drop-down menus. When you are ready to test the
hardware configuration or move on to developing code for the
project, you perform the “Generate Application” step. This
causes PSoC Designer to generate source code that automati cally configures the device to your specification and provides the
high-level user module API functions.
Figure 4. User Module and Source Code Develo pment Flows
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE CUBE)
where it runs at full speed. Debugger capabilities rival those of
systems costing many times more. In addition to traditional
single-step, run-to-breakpoint and watch-variable features, the
Debugger provides a large trace buffer and allows you define
complex breakpoint events that include monitoring address and
data bus values, memory locations and external signals.
Document 38-08036 Rev. *C Page 6 of 30
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Acronym Description
AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
ECO external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
LSb least-significant bit
LVD low voltage detect
MSb most-significan t bit
PC program counter
PLL phase-locked loop
POR power on reset
PPOR precision power on reset
PSoC Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 5 on page 13 lists all the abbreviations used to
measure the enCoRe III devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (For example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document 38-08036 Rev. *C Page 7 of 30
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CY7C64215
MLF
(Top View)
A, I, M, P2[3]
A, I, M, P2[1]
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
M, I2C SCL, P1[7]
M, I2C SD A, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
D+
D-
Vdd
P7[7]
P7[0]
M, I 2C SD A, P1[0]
M, P1[2]
M, P1[4]
M, P1[6]
15161718192021
22
2324252627
28
P2[4], M
P2[6], M
P0[0], A, I, M
P0[2], A, I, M
P0[4], A, I, M
P0[6], A, I, M
Vdd
Vss
P0[7], A, I, M
P0[5], A, IO, M
P0[3], A, IO, M
P0[1], A, I, M
P2[7], M
P2[5], M
43
44
45
46
47
48
49
50
51
52
53
54
55
56
P2[2], A, I, M
P2[0], A, I, M
P4[6], M
P4[4], M
P4[2], M
P4[0], M
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
42
41
40
39
38
37
36
35
34
33
32
31
30
29
56-Pin Part Pinout
The CY7C64215 enCoRe III device is available in a 56-pin package which is listed and illustrated in the following table. Every port pin
(labeled “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 2. 56-Pin Part Pinout (MLF*)
Pin
No.
Type
Digital Analog
Name Description
1 IO I, M P2[3] Direct switched capacitor block input.
2 IO I, M P2[1] Direct switched capacitor block input.
3 IO M P4[7]
4 IO M P4[5]
5 IO M P4[3]
6 IO M P4[1]
7 IO M P3[7]
8 IO M P3[5]
9 IO M P3[3]
10 IO M P3[1]
11 IO M P5[7]
12 IO M P5[5]
13 IO M P5[3]
14 IO M P5[1]
15 IO M P1[7] I2C Serial Clock (SCL).
16 IO M P1[5] I2C Serial Data (SDA).
17 IO M P1[3]
18 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
19 Power Vss Ground connection.
20 USB D+
21 USB D22 Power Vdd Supply voltage.
23 IO P7[7]
24 IO P7[0]
25 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
26 IO M P1[2]
27 IO M P1[4]
28 IO M P1[6]
29 IO M P5[0]
Pin
No.
31 IO M P5[4] 44 IO M P2[6] External Voltage Reference (VREF) input.
32 IO M P5[6] 45 IO I, M P0[0] Analog column mux input.
33 IO M P3[0] 46 IO I, M P0[2] Analog column mux input and column output.
34 IO M P3[2] 47 IO I, M P0[4] Analog column mux input and column output.
35 IO M P3[4] 48 IO I, M P0[6] Analog column mux input.
36 IO M P3[6] 49 Power Vdd Supply voltage.
37 IO M P4[0] 50 Power Vss Ground connection.
38 IO M P4[2] 51 IO I, M P0[7] Analog column mux input.
39 IO M P4[4] 52 IO IO, M P0[5] Analog column mux input and column output
40 IO M P4[6] 53 IO IO, M P0[3] Analog column mux input and column output.
41 IO I, M P2[0] Direct switched capacitor block input. 54 IO I, M P0[1] A nalog column mux input.
42 IO I, M P2[2] Direct switched capacitor block input. 55 IO M P2[7]
43 IO M P2[4] External Analog Ground (AGND) in-
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground (Vss).
put.
56 IO MP2[5]
CY7C64215 56-Pin enCoRe III Device
Type
Name Description30 IO M P5[2] Digital Analog
Document 38-08036 Rev. *C Page 8 of 30
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CY7C64215
28-Pin Part Pinout
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[4]
P2[2], AI
P2[0], AI
P1[6]
P1[4]
P1[2]
P1[0], I2C SDA
Vdd
D-
Vss
AI, P0[7]
AIO, P0[5]
AIO, P0[3]
AI, P0[1]
P2[5]
AI, P 2[3]
AI, P2[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, P1[1]
Vss
D+
The CY7C64215 enCoRe III device is available in a 28-pin package which is listed and illustrated in the following table. Every port pin
(labeled with a “P”) is capable of Digital IO. However, Vss and Vdd are not capable of Digital IO.
Table 3. 28-Pin Part Pinout (SSOP)
Pin
No.
1 Power GND Ground connection
2 IO I, M P0[7] Analog column mux input.
3 IO IO,M P0[5] Analog column mux input and column
4 IO IO,M P0[3] Analog column mux input and column
5 IO I,M P0[1] Analog column mux input.
6 IO M P2[5]
7 IO M P2[3] Direct switched capacitor block input.
8 IO M P2[1] Direct switched capacitor block input.
9 IO M P1[7] I2C Serial Clock (SCL).
10 IO M P1[5] I2C Serial Data (SDA).
11 IO M P1[3]
12 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
13 Power GND Ground connection
14 USB D+
15 USB D16 Power Vdd Supply voltage.
17 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
18 IO M P1[2]
19 IO M P1[4]
20 IO M P1[6]
21 IO M P2[0] Direct switched capacitor block input.
22 IO M P2[2] Direct switched capacitor block input.
23 IO M P2[4] External Analog Ground (AGND) input.
24 IO M P0[0] Analog column mux input.
25 IO M P0[2] Analog column mux input and column
26 IO M P0[4] Analog column mux input and column
27 IO M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.
Type
Digital Analog
Name Description
output
output.
output.
output.
CY7C64215 28-Pin enCoRe III Device
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground (Vss).
Document 38-08036 Rev. *C Page 9 of 30
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