CY7C64013C
CY7C64113C
Full-Speed USB (12-Mbps) Function
Full-Speed USB (12-Mbps) Function
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08001 Rev. *B Revised March 3, 2006
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CY7C64013C
CY7C64113C
TABLE OF CONTENTS
1.0 FEATURES .......................................................................................................................................6
2.0 FUNCTIONAL OVERVIEW ..............................................................................................................7
3.0 PIN CONFIGURATIONS ..................................................................................................................9
4.0 PRODUCT SUMMARY TABLES ...................................................................................................10
4.1 Pin Assignments ......................................................................................................................10
4.2 I/O Register Summary ...............................................................................................................10
4.3 Instruction Set Summary ...........................................................................................................12
5.0 PROGRAMMING MODEL ..............................................................................................................13
5.1 14-Bit Program Counter (PC) ....................................................................................................13
5.1.1 Program Memory Organization .......................................................................................................14
5.2 8-Bit Accumulator (A) ................................................................................................................15
5.3 8-Bit Temporary Register (X) ....................................................................................................15
5.4 8-Bit Program Stack Pointer (PSP) ...........................................................................................15
5.4.1 Data Memory Organization .............................................................................................................15
5.5 8-Bit Data Stack Pointer (DSP) .................................................................................................16
5.6 Address Modes .........................................................................................................................16
5.6.1 Data (Immediate) .............................................................................................................................16
5.6.2 Direct ...............................................................................................................................................16
5.6.3 Indexed ...........................................................................................................................................16
6.0 CLOCKING .....................................................................................................................................17
7.0 RESET ............................................................................................................................................17
7.1 Power-On Reset (POR) ............................................................................................................17
7.2 Watchdog Reset (WDR) ............................................................................................................17
8.0 SUSPEND MODE ...........................................................................................................................18
9.0 GENERAL-PURPOSE I/O (GPIO) PORTS ....................................................................................19
9.1 GPIO Configuration Port ...........................................................................................................20
9.2 GPIO Interrupt Enable Ports .....................................................................................................21
10.0 DAC PORT ...................................................................................................................................21
10.1 DAC Isink Registers ................................................................................................................22
10.2 DAC Port Interrupts .................................................................................................................23
11.0 12-BIT FREE-RUNNING TIMER ..................................................................................................23
2
12.0 I
13.0 I
C AND HAPI CONFIGURATION REGISTER ...........................................................................24
2
C-COMPATIBLE CONTROLLER ..............................................................................................25
14.0 HARDWARE ASSISTED PARALLEL INTERFACE (HAPI) ........................................................27
15.0 PROCESSOR STATUS AND CONTROL REGISTER .................................................................28
16.0 INTERRUPTS ...............................................................................................................................29
16.1 Interrupt Vectors ......................................................................................................................30
16.2 Interrupt Latency .....................................................................................................................31
16.3 USB Bus Reset Interrupt .........................................................................................................31
16.4 Timer Interrupt .........................................................................................................................31
16.5 USB Endpoint Interrupts .........................................................................................................31
Document #: 38-08001 Rev. *B Page 2 of 51
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TABLE OF CONTENTS
16.6 DAC Interrupt ..........................................................................................................................31
16.7 GPIO/HAPI Interrupt ...............................................................................................................32
2
16.8 I
17.0 USB OVERVIEW ..........................................................................................................................33
17.1 USB Serial Interface Engine (SIE) ..........................................................................................33
17.2 USB Enumeration ...................................................................................................................33
17.3 USB Upstream Port Status and Control ..................................................................................33
18.0 USB SERIAL INTERFACE ENGINE OPERATION ......................................................................34
18.1 USB Device Address ...............................................................................................................34
18.2 USB Device Endpoints ............................................................................................................35
18.3 USB Control Endpoint Mode Register .....................................................................................35
18.4 USB Non-Control Endpoint Mode Registers ...........................................................................36
18.5 USB Endpoint Counter Registers ............................................................................................36
18.6 Endpoint Mode/Count Registers Update and Locking Mechanism .........................................37
19.0 USB MODE TABLES ...................................................................................................................39
20.0 REGISTER SUMMARY ................................................................................................................43
21.0 SAMPLE SCHEMATIC .................................................................................................................44
C Interrupt .............................................................................................................................32
22.0 ABSOLUTE MAXIMUM RATINGS ...............................................................................................45
23.0 ELECTRICAL CHARACTERISTICS
FOSC = 6 MHZ; OPERATING TEMPERATURE = 0 TO 70°C, V
24.0 SWITCHING CHARACTERISTICS
(fOSC = 6.0 MHz) ...................................................................................... 46
= 4.0V TO 5.25V ........................45
CC
25.0 ORDERING INFORMATION ........................................................................................................48
26.0 PACKAGE DIAGRAMS ................................................................................................................49
Document #: 38-08001 Rev. *B Page 3 of 51
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CY7C64113C
LIST OF FIGURES
Figure 6-1. Clock Oscillator On-Chip Circuit ..........................................................................................17
Figure 7-1. Watchdog Reset (WDR) ......................................................................................................18
Figure 9-1. Block Diagram of a GPIO Pin ..............................................................................................19
Figure 9-2. Port 0 Data ..........................................................................................................................19
Figure 9-3. Port 1 Data ..........................................................................................................................19
Figure 9-4. Port 2 Data ..........................................................................................................................19
Figure 9-5. Port 3 Data ..........................................................................................................................20
Figure 9-6. GPIO Configuration Register...............................................................................................20
Figure 9-7. Port 0 Interrupt Enable.........................................................................................................21
Figure 9-8. Port 1 Interrupt Enable.........................................................................................................21
Figure 9-9. Port 2 Interrupt Enable.........................................................................................................21
Figure 9-10. Port 3 Interrupt Enable.......................................................................................................21
Figure 10-1. Block Diagram of a DAC Pin..............................................................................................22
Figure 10-2. DAC Port Data...................................................................................................................22
Figure 10-3. DAC Sink Register.............................................................................................................22
Figure 10-4. DAC Port Interrupt Enable.................................................................................................23
Figure 10-5. DAC Port Interrupt Polarity ................................................................................................23
Figure 11-1. Timer LSB Register ...........................................................................................................23
Figure 11-2. Timer MSB Register ..........................................................................................................24
Figure 11-3. Timer Block Diagram .........................................................................................................24
Figure 12-1. HAPI/I2C Configuration Register.......................................................................................24
Figure 13-1. I
Figure 13-2. I2C Status and Control Register........................................................................................25
Figure 15-1. Processor Status and Control Register .............................................................................28
Figure 16-1. Global Interrupt Enable Register .......................................................................................29
Figure 16-2. USB Endpoint Interrupt Enable Register ...........................................................................29
Figure 16-3. Interrupt Controller Function Diagram ...............................................................................30
Figure 16-4. GPIO Interrupt Structure....................................................................................................32
Figure 17-1. USB Status and Control Register ......................................................................................34
Figure 18-1. USB Device Address Registers.........................................................................................34
Figure 18-2. USB Device Endpoint Zero Mode Registers......................................................................35
Figure 18-3. USB Non-Control Device Endpoint Mode Registers..........................................................36
Figure 18-4. USB Endpoint Counter Registers ......................................................................................36
Figure 18-5. Token/Data Packet Flow Diagram.....................................................................................38
Figure 24-1. Clock Timing......................................................................................................................47
Figure 24-2. USB Data Signal Timing....................................................................................................47
Figure 24-3. HAPI Read by External Interface from USB Microcontroller..............................................47
Figure 24-4. HAPI Write by External Device to USB Microcontroller.....................................................48
2
C Data Register...............................................................................................................25
Document #: 38-08001 Rev. *B Page 4 of 51
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CY7C64113C
LIST OF TABLES
Table 4-1. Pin Assignments ..................................................................................................................10
Table 4-2. I/O Register Summary .........................................................................................................10
Table 4-3. Instruction Set Summary ......................................................................................................12
Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity ..............................................20
Table 12-1. HAPI Port Configuration .....................................................................................................25
Table 12-2. I
Table 13-1. I
Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions .............................................................27
Table 16-1. Interrupt Vector Assignments .............................................................................................31
Table 17-1. Control Bit Definition for Upstream Port .............................................................................34
Table 18-1. Memory Allocation for Endpoints ......................................................................................35
Table 19-1. USB Register Mode Encoding ...........................................................................................39
Table 19-2. Details of Modes for Differing Traffic Conditions
2
C Port Configuration ........................................................................................................25
2
C Status and Control Register Bit Definitions ..................................................................26
(see Table 19-1 for the decode legend) ........... 41
Document #: 38-08001 Rev. *B Page 5 of 51
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1.0 Features
• Full-speed USB Microcontroller
• 8-bit USB Optimized Microcontroller
— Harvard architecture
— 6-MHz external clock source
— 12-MHz internal CPU clock
— 48-MHz internal clock
• Internal memory
— 256 bytes of RAM
— 8 KB of PROM (CY7C64013C, CY7C64113C)
• Integrated Master/Slave I
• Hardware Assisted Parallel Interface (HAPI) for data transfer to external devices
• I/O ports
— Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per pin (typical)
— An additional GPIO port (Port 3) capable of sinking 12 mA per pin (typical) for high current requirements: LEDs
— Higher current drive achievable by connecting multiple GPIO pins together to drive a common output
— Each GPIO port can be configured as inputs with internal pull-ups or open drain outputs or traditional CMOS outputs
— A Digital to Analog Conversion (DAC) port with programmable current sink outputs is available on the CY7C64113C
devices
— Maskable interrupts on all I/O pins
• 12-bit free-running timer with one microsecond clock ticks
• Watchdog Timer (WDT)
• Internal Power-On Reset (POR)
• USB Specification Compliance
— Conforms to USB Specification, Version 1.1
— Conforms to USB HID Specification, Version 1.1
— Supports up to five user configured endpoints
Up to four 8-byte data endpoints
Up to two 32-byte data endpoints
— Integrated USB transceivers
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70 degrees Celsius
— CY7C64013C available in 28-pin SOIC and 28-pin PDIP packages
— CY7C64113C available in 48-pin SSOP packages
• Industry-standard programmer support
2
C-compatible Controller (100 kHz) enabled through General-Purpose I/O (GPIO) pins
Document #: 38-08001 Rev. *B Page 6 of 51
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CY7C64113C
2.0 Functional Overview
The CY7C64013C and CY7C64113C are 8-bit One Time Programmable microcontrollers that are designed for full-speed USB
applications. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used
for a variety of non-USB embedded applications.
GPIO
The CY7C64013C features 19 GPIO pins to support USB and other applications. The I/O pins are grouped into three ports
(P0[7:0], P1[2:0], P2[6:2], P3[2:0]) where each port can be configured as inputs with internal pull-ups, open drain outputs, or
traditional CMOS outputs. There are 16 GPIO pins (Ports 0 and 1) which are rated at 7 mA typical sink current. Port 3 pins are
rated at 12 mA typical sink current, a current sufficient to drive LEDs. Multiple GPIO pins can be connected together to drive a
single output for more drive current capacity. Additionally, each GPIO can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts share the same “GPIO” interrupt vector.
The CY7C64113C has 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0], P3[7:0])
DAC
The CY7C64113C has four programmable sink current I/O pins (DAC) pins (P4[7,2:0]). Every DAC pin includes an integrated 14kΩ pull-up resistor. When a ‘1’ is written to a DAC I/O pin, the output current sink is disabled and the output pin is driven HIGH
by the internal pull-up resistor. When a ‘0’ is written to a DAC I/O pin, the internal pull-up resistor is disabled and the output pin
provides the programmed amount of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a ‘1’
to the pin.
The sink current for each DAC I/O pin can be individually programmed to one of 16 values using dedicated Isink registers. DAC
bits P4[1:0] can be used as high-current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits
P4[7,2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Multiple DAC pins can be connected together to drive
a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the microcontroller. Also, the interrupt polarity for each DAC I/O pin is individually programmable.
Clock
The microcontroller uses an external 6-MHz crystal and an internal oscillator to provide a reference to an internal PLL-based
clock generator. This technology allows the customer application to use an inexpensive 6-MHz fundamental crystal that reduces
the clock-related noise emissions (EMI). A PLL clock generator provides the 6-, 12-, and 48-MHz clock signals for distribution
within the microcontroller.
Memory
The CY7C64013C and CY7C64113C have 8 KB of PROM.
Power on Reset, Watchdog and Free running Time
These parts include power-on reset logic, a Watchdog timer, and a 12-bit free-running timer. The power-on reset (POR) logic
detects when power is applied to the device, resets the logic to a known state, and begins executing instructions at PROM address
0x0000. The Watchdog timer is used to ensure the microcontroller recovers after a period of inactivity. The firmware may become
inactive for a variety of reasons, including errors in the code or a hardware failure such as waiting for an interrupt that never occurs.
I2C and HAPI Interface
The microcontroller can communicate with external electronics through the GPIO pins. An I
dates a 100-kHz serial link with an external device. There is also a Hardware Assisted Parallel Interface (HAPI) which can be
used to transfer data to an external device.
Timer
The free-running 12-bit timer clocked at 1 MHz provides two interrupt sources, 128-µs and 1.024-ms. The timer can be used to
measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the duration of the event in microseconds. The upper four bits of
the timer are latched into an internal register when the firmware reads the lower eight bits. A read from the upper four bits actually
reads data from the internal register, instead of the timer. This feature eliminates the need for firmware to try to compensate if the
upper four bits increment immediately after the lower eight bits are read.
Interrupts
The microcontroller supports 11 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB Bus
Reset interrupt, the 128-µs (bit 6) and 1.024-ms (bit 9) outputs from the free-running timer, five USB endpoints, the DAC port, the
GPIO ports, and the I
from LOW ‘0’ to HIGH ‘1.’ The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB
controller sends a packet to the USB host. The DAC ports have an additional level of masking that allows the user to select which
DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select which GPIO inputs can cause a
GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is programmable for each pin of the
DAC port. Input transition polarity can be programmed for each GPIO port as part of the port configuration. The interrupt polarity
can be rising edge (‘0’ to ‘1’) or falling edge (‘1’ to ‘0’).
2
C-compatible master mode interface. The timer bits cause an interrupt (if enabled) when the bit toggles
2
C-compatible interface accommo-
Document #: 38-08001 Rev. *B Page 7 of 51
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Logic Block Diagram
6-MHz crystal
PLL
48 MHz
CY7C64013C
CY7C64113C
Clock
Divider
6 MHz
12 MHz
12-MHz
8-bit
CPU
PROM
8 KB
RAM
256 byte
12-bit
Timer
Watchdog
Timer
Power-On
Reset
8-bit Bus
USB
SIE
Interrupt
Controller
GPIO
PORT 0
GPIO
PORT 1
GPIO/
HAPI
PORT 2
GPIO
USB
Transceiver
P0[7:0]
P1[2:0]
P1[7:3]
CY7C64113C only
P2[0,1,7]
P2[2]; Latch_Empty
P2[3]; Data_Ready
P2[4]; STB
P2[5]; OE
P2[6]; CS
High Current
P3[2:0]
Outputs
D+[0]
D–[0]
Upstream
USB Port
PORT 3
DAC
PORT
CY7C64113C only
I2C
Interface
*I2C-compatible interface enabled by firmware through
P2[1:0] or P1[1:0]
P3[7:3]
DAC[0]
DAC[2]
DAC[7]
SCLK
SDATA
Additional
High Current
Outputs
Document #: 38-08001 Rev. *B Page 8 of 51
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3.0 Pin Configurations
TOP VIEW
CY7C64013C
CY7C64113C
XTALOUT
XTALIN
V
REF
GND
P3[1]
D+[0]
D–[0]
P2[3]
P2[5]
P0[7]
P0[5]
P0[3]
P0[1]
P0[6]
CY7C64013C
28-pin SOIC
28
1
2
27
26
3
4
25
5
24
23
6
7
22
8
21
9
20
19
10
11
18
12
17
13
16
15
14
V
CC
P1[1]
P1[0]
P1[2]
P3[0]
P3[2]
GND
P2[2]
P2[4]
P2[6]
V
PP
P0[0]
P0[2]
P0[4]
XTALOUT
XTALIN
V
REF
P1[1]
GND
P3[1]
D+[0]
D–[0]
P2[3]
P2[5]
P0[7]
P0[5]
P0[3]
P0[1]
CY7C64013C
28-pin PDIP
1
28
2
27
26
3
4
25
5
24
23
6
7
22
8
21
9
20
19
10
11
18
12
17
13
16
15
14
V
CC
P1[0]
P1[2]
P3[0]
P3[2]
P2[2]
GND
P2[4]
P2[6]
V
PP
P0[0]
P0[2]
P0[4]
P0[6]
XTALOUT
XTALIN
V
REF
P1[3]
P1[5]
P1[7]
P3[1]
D+[0]
D–[0]
P3[3]
GND
P3[5]
P3[7]
P2[1]
P2[3]
GND
P2[5]
P2[7]
DAC[7]
P0[7]
P0[5]
P0[3]
P0[1]
DAC[1]
CY7C64113C
48-pin SSOP
48
1
2
47
46
3
4
45
5
44
43
6
7
42
8
41
9
40
39
10
11
38
12
37
13
36
35
14
15
34
16
33
17
32
18
31
19
30
29
20
21
28
22
27
23
26
24 25
V
CC
P1[1]
P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
P3[2]
GND
P3[4]
NC
P3[6]
P2[0]
P2[2]
GND
P2[4]
P2[6]
DAC[0]
V
PP
P0[0]
P0[2]
P0[4]
P0[6]
DAC[2]
Document #: 38-08001 Rev. *B Page 9 of 51
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4.0 Product Summary Tables
4.1 Pin Assignments
Table 4-1. Pin Assignments
Name I/O 28-Pin SOIC 28-Pin PDIP 48-Pin SSOP Description
D+[0], D–[0] I/O 6, 7 7, 8 7, 8 Upstream port, USB differential data.
P0 I/O P0[7:0]
10, 14, 11, 15,
12, 16, 13, 17
P1 I/O P1[2:0]
25, 27, 26
P2 I/O P2[6:2]
19, 9, 20, 8,
21
P3 I/O P3[2:0]
23, 5, 24
DAC I/O DAC[7,2:0]
XTAL
IN
XTAL
OUT
V
PP
V
CC
GND IN 4, 22 5, 22 11, 16, 34, 40 Ground.
V
REF
NC 38 No Connect.
IN 2 2 2 6-MHz crystal or external clock input.
OUT 1 1 1 6-MHz crystal out.
IN 18 19 30 Programming voltage supply, tie to ground during
IN 28 28 48 Voltage supply.
IN 3 3 3 External 3.3V supply voltage for the differential data
P0[7:0]
11, 15, 12, 16,
13, 17, 14, 18
P1[2:0]
26, 4, 27
P2[6:2]
20, 10, 21,
9, 23
P3[2:0]
24, 6, 25
P0[7:0]
20, 26, 21, 27,
22, 28, 23, 29
P1[7:0]
6, 43, 5, 44,
4, 45, 47, 46
P2[7:0]
18, 32, 17, 33,
15, 35, 14, 36
P3[7:0]
13, 37, 12, 39,
10, 41, 7, 42
19, 25, 24, 31
GPIO Port 0 capable of sinking 7 mA (typical).
GPIO Port 1 capable of sinking 7 mA (typical).
GPIO Port 2 capable of sinking 7 mA (typical). HAPI
is also supported through P2[6:2].
GPIO Port 3, capable of sinking 12 mA (typical).
DAC Port with programmable current sink outputs.
DAC[1:0] offer a programmable range of 3.2 to 16 mA
typical. DAC[7,2] have a programmable sink current
range of 0.2 to 1.0 mA typical.
normal operation.
output buffers and the D+ pull-up.
4.2 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port. Indexed I/O Write
(IOWX) adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to
the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X.
All undefined registers are reserved. It is important not to write to reserved registers as this may cause an undefined operation
or increased current consumption during operation. When writing to registers with reserved bits, the reserved bits must be written
with ‘0.’
Table 4-2. I/O Register Summary
Register Name I/O Address Read/Write Function Page
Port 0 Data 0x00 R/W GPIO Port 0 Data 19
Port 1 Data 0x01 R/W GPIO Port 1 Data 19
Port 2 Data 0x02 R/W GPIO Port 2 Data 19
Port 3 Data 0x03 R/W GPIO Port 3 Data 20
Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 21
Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 21
Port 2 Interrupt Enable 0x06 W Interrupt Enable for Pins in Port 2 21
Port 3 Interrupt Enable 0x07 W Interrupt Enable for Pins in Port 3 21
Document #: 38-08001 Rev. *B Page 10 of 51
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Table 4-2. I/O Register Summary (continued)
Register Name I/O Address Read/Write Function Page
GPIO Configuration 0x08 R/W GPIO Port Configurations 20
HAPI and I2C Configuration 0x09 R/W HAPI Width and I2C Position Configuration 24
USB Device Address A 0x10 R/W USB Device Address A 34
EP A0 Counter Register 0x11 R/W USB Address A, Endpoint 0 Counter 35
EP A0 Mode Register 0x12 R/W USB Address A, Endpoint 0 Configuration 34
EP A1 Counter Register 0x13 R/W USB Address A, Endpoint 1 Counter 35
EP A1 Mode Register 0x14 R/W USB Address A, Endpoint 1 Configuration 35
EP A2 Counter Register 0x15 R/W USB Address A, Endpoint 2 Counter 35
EP A2 Mode Register 0x16 R/W USB Address A, Endpoint 2 Configuration 35
USB Status & Control 0x1F R/W USB Upstream Port Traffic Status and Control 34
Global Interrupt Enable 0x20 R/W Global Interrupt Enable 29
Endpoint Interrupt Enable 0x21 R/W USB Endpoint Interrupt Enables 29
Timer (LSB) 0x24 R Lower 8 Bits of Free-running Timer (1 MHz) 23
Timer (MSB) 0x25 R Upper 4 Bits of Free-running Timer 24
WDT Clear 0x26 W Watchdog Timer Clear 18
2
C Control & Status 0x28 R/W I2C Status and Control 25
I
2
C Data 0x29 R/W I2C Data 25
I
DAC Data 0x30 R/W DAC Data 22
DAC Interrupt Enable 0x31 W Interrupt Enable for each DAC Pin 23
DAC Interrupt Polarity 0x32 W Interrupt Polarity for each DAC Pin 23
DAC Isink 0x38-0x3F W Input Sink Current Control for each DAC Pin 22
Reserved 0x40 Reserved
EP A3 Counter Register 0x41 R/W USB Address A, Endpoint 3 Counter 35
EP A3 Mode Register 0x42 R/W USB Address A, Endpoint 3 Configuration 34
EP A4 Counter Register 0x43 R/W USB Address A, Endpoint 4 Counter 35
EP A4 Mode Register 0x44 R/W USB Address A, Endpoint 4 Configuration 35
Reserved 0x48 Reserved
Reserved 0x49 Reserved
Reserved 0x4A Reserved
Reserved 0x4B Reserved
Reserved 0x4C Reserved
Reserved 0x4D Reserved
Reserved 0x4E Reserved
Reserved 0x4F Reserved
Reserved 0x50 Reserved
Reserved 0x51 Reserved
Processor Status & Control 0xFF R/W Microprocessor Status and Control Register 26
Document #: 38-08001 Rev. *B Page 11 of 51
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4.3 Instruction Set Summary
Refer to the CYASM Assembler User’s Guide for more details.
Table 4-3. Instruction Set Summary
MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles
HALT 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50 - 5F 10 JC addr C0-CF 5
JMP addr 80-8F 5 JNC addr D0-DF 5
CALL addr 90-9F 10 JACC addr E0-EF 7
JZ addr A0-AF 5 INDEX addr F0-FF 14
JNZ addr B0-BF 5
Document #: 38-08001 Rev. *B Page 12 of 51
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CY7C64113C
5.0 Programming Model
5.1 14-Bit Program Counter (PC)
The 14-bit program counter (PC) allows access to up to 8 KB of PROM available with the CY7C64x13C architecture. The top 32
bytes of the ROM in the 8 Kb part are reserved for testing purposes. The program counter is cleared during reset, such that the
first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes
the application (see Interrupt Vectors on page 30).
The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte
“page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” causes the assembler to insert
XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally
need to insert a NOP followed by an XPAGE to execute correctly.
The address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack during a RETI instruction. Only the program counter is restored during a RET instruction.
The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from
location 0x00 and up.
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5.1.1 Program Memory Organization
after reset Address
14-bit PC 0x0000 Program execution begins here after a reset
0x0002 USB Bus Reset interrupt vector
0x0004 128-µs timer interrupt vector
0x0006 1.024-ms timer interrupt vector
0x0008 USB address A endpoint 0 interrupt vector
0x000A USB address A endpoint 1 interrupt vector
0x000C USB address A endpoint 2 interrupt vector
0x000E USB address A endpoint 3 interrupt vector
CY7C64013C
CY7C64113C
0x0010 USB address A endpoint 4 interrupt vector
0x0012 Reserved
0x0014 DAC interrupt vector
0x0016 GPIO interrupt vector
0x0018
0x001A
2
I
C interrupt vector
Program Memory begins here
0x1FDF 8 KB (-32) PROM ends here (CY7C64013C, CY7C64113C)
Document #: 38-08001 Rev. *B Page 14 of 51
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5.2 8-Bit Accumulator (A)
The accumulator is the general-purpose register for the microcontroller.
5.3 8-Bit Temporary Register (X)
The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed
operations based on the value in X. Refer to Section 5.6.3 for additional information.
5.4 8-Bit Program Stack Pointer (PSP)
During a reset, the program stack pointer (PSP) is set to 0x00 and “grows” upward from this address. The PSP may be set by
firmware, using the MOV PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and
RETI instructions under firmware control. The PSP is not readable by the firmware.
During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is stored in the memory addressed by the PSP, then the PSP is incremented. The second
byte is stored in memory addressed by the PSP, and the PSP is incremented again. The overall effect is to store the program
counter and flags on the program “stack” and increment the PSP by two.
The Return from Interrupt (RETI) instruction decrements the PSP, then restores the second byte from memory addressed by the
PSP. The PSP is decremented again and the first byte is restored from memory addressed by the PSP. After the program counter
and flags have been restored from stack, the interrupts are enabled. The overall effect is to restore the program counter and flags
from the program stack, decrement the PSP by two, and reenable interrupts.
The Call Subroutine (CALL) instruction stores the program counter and flags on the program stack and increments the PSP by
two.
The Return from Subroutine (RET) instruction restores the program counter but not the flags from the program stack and decrements the PSP by two.
5.4.1 Data Memory Organization
The CY7C64x13C microcontrollers provide 256 bytes of data RAM. Normally, the SRAM is partitioned into four areas: program
stack, user variables, data stack, and USB endpoint FIFOs. The following is one example of where the program stack, data stack,
and user variables areas could be located.
After reset Address
8-bit DSP 8-bit PSP 0x00 Program Stack Growth
(Move DSP
8-bit DSP
Notes:
1. Refer to Section 5.5 for a description of DSP.
2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 18-1.
[1]
)
user selected Data Stack Growth
User variables
USB FIFO space for five endpoints
0xFF
[2]
Document #: 38-08001 Rev. *B Page 15 of 51
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5.5 8-Bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads
data from the memory location addressed by the DSP, then post-increments the DSP.
During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM
(address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed
at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB
endpoint FIFOs.
For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated
to USB FIFOs. The memory requirements for the USB endpoints are described in Section 18.2. Example assembly instructions
to do this with two device addresses (FIFOs begin at 0xD8) are shown below:
MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less)
SWAP A,DSP ; swap accumulator value into DSP register
5.6 Address Modes
The CY7C64013C and CY7C64113C microcontrollers support three addressing modes for instructions that require data
operands: data, direct, and indexed.
5.6.1 Data (Immediate)
“Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the
instruction that loads A with the constant 0xD8:
• MOV A,0D8h
This instruction requires two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction is the constant “0xD8.” A constant may be referred to by name if a prior “EQU”
statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:
• DSPINIT: EQU 0D8h
• MOV A,DSPINIT
5.6.2 Direct
“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10:
• MOV A,[10h]
Normally, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler
source code. As an example, the following code is equivalent to the example shown above:
• buttons: EQU 10h
• MOV A,[buttons]
5.6.3 Indexed
“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. Normally, the constant is the “base” address
of an array of data and the X register contains an index that indicates which element of the array is actually addressed:
•array: EQU 10h
•MOV X,3
• MOV A,[X+array]
This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.
Document #: 38-08001 Rev. *B Page 16 of 51
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