CYPRESS CY7C63612, CY7C63613 User Manual
PRELIMINARY
,
CY7C63612/13
CY7C63612/13
Low-Speed, Low I/O
1.5 Mbps USB Controller
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 26
1999
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TABLE OF CONTENTS
1.0 FEATURES .....................................................................................................................................5
2.0 FUNCTIONAL OVERVIEW .............................................................................................................6
3.0 PIN ASSIGNMENTS .......................................................................................................................8
4.0 PROGRAMMING MODEL ...............................................................................................................8
4.1 14-bit Program Counter (PC) ...........................................................................................................8
4.2 8-bit Accumulator (A) .......................................................................................................................8
4.3 8-bit Index Register (X) ....................................................................................................................8
4.4 8-bit Program Stack Pointer (PSP) ..................................................................................................8
4.5 8-bit Data Stack Pointer (DSP) ........................................................................................................9
4.6 Address Modes ................................................................................................................................9
4.6.1 Data ........................................................................................................................................................9
4.6.2 Direct ......................................................................................................................................................9
4.6.3 Indexed ................................................................................................................................................... 9
5.0 INSTRUCTION SET SUMMARY ...................................................................................................10
6.0 MEMORY ORGANIZATION ..........................................................................................................11
6.1 Program Memory Organization ......................................................................................................11
6.2 Data Memory Organization ............................................................................................................12
6.3 I/O Register Summary ................................................................................................................... 1 3
7.0 CLOCKING ....................................................................................................................................1 4
8.0 RESET ...........................................................................................................................................1 4
8.1 Power-On Reset (POR) .................................................................................................................14
8.2 Watch Dog Reset (WDR) ............................................................................................................... 1 5
9.0 GENERAL PURPOSE I/O PORTS ...............................................................................................15
9.1 GPIO Interrupt Enable Ports ..........................................................................................................16
9.2 GPIO Configuration Port ................................................................................................................17
10.0 USB SERIAL INTERFACE ENGINE (SIE) .................................................................................1 7
10.1 USB Enumeration ........................................................................................................................1 8
10.2 PS/2 Operation .............. ............... ......................... ............... ............... .............. ...................... ....18
10.3 USB Port Status and Control .......................................................................................................18
11.0 USB DEVICE ...............................................................................................................................1 9
11.1 USB Ports .................................................................................................................................... 1 9
11.2 Device Endpoints (3) ...................................................................................................................19
12.0 12-BIT FREE-RUNNING TIMER .................................................................................................20
12.1 Timer (LSB) .................................................................................................................................2 0
12.2 Timer (MSB) ................................................................................................................................ 2 0
13.0 PROCESSOR STATUS AND CONTROL REGISTER ......................................... ............... .......21
14.0 INTERRUPTS ..............................................................................................................................2 1
14.1 Interrupt Vectors ..........................................................................................................................22
14.2 Interrupt Latency ..........................................................................................................................22
14.2.1 USB Bus Reset Interrupt ....................................................................................................................22
14.2.2 Timer Interrupt ....................................................................................................................................23
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14.2.3 USB Endpoint Interrupts .....................................................................................................................23
14.2.4 DAC Interrupt ......................................................................................................................................23
14.2.5 GPIO Interrupt ....................................................................................................................................23
15.0 TRUTH TABLES .........................................................................................................................23
16.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................2 6
17.0 DC CHARACTERISTICS ............................................................................................................27
18.0 SWITCHING CHARACTERISTICS .............................................................................................28
19.0 ORDERING INFORMATION .......................................................................................................30
20.0 PACKAGE DIAGRAM .................................................................................................................30
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LIST OF FIGURES
Figure 6-1. Program Memory Space with Interrupt Vector Table .........................................................11
Figure 7-1. Clock Oscillator On-chip Circuit ..........................................................................................14
Figure 8-1. Watch Dog Reset (WDR) ...................................................................................................15
Figure 9-1. Block Diagram of a GPIO Line ...........................................................................................15
Figure 9-2. Port 0 Data 0x00h (read/write) ...........................................................................................16
Figure 9-3. Port 1 Data 0x01h (read/write) ...........................................................................................16
Figure 9-4. Port 2 Data 0x02h (read/write) ...........................................................................................16
Figure 9-5. Port 3 Data 0x03h (read/write) ...........................................................................................16
Figure 9-6. DAC Port Data 0x30h (read/write) ......................................................................................16
Figure 9-7. Port 0 Interrupt Enable 0x04h (write only) ..........................................................................16
Figure 9-8. Port 1 Interrupt Enable 0x05h (write only) ..........................................................................16
Figure 9-9. Port 2 Interrupt Enable 0x06h (write only) ..........................................................................16
Figure 9-10. Port 3 Interrupt Enable 0x07h (write only) ........................................................................ 16
Figure 9-11. GPIO Configuration Register 0x08h (write only) ..............................................................17
Figure 10-1. USB Status and Control Register 0x1Fh ..........................................................................18
Figure 11-1. USB Device Address Register 0x10h (read/write) ...........................................................19
Figure 11-2. USB Device EPA0 Mode Register 0x12h (read/write) .....................................................19
Figure 11-3. USB Device Endpoint Mode Registers 0x14h, 0x16h (read/write) ...................................19
Figure 11-4. USB Device Counter Registers 0x11h, 0x13h, 0x15h (read/write) ..................................20
Figure 12-1. Timer Register 0x24h (read only) ..................................................................................... 20
Figure 12-2. Timer Register 0x25h (read only) ..................................................................................... 20
Figure 12-3. Timer Block Diagram ........................................................................................................20
Figure 13-1. Processor Status and Control Register 0xFFh .................................................................21
Figure 14-1. Global Interrupt Enable Register 0x20h (read/write) ........................................................21
Figure 14-2. USB End Point Interrupt Enable Register 0x21h (read/write) ..........................................22
Figure 18-1. Clock Timing .....................................................................................................................28
Figure 18-2. USB Data Signal Timing ...................................................................................................29
Figure 18-3. Receiver Jitter Tolerance .... ............... ............... .............. ............... ............... ...................29
Figure 18-4. Differential to EOP Transition Skew and EOP Width .......................................................29
Figure 18-5. Differential Data Jitter .......................................................................................................30
LIST OF TABLES
Table 6-1. I/O Register Summary ........................................................................................................13
Table 14-1. Interrupt Vector Assignments ...........................................................................................22
Table 15-1. USB Register Mode Encoding ..........................................................................................23
Table 15-2. Decode tab le f or
Table 15-3
: “Details of M odes for Differing Traffic Conditions” .. ............24
Table 15-3. Details of Modes for Differing Traffic Conditions ..............................................................25
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1.0 Features
• Low-cost solution for low-speed applications with low I/O requirements such as mice, gamepads, a nd joystick applications
• USB Specification Compliance
—Conforms to USB Specificat ion, Version 1.1
—Conforms to USB HID Specification, Version 1.1
—Supports 1 device address and 3 data endpoints
—Integrated USB transceiver
• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator
—12-MHz internal CPU clock
• Internal memory
—256 bytes of RAM
—6 Kbytes of EPROM (CY7C63612)
—8 Kbytes of EPROM (CY7C63613)
• Interface can aut o-configure to operate as PS2 or USB
• I/O port
—12 General-Purpose I/O (GPIO) pins (Port 0 to 2) capable of sinking 7 mA per pin (t ypical)
—Four GPIO pins (Port 3) capable of sinking 12 mA per pin (typical) wh ich can drive LEDs
—Higher current drive is available by connecting multi ple GPIO pins together to drive an commo n output
—Eac h GPIO port can be configured as input s with internal pull- ups or open drain outputs or tradi tional CMOS outputs
—M askable interrupt s on all I/O pi ns
• 12-bit free-running timer with one microsecond clock ticks
• Watch D o g T i m e r (WDT )
• Internal Power-On Reset (POR)
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5V DC
• Operating temperature from 0 to 70 degrees Celsius
• CY7C63612/13 available in 24-pin SOIC packages for production
• Industry-sta ndard programmer support
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2.0 Functional Overview
The CY7C63612/13 are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been optimized
specifica ll y for USB operation s, although the microcontrollers can be used for a variety of non-USB embedded applications .
The CY7C63612/13 features 16 General-Purpose I/O (GPIO) pins to support USB and other applications. The I/O pins are
grouped int o three ports (P ort 0, 1, and 3) wher e each port can be conf igure d as input s wit h internal pul l-up s, open dr ain out puts,
or tradi ti onal CMOS outputs . 12 GPIO pins (Ports 0 and 1) are rated at 7 mA typical sink current. There are 4 GPIO pins (Port 3)
which are rat ed at 12 mA typical sink current , which allows these pins to drive LEDs . Multiple GPIO pins ca n be connected toget her
to drive a single outp ut f or more driv e current capac ity. Addi tion ally, each I/O pin can be used to generate a GPIO interrupt to the
microcontroller. Note the GPIO interrupts all share the same “GPIO” interrupt vector.
The Cypress microc ontroll ers use an ex ternal 6-MHz cer amic resonato r to provide a re ferenc e to an internal clo ck generat or . This
clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that
remain internal to the microcontroller.
The CY7C63612/13 are of fered with two EPROM options t o maximize f lexib ility and mini mize cost . The CY7C63612 has 6 Kb ytes
of EPROM. The CY7C63613 has 8 Kbytes of EPROM.
These parts include power-on reset logi c, a watch dog timer, a vect ored interrupt control ler, and a 12-bi t free-running timer. The
Po wer-On Reset (PO R) lo gic det ects when p ow er is app lied to th e de vi ce , res ets t he logi c to a k nown stat e, an d be gins e xecuting
instructions at EPROM address 0x0000h. The watch dog timer can be used to ensure the firmware never gets stalled for more
than approximately 8 ms. The firmware can get stalled for a variety of r easons, including errors in the code or a hardware failur e
such as waiting for an interrupt that never occurs. The firmware should clear the watchdog timer periodically. If the watch dog
timer is not cleared for approximately 8 ms, the microcontroller wil l generate a hardware wa tch dog reset.
The microcontr oller s upports eight maskab le inter rupts in th e vector ed interrupt c ontroll er. Interrupt sour ces incl ude the USB BusReset, the 128-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports.
The timer bits cause an interrupt (if enabled) when the bit toggles from LOW “0” to HIGH “1”. The USB endpoints interrupt after
either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that
allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select
which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is
programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port
configuration. The interrupt polarity can be either rising edge (“0” to “1”) or falling edge (“1” to “0”).
The free-runn ing 12-bit tim er clocked at 1 MHz pro vides two int errupt sources as noted above (128-µs and 1.024-ms). The timer
can be used to measur e the dur ation of an ev ent under firmware control by read ing the timer twice: once at the start of the event ,
and once after the event is complete. The differ ence between the two readings indicates the duration of the event measured in
microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits.
A read from t he u pper four bits actually reads dat a from t he internal r egist er , inst ead o f the timer. This feature elimi nat es the n eed
for fi rmware to attempt to compensate if the upper four bits happened to increment right aft er t he lower 8 bits are read.
The CY7C63612/13 include an integrated USB serial interface engine (SIE) that supports the integrated peripherals. The hardware supports one USB device address with three endpoints. The SIE allows the USB host to communicate with the function
integrated into the microcontroller.
Finally, the CY7C63612/13 support PS/2 operation . With appr opriate fi rmware the D+ and D– USB pins can al so be used as PS/
2 clock and data signals. Products u tilizing these devices can be used for USB and/or PS/2 operation with appropriate firmware.
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Logic Block Diagram
6-MHz ceramic resonator
OSC
12 MHz
4/6/8 Kbyte
6 MHz
12-MHz
8-bit
CPU
EPROM
RAM
256 byte
8-bit Bus
PRELIMINARY
USB
Transceiver
USB
SIE
Interrupt
Controller
D+
D–
USB
PS/2
PORT
Pin Configuration
CY7C63612/13
24-pin SO IC
1
24 V
2
23
3
22
4
21
5
20
6
19
7
18
17
9
16
10815
11
14
12
13
TOP VIEW
CC
V
SS
P3[6]
P3[4]
P1[2]
P1[0]
P0[6]
P0[4]
P0[2]
P0[0]
XTAL
XTAL
P3[7]
P3[5]
P1[3]
P1[1]
P0[7]
P0[5]
P0[3]
P0[1]
V
Vss
D+
D–
PP
CY7C63612/13
OUT
IN
12-bit
Timer
Watch Do g
Timer
Power-o n
Reset
GPIO
PORT 0
GPIO
PORT 1
GPIO
PORT 2
GPIO
PORT 3
DAC
PORT
P0[0]
P0[7]
P1[0]
P1[7]
P2[0]
P2[7]
P3[0]
P3[7]
DAC[0]
DAC[7]
See Note 1
High Current
Outputs
Note:
1. CY7C63612/13 is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 16
for firmware code needed for unused GPIO pins.
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3.0 Pin Assignments
CY7C63613
Name I/O
D+, D– I/O 1,2 USB differential data; PS/2 clock and data signals
P0[7:0]
I/O
P1[3:0]
7,18,8,17,
9,16,10,15
5,20,6,19 GPIO Port 1 capab le of sinking 7 mA (typical). P1[ 7:4] not bonded out on
I/O
P2
n/a GPIO Port 2 not bonded out on CY7C63612/13. See note on page 16 for firm-
I/O
P3[7:4]
3,22,4,21 GPIO Port 3 capab le of sinking 12 mA (typical). P3[ 3:0] not bonded out on
I/O
DAC I/O n/a DAC I /O Port not bonded out on CY7C63612/13. See not e on page 16 for firm-
XTAL
XTAL
V
PP
V
CC
IN 13 6-MHz ceramic resonator or external clock input
IN
OUT 14 6-MHz ceramic resonator
OUT
11 Pr ogramming voltage supply, ground for normal operation
24 Voltage supply
Vss 12,23 Ground
Description24-Pin
GPIO port 0 capable of sinking 7 mA (typical)
CY7C63612/13. See not e on page 16 for f irmware code nee ded for unused pins .
ware code needed for unused pins.
CY7C63612/13. See not e on page 16 for f irmware code nee ded for unused pins .
ware code needed for unused pins.
4.0 Programming Model
4.1 14-bit Program Counter (PC)
The 14-bit Pr ogra m Counte r (PC) a llo ws acc ess f or up to 8 k ilob ytes of EPR OM usi ng the CY7 C636xx archi tectur e . The pr ogram
counter is cleare d during r ese t, suc h that the fi rst instruc tion ex ec uted af te r a res et is at addr ess 0 x0000h. T his i s typi call y a jump
instruction to a res et handler that initializes the application.
The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are inc remented by executing an XPAGE instruction. As a result , the last i nstruction executed within a 256-b yte
“page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON ” will cause the assembler to
insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally
need to insert a NOP follow ed by an XPAGE for correct execution.
The program counte r of t he ne xt i nstruct ion t o be executed, carry flag, and zer o fla g are sa v ed a s two b ytes on the p rogr am st ack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack only during a RETI instruction.
Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading
SRAM from location 0x00 and up.
4.2 8-bit Accumulator (A)
The accumulator is the general purpose, do everything register in the architecture where results are usually calculated.
4.3 8-bit Index Register (X)
The index regi ster “X” is av ailab le to the firmware as an auxi liary accumul ator . The X register also allows the processo r to perform
indexed operations by loading an inde x value into X.
4.4 8-bit Program Stac k Pointer ( PSP)
During a rese t, the Progr am Stack P ointer (PSP) is set to z ero. This means the program “stack ” starts at RAM address 0x00 and
“grows” upw ard from there . Note the progr am stac k pointe r is directl y address able unde r firmware control , using the MO V PSP,A
instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware
control.
During an interrupt ac knowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is
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incremented. The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again.
The net effect is to store the pro gram counter and flags on the program “stack” and increment the program stack pointer by tw o.
The Return From I nterrupt (RETI) instruct ion dec rements t he pro gram st ac k point er , then res tores t he second b yt e from memory
addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed
by the PSP. After the pr og ram cou nte r and flags ha v e be en r estor ed from st ac k, the inte rrupts are en ab led. The eff e ct i s to res tore
the program counter and flags from the program stack, decrement the program stack pointer b y two, and re-enable interrupts.
The Call Subrout ine (CALL) instruct ion stores the progr am counter and flags on t he program stac k and incremen ts the PSP by two .
The Return From Subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decre-
ments the PSP by two .
4.5 8-bit Data Stack Pointer (DSP)
The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction wi ll pr e-decr ement the DSP, then write data t o the memory l ocatio n address ed b y the DSP. A POP instruction will read
data from the memory location addressed by the DSP, then post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will w r ite d a ta a t t h e to p of
the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB
applications, this works fi ne and is not a problem. For USB applicati ons, it is strongly recommen ded that the DSP is loaded after
reset just below the USB DMA buffers .
4.6 Address Modes
The CY7C63612/13 microcontrollers support three addressing modes for instructions that require data operands: data, direct,
and indexed.
4.6.1 Data
The “Data” add res s mode refers to a data operand tha t is a ctual ly a con st ant encod ed i n the i nstruct ion. As an exa mple , cons ide r
the instruction that loads A with the constant 0xE8h:
• MOV A,0E8h
This instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior
“EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown
above:
• DSPINIT: EQU 0E8h
• MOV A,DSPINIT
4.6.2 Direct
“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10h:
• MOV A, [10h]
In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the
assembl er source code. As an example, the fol lowing code is equivalent to the exampl e shown above:
• buttons: EQU 10h
• MOV A,[buttons]
4.6.3 Indexed
“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the
“base” address of an array of data and the X register will contain an index that indicates which element of the array is actually
addressed:
• array: EQU 10h
•MOV X,3
• MOV A,[x+array]
This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The four th
element would be at add ress 0x13h.
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