CYPRESS CY7C63411, CY7C63412, CY7C63413, CY7C63511, CY7C63512 User Manual

CY7C63411/12/13

CY7C63511/12/13

CY7C63612/13

CY7C63411/12/13
CY7C63511/12/13
CY7C63612/13
Low-speed USB Peripheral Controller

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-08027 Rev. ** Revised June 4, 2002

FOR

FOR

CY7C63411/12/13

CY7C63511/12/13

CY7C63612/13

TABLE OF CONTENTS

1.0 FEATURES .....................................................................................................................................5

2.0 FUNCTIONAL OVERVIEW ...... ...................... ........................ ..................... .. ..................................6

3.0 PIN ASSIGNMENTS .......................................................................................................................8

4.0 PROGRAMM I N G M OD E L ..... .. .. .............. .. ............. .. ............. ... ............. .. ............. ... ............. .. .........8

4.1 14-bit Program Counter (PC) ................. ..........................................................................................8

4.2 8-bit Accumulator (A) .......................................................................................................................8

4.3 8-bit Index Register (X) ................................................ .................... .................... ............................8

4.4 8-bit Program Stack Pointer (PSP) ..................................................................................................9

4.5 8-bit Data Stack Pointer (DSP) ........................................................................................................9

4.6 Address Modes ........................................................ ................................................... .....................9

4.6.1 Data ........................................................................................................................................................9

4.6.2 Direct ......................................................................................................................................................9

4.6.3 Indexed ...................................................................................................................................................9

5.0 INSTRUCTION SET SUMMARY ........................................................ .. .. ............................... .. .. .. ..11

6.0 MEMORY ORGANIZATION ..........................................................................................................12

6.1 Program Memory Organization ................................ ........................... .. .........................................12

6.2 Data Memor y O r ga n ization ............. .. .. ............. .............. .. ............. .. .............. .. ............. .. ................13

6.3 I/O Registe r S u m ma ry ........................ .. .............. .. ............. .. ............. ... ............. ............. ................14

7.0 CLOCKING ....................................................................................................................................15

8.0 RESET ................................................................. .............................. ............................................15

8.1 Power-On Reset (POR) .................................................................................................................15

8.2 Watch Dog Res e t (WDR) ........... .. .............. .. ............. .. .............. .. .. ............. ... ............. .. ..................16

9.0 GENERAL PURPOSE I/O PORTS ...............................................................................................16

9.1 GPIO Interrupt Enable Ports ..........................................................................................................17

9.2 GPIO Configuration Port ................................................................................................................18

10.0 DAC PORT ..................................................................................................................................19

10.1 DAC Port Int e rrupts ............... ............. ... ............. .. ............. .. .............. .. .. ............. ... ......................19

10.2 DAC Isink Re g i sters .. ............. .. .............. .. ............. .. ............. ... ............. .. ............. ... ......................20

11.0 USB SERIAL IN T E R F A CE ENGINE (SI E ) ................... .. ............. .. .............. .. ............. .. ..............20

11.1 USB Enum e ra tion ....... .. ............. ... ............. .. ............. .............. .. ............. .. .............. .. ....................20

11.2 PS/2 Opera t io n .... ... ............. .. ............. ... ............. .. ............. .. .............. .. ............. .. .........................20

11.3 USB Port Status and Control .......................................................................................................21

12.0 USB DEVICE ....... ... ............. .. ............. ... ............. .. ............. .. .............. .. ............. .. .........................21

12.1 USB Ports ............... .. ............. .. .............. .. .. ............. .. .............. .. ............. .. .............. ......................21

12.2 Device Endpoints (3) .................................................. ........................ .. ........................ ...............21

13.0 12-BIT FREE-RUNNING TIMER ............................................................ ............................. ........22

13.1 Timer (LSB) .................................................................................................................................22

13.2 Timer (MSB) ................................................................................................................................22

14.0 PROCESSOR STATUS AND CONTROL REGISTER ................................. .. ............................23

15.0 INTERRUPTS ..............................................................................................................................24

15.1 Interrupt Vectors ..........................................................................................................................24

Document #: 38-08027 Rev. ** Page 2 of 36

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CY7C63511/12/13

CY7C63612/13

15.2 Interrupt Latency ..........................................................................................................................25

15.2.1 USB Bus Reset Interrupt ....................................................................................................................25

15.2.2 Timer Interrupt ................................. ...... ....... ...... ....... ...... ...... ....... ...... ................................................25

15.2.3 USB Endpoint Interrupts .....................................................................................................................25

15.2.4 DAC Interrupt ............... ....... ...... ....... ...... ....... ...... ....... ...... ...... .............................................................25

15.2.5 GPIO Interrupt ....................................................................................................................................25

16.0 TRUTH TABLES .........................................................................................................................26

17.0 ABSOLUTE M A X I M U M R A T INGS ......... ............. .. .. .............. .. ............. .. .............. .. ............. .. .....29

18.0 DC CHARACTERISTICS ............................................................................................................30

19.0 SWITCHING CHARACTERISTICS ............................................... .. ............................................31

20.0 ORDERIN G IN F O RMATION .............. ... ............. .. .. ............. ... ............. .. ............. ... ............. .. .......33

21.0 PACKAGE DIAGRAMS ................................. ................................. ............................................34

Document #: 38-08027 Rev. ** Page 3 of 36

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LIST OF FIGURES

Figure 6-1. Pro g ra m M e mo ry Space with In te rrupt Vector T ab le ........... .............. .. ............. ............. ... . 12

Figure 7-1. Clo ck Oscillator On-c h i p Ci r cu i t ..... .. ............. .. .............. .. ............. .. .............. .. .....................15

Figure 8-1. Watch Dog Reset (W D R ) ... .. ............. .. .............. .. ............. .. .............. .. ............. .. .................16

Figure 9-1. Blo ck D ia g ra m of a GPIO Line .... .. ............. .. ............. ... ............. .. ............. ... .. ............. ........ 16

Figure 9-2. Por t 1 Data 0x01h (rea d/ w ri te ) .......................... .. ............. .. .............. .. .. ............. .. ...............17

Figure 9-3. Por t 2 Data 0x02h (rea d/ w ri te ) .......................... .. ............. .. .............. .. .. ............. .. ...............17

Figure 9-4. Por t 3 Data 0x03h (rea d/ w ri te ) .......................... .. ............. .. .............. .. .. ............. .. ...............17

Figure 9-5. DAC Port Data 0x30h (read/write) ........................................................... ........................... 17

Figure 9-6. Por t 0 Int e rr u p t E na b le 0x04h (writ e on ly ) ......... ............. .. ............. ... ............. .. ............. .. . ...17

Figure 9-7. Por t 1 Int e rr u p t E na b le 0x05h (writ e on ly ) ......... ............. .. ............. ... ............. .. ............. .. . ...17

Figure 9-8. Por t 2 Int e rr u p t E na b le 0x06h (writ e on ly ) ......... ............. .. ............. ... ............. .. ............. .. . ...17

Figure 9-9. Por t 3 Int e rr u p t E na b le 0x07h (writ e on ly ) ......... ............. .. ............. ... ............. .. ............. .. . ...17

Figure 10-1. Bl o ck D ia g ra m o f D A C P or t ......... .. ............. .. .............. .. ............. .. ... ............. .. ...................19

Figure 10-2. DAC Port Data 0x30h (read/write) ............................................................ .. ......................19

Figure 10-3. DAC Port Interrupt Enable 0x31h (write only) .......................................... ........................19

Figure 10-4. DAC Port Interrupt Polarity 0x32h (write o nly) .................................. ...................... .........19

Figure 10-5. DAC Port Isink 0x3 8 h to 0 x3 F h (write only) .......... ............. ... ............. .. ............. ... ............ 20

Figure 11-1. USB Status and Control Register 0x1Fh ..........................................................................21

Figure 12-1. USB Device Address Register 0x10h (read/write) ...........................................................21

Figure 12-2. USB Device Counter Registers 0x11h, 0x13h, 0x15h (read/write) ................ ..................22

Figure 13-1. Ti m e r B lo c k D ia g r a m .......... .. ............. ... ............. .. ............. .. .............. .. ............. .. ...............23

Figure 15-1. USB End Point Interrupt Enable Register 0x21h (read/write) ..........................................24

Figure 19-1. Cl o ck T im in g ................ .. .............. .. ............. .. .............. .. .. ............. ... ............. .. ................... 32

Figure 19-2. USB Data Signal Timing ...................................................................................................32

Figure 19-3. Rec e iver Jitter Tole ra n c e ..... .. .............. .. ............. .. .. .............. .. ............. .. .............. ............ 32

Figure 19-4. Di ff erential to EOP T ra n sition Skew and E O P Wid t h . ............. .. ............. ... ............. .. ........ 33

Figure 19-5. Differential Data Jitter ....................................................................................................... 33

LIST OF TABLES

Table 6-1. I/O Register Summary ........................................................................................................ 14

Table 15-1. Interrupt Vector Assignments ...........................................................................................24

Table 16-1. USB Register Mode Encoding ................................................. .. .......................... .............26

Table 16-2. Decode table forTable 16-3: “Details of Modes for Differing Traffic Conditions” ..............27

Table 16-3. Details of Modes for Differing Traffic Co nditions ..............................................................28

Document #: 38-08027 Rev. ** Page 4 of 36

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CY7C63612/13

1.0 Features

• Low-cost solution for low-speed applications such as mice, gamepads, keyboards, joystick and others

• USB Specification Compliance
—Conforms to USB Specification, Versions 1.1 and 2.0

—Conforms to USB HID Specification, Version 1.1
—Supports 1 device address and 3 data endpoints
—Integrated USB transceiver

• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator
—12-MHz internal CPU clock

• Internal memory
—256 bytes of RAM
—4 Kbytes of EPROM (CY7C63411, CY7C63511)
—6 Kbytes of EPROM (CY7C63412, CY7C63512, CY7C63612)
—8 Kbytes of EPROM (CY7C63413, CY7C63513, CY7C63613)

• Interface can auto-configure to operate as PS2 or USB

•I/O port
—The CY7634XX/5XX have 24 General Purpose I/O (GPIO) pin s (Port 0 to 2) capable of sinki ng 7 mA per pin (typical)

—The CY7C636XX have 12 General-Purpose I/O (GPIO) pins (Port 0 to 2) capable of sinking 7 mA per pin (typical)
—The CY7C634XX/5XX have eight GPIO pi ns (Port 3) capable of sinkin g 12 mA per pin (typical) which can drive LEDs
—The CY7C636XX have four GPIO pins (Port 3) capable of sinking 12 mA per pin (typical) which can drive LEDs
—Higher current drive is available by connecting multiple GPIO pins together to drive a common output
—Each GPIO port can be configured as inputs w ith internal pull-ups or open drain outputs or traditional CMO S outputs
—The CY7C635XX has an additional eight I/O pins on a DAC port which has programmable current sink outputs
—Maskable interrupts on all I/O pins

• 12-bit free-running timer with one microsecond clock ticks

• Watch Dog Timer (WDT)

• Internal Power-On Reset (POR)

• Improved output drivers to reduce EMI

• Operating voltage from 4.0V to 5.5V DC

• Operating temperature from 0 to 70 degrees Celsius

• CY7C634XX available in 40-pin PDIP, 48-pin SSOP for production

• CY7C635XX available in 48-pin SSOP packages for production

• CY7C636XX available in 24-pin SOIC packages for production

• Industry-standard programmer support

Document #: 38-08027 Rev. ** Page 5 of 36

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2.0 Functional Overview

The CY7C634XX/5XX/6XX are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been opti­mized specifical ly for USB operations alt hough, the microcon trollers can be used for a variety of non-USB emb edded applications.

The CY7C634XX/5XX feature 32 General-Purpose I/O (GPIO) pins and the CY7C636XX features 16 General-Purpose I/O
(GPIO) pins to sup port USB and o ther appli cations. Th e I/O pi ns ar e gr ouped into four po rts (Po rt 0, 1 , 2, a nd 3) where each po rt
can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs. The CYC634XX/5XX have
24 GPIO pins (Ports 0, 1, and 2) and th e CY7C636XX has 12 GPIO pins (Ports 0 and 1) that are rated at 7 mA ty pical sink current .
The CYC634XX/5XX has 8 GPIO pins (Port 3) and the CY7C636XX has 4 GPIO pins (Port 3) which are rated at 12 mA typical
sink current, which allows these pins to drive LEDs. Multiple GPIO pins can be connected together to drive a single output for
more drive current capacity. Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. Note the
GPIO interrupts all share the same “GPIO” interrupt vector.

The CY7C635XX feat ures an additional 8 I/O pins in the DAC port. Every DA C pin includes an integrated 14-Koh m pull-up resisto r.
When a “1” is writte n t o a D AC I/O p in , th e o utpu t c urre nt sink is disabled and the ou tput pi n is driven high by the internal pull-up
resistor . When a “0” is writ ten to a DAC I/O pin, the i nternal pull-up is disab led and the output pin provides the prog rammed amount
of sink current. A DAC I/O pin can be used as an input with an internal pull-up by writing a “1” to the pin.

The sink current for each DAC I/O pin can be individually programmed to one of sixteen values using dedicated Isink registers.
DAC bits [1:0] can be used as high current outputs with a programmable sink current range of 3.2 to 16 mA (typical). DAC bits
[7:2] have a programmable current sink range of 0.2 to 1.0 mA (typical). Again, multiple DAC pins can be connected together to
drive a single output that requires more sink current capacity. Each I/O pin can be used to generate a DAC interrupt to the
microcontroller and the interrupt polarity for each DAC I/O pin is individually programmable. The DAC port interrupts share a
separate “DAC” interrupt vector.

The Cypress microc ontrollers use an extern al 6-MHz ceramic resonator to provide a reference to an internal cl ock generator . Thi s
clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6- and 12-MHz clocks that
remain internal to the microcontroller.

The CY7C64XX/5XX/6XX are offered with multiple EPROM options to maximize flexibility and minimize cost. The CY7C63411
and the CY7C63511 have 4 Kilobytes of EPROM. The CY7C63412, CY7C63512, and CY7C63612 have 6 Kbytes of EPROM.
The CY7C63413, CY7C63513, and CY7C63613 have 8 Kbytes of EPROM.

These parts include Power-on Reset logic, a Watch Dog Timer, a vectored interrupt controller, and a 12-bit free-running timer.
The Power-On Reset (POR) logic detects when power is applied to the device, resets the logic to a known state, and begins
executing instruc tions at EPROM a ddress 0x0 000h. Th e W atch Dog T imer can be used t o ensure the firmw are neve r gets sta lled
for more than approximatel y 8 ms. The firmware can get stall ed for a variety of reasons , including errors in the co de or a hardware
failure such as waitin g for an interrupt that neve r occurs. The firmware sh ould clear the W atch Dog T imer periodically. If the Watch
Dog Timer is not cleared for approximately 8 ms, the microcontroller will generate a hardware watch dog reset.

The microcontroller su pports eight maskab le interrupts in the v ectored interrupt cont roller . Interrupt sour ces include the USB Bus­Reset, th e 12 8-µs and 1.024-ms outputs from the free-running timer, three USB endpoints, the DAC port, and the GPIO ports.
The timer bits cause an interrupt (if enabled) when the bit toggles from LOW “0” to HIGH “1.” The USB endpoints interrupt after
either the USB host or the USB controller sends a packet to the USB. The DAC ports have an additional level of masking that
allows the user to select which DAC inputs can cause a DAC interrupt. The GPIO ports also have a level of masking to select
which GPIO inputs can cause a GPIO interrupt. For additional flexibility, the input transition polarity that causes an interrupt is
programmable for each pin of the DAC port. Input transition polarity can be programmed for each GPIO port as part of the port
configuration. The interrupt polarity can be either rising edge (“0” to “1”) or falling edge (“1” to “0”).

The free-running 12-b it time r cloc ked at 1 MHz pro vides two inter rupt sou rce s as n oted ab ove (12 8-µs a nd 1.02 4-ms). The timer
can be used to measure th e duration of a n event unde r firmware con trol by readi ng the timer twi ce: once at the st art of the eve nt,
and once after the event is complete. The difference between the two readings indicates the duration of the event measured in
microseconds. The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits.
A read from the upper four bits actual ly reads data from the internal regist er , instead of the timer . This featur e eliminates th e need
for firmware to attempt to compensate if the upper four bits happened to increment right after the lower 8 bits are read.

The CY7C634XX/5XX/6XX in clude an integr ated USB seria l interfac e engi ne (S IE) that supp orts th e integ rated p eripher als. Th e
hardware supports one U SB device address with three endpoi nts. The SIE allows the USB host to commu nicate with the f unction
integrated into the microcontroller.

Finally, the CY7C634XX/5XX/6 XX supp ort PS/2 o perati on. Wit h appro priate firmware the D+ and D– USB pins can also be used
as PS/2 clock and data signals. Products utilizing these devices can be used for USB and/or PS/2 operation with appropriate
firmware.

Document #: 38-08027 Rev. ** Page 6 of 36

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CY7C63612/13

.

Logic Block Diagram

6-MHz ceramic resonator

OSC

12 MHz

4/6/8 Kbyte

6 MHz

12-MHz

8-bit

CPU

EPROM

RAM

256 byte

8-bit Bus

12-bit
Timer

Watch Dog

Timer

Power-on

Reset

USB

Transceiver

USB

SIE

Interrupt

Controller

GPIO

PORT 0

GPIO

PORT 1

GPIO

PORT 2

GPIO

PORT 3

DAC

PORT

D+
D–

TOP VIEW

P0[0]

P0[7]

P1[0]

P1[7]

P2[0]

P2[7]

P3[0]

P3[7]

DAC[0]

DAC[7]

USB
PS/2
PORT

See Note 1

High Current
Outputs

Pin Configuration

48-pin SSOP

1

D+

D–
P3[7]
P3[5]
P3[3]
P3[1]
P2[7]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]

DAC[7]
DAC[5]

P0[7]
P0[5]
P0[3]
P0[1]

DAC[3]
DAC[1]

V

PP

Vss

CY7C63411/12/13

40-pin PDIP

40-pin CerDIP

D+

D–
P3[7]
P3[5]
P3[3]
P3[1]
P2[7]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
P1[3]
P1[1]
P0[7]
P0[5]
P0[3]
P0[1]

V

PP

Vss

48

2

47

3

46

4

45

5

44
43

6
7

42

8

41

9

40

10

39

11

38

12

37

13

36
35

14
15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24 25

40

1

39

2

38

3

37

4

36

5

35

6

34

7

33

8

32

9

31

10

30

11

29

12

28

13

27

14

26

15

25

16

24

17

23

18
19

22

20

21

TOP VIEW

V

CC

Vss
P3[6]
P3[4]
P3[2]
P3[0]
P2[6]
P2[4]
P2[2]
P2[0]
P1[6]
P1[4]
P1[2]
P1[0]
DAC[6]
DAC[4]
P0[6]
P0[4]
P0[2]
P0[0]
DAC[2]
DAC[0]
XTAL
XTAL

V

CC

V

SS

P3[6]
P3[4]
P3[2]
P3[0]
P2[6]
P2[4]
P2[2]
P2[0]
P1[6]
P1[4]
P1[2]
P1[0]
P0[6]
P0[4]
P0[2]
P0[0]
XTAL
XTAL

OUT
IN

OUT
IN

48-pin SSOP

48-pin SideBraze48-pin SideBraze

1

D+

2

D–

3

P3[7]

4

P3[5]

5

P3[3]

6

P3[1]

7

P2[7]
P2[5]

8
9

P2[3]

10

P2[1]

11

P1[7]
P1[5]

12
13

P1[3]

14

P1[1]

15

NC

16

NC

17

P0[7]

18

P0[5]

19

P0[3]

20

P0[1]

NC

21

NC

22

V

23

PP

Vss

24 25

CY7C63612/13

24-pin SOIC

1

D+

2

D–

3

P3[7]

4

P3[5]

5

P1[3]

6

P1[1]

7

P0[7]
P0[5]

9

P0[3]

10815

P0[1]

11

V

PP

12

Vss

TOP VIEW

48

V

CC

Vss

47
46

P3[6]
P3[4]

45

P3[2]

44

P3[0]

43

P2[6]

42

P2[4]

41

P2[2]

40
39

P2[0]

38

P1[6]

37

P1[4]

36

P1[2]

35

P1[0]

34

NC

33

NC
P0[6]

32
31

P0[4]

30

P0[2]

29

P0[0]
NC

28

NC

27

XTAL

26

24
23

22
21
20
19
18
17
16

14
13

XTAL

V

CC

V

SS

P3[6]
P3[4]
P1[2]
P1[0]
P0[6]
P0[4]
P0[2]
P0[0]
XTAL
XTAL

OUT
IN

OUT
IN

Note:

1. CY7C63612/13 is not bonded out for all GPIO pins shown in Logic Block Diagram. Refer to pin configuration diagram for bonded out pins. See note on page 17
for firmware code needed for unused GPIO pins.

Document #: 38-08027 Rev. ** Page 7 of 36

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3.0 Pin Assignments

CY7C63411/12/13

Name I/O

D+, D– I/O 1,2 1,2 1,2 1,2 USB differential data; PS/2 clock and data signals
P0[7:0]

P1[3:0]

P2

P3[7:4]

DAC I/O n/a n/a 15,34,16,

XTAL

IN

XTAL

OUT

V

PP

V

CC

Vss 20,39 24,47 24,47 12,23 Ground

15,26,16,
25,17,24,

I/O

I/O

I/O

I/O

IN 21 25 25 13 6-MHz ceramic resonator or external clock input

OUT 22 26 26 14 6-MHz ceramic resonator

18,23

11,30,12,
29,13,28,

14,27

7,34,8,

33,9,32,

10,31

3,38,4,

37,5,36,

6,35

19 23 23 11 Programming voltage supply, ground during operation
40 48 48 24 Voltage supply

17,32,18,
31,19,30,

20,29

11,38,12,
37,13,36,

14,35

7,42,8,

41,9,40,

10,39

3,46,4,

45,5,44,

6,43

CY7C635

11/12/13

17,32,18,
31,19,30,

20,29

11,38,12,
37,13,36,

14,35

7,42,8,

41,9,40,

10,39

3,46,4,

45,5,44,

6,43

33,21,28,

22,27

CY7C636

12/13

Description40-Pin 48-Pin 48-Pin 24-Pin

7,18,8,

17,9,16,

10,15

5,20,6,19GPIO Port 1 capable of sink ing 7 mA (typical). P1[7:4] not

n/a GPIO Port 2 not bonded out on CY7C63612/13. See

3,22,4,21GPIO Port 3 capable of sinking 12 mA (typical). P3[3:0]

n/a DAC I/O Port with programmable current sink outputs.

GPIO port 0 capable of sinking 7 mA (typical)

bonded out on CY7C63612/13. See note on page 17
for firmware code needed for unused pins.

note on page 17 for firmware code needed for unused
pins.

not bonded out on CY7C63612/13. See note on
page 17 for firmware code needed for unused pins.

DAC[1:0] offer a programmable range of 3.2 to 16 mA
typical. DAC[7:2] have a programmable sink current
range of 0.2 to 1.0 mA ty pi ca l. D AC I/O Port not bonded
out on CY7C63612/13. See not e on page 17 for firmware
code needed for unused pins.

4.0 Programming Model

4.1 14-bit Program Counter (PC)

The 14-bit Program Counter (PC) allows access for up to 8 kilobytes of EPROM using the CY7C634XX/5XX/6XX architecture.
The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. This is
typically a jump instruction to a reset handler that initializes the application.

The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the
program counter are increm ented by exe cuting an XPAGE instr uction . As a result, the la st instruc tion execu ted within a 256 -byte
“page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to
insert XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally
need to insert a NOP followed by an XPAGE for correct execution.

The program counter of the next instructio n to be executed, ca rry flag, and zero fla g are saved as two bytes on the program sta ck
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack only during a RETI instruction.

Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading
SRAM from location 0x00 and up.

4.2 8-bit Accumulator (A)

The accumulator is the general purpose, do everything register in the architecture where results are usually calculated.

4.3 8-bit Index Register (X)

The index register “X” is available to the firmware as an auxiliary a ccumulator . The X regist er also allow s the processo r to perform
indexed operations by loading an index value into X.

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4.4 8-bit Program Stack Pointer (PSP)

During a reset, the Progra m Stac k Pointer (PSP) is s et to z ero. This mean s the program “stack” starts at RAM addre ss 0x 00 an d
“grows” upward from there. Note the program stack pointe r is directly addressable under firmware co ntrol, usin g the MOV PSP,A

instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under firmware
control.

During an interrupt acknowledge, interrupts are disabled and the 14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is
incremented. The second byte is stored in memory addressed by the program stack pointer and the PSP is incremented again.
The net effect i s t o s tore the prog ram co unt er an d fl ags on the program “stack” and increment the program stack pointer by two.

The Return From Interrupt (RETI) instruction dec rements th e program stack po inter , th en restores th e second byte from memory
addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed
by the PSP. After the program counter and flags have been restore d from stack, the interrupts are enabled. The ef fect is to restore
the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.

The Call Subroutine (CALL) in struction stores the program counter and flags on the progra m stack and increments the PSP b y two.
The Return From Subroutine (RET) instruction restores the program counter, but not the flags, from program stack and decre-

ments the PSP by two.

4.5 8-bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction will pre-decremen t the DSP, then wri te data to the memory locatio n address ed by the DSP. A POP instruction will rea d
data from the memory location addressed by the DSP, then post-increment the DSP.

During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equal zero will write data at the top of
the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB
applications, this works fine and is not a proble m. For USB ap plicat ions, it is strong ly recomm ended th at the DSP is load ed aft er
reset just below the USB DMA buffers.

4.6 Address Modes

The CY7C63612/13 microcontrollers support three addressing modes for instructions that require data operands: data, direct,
and indexed.

4.6.1 Data

The “Data” addre ss mode refers to a data ope rand that is actual ly a constant encod ed in the instructi on. As an example, cons ider
the instruction that loads A with the constant 0xE8h:

• MOV A,0E8h

This instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior
“EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown
above:

• DSPINIT: EQU 0E8h

• MOV A,DSPINIT

4.6.2 Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10h:

• MOV A, [10h]

In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the
assembler source code. As an example, the following code is equivalent to the example shown above:

• buttons: EQU 10h

• MOV A,[buttons]

4.6.3 Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the
“base” address of an array of data and the X register will contain an index that indicates which element of the array is actually
addressed:

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• array: EQU 10h

• MOV X,3

• MOV A,[x+array]

This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth
element would be at address 0x13h.

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5.0 Instruction Set Summary

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

HAL T 00 7 NOP 20 4
ADD A,expr data 01 4 INC A acc 21 4
ADD A,[expr] direct 02 6 INC X x 22 4
ADD A,[X+expr] index 03 7 INC [expr] direct 23 7
ADC A,expr data 04 4 INC [X+expr] index 24 8
ADC A,[expr] direct 05 6 DEC A acc 25 4
ADC A,[X+expr] index 06 7 DEC X x 26 4
SUB A,expr data 07 4 DEC [expr] direct 27 7
SUB A,[expr] direct 08 6 DEC [X+expr] index 28 8
SUB A,[X+expr] index 09 7 IORD expr address 29 5
SBB A,expr data 0A 4 IOWR expr address 2A 5
SBB A,[expr] direct 0B 6 POP A 2B 4
SBB A,[X+expr] index 0C 7 POP X 2C 4
OR A,expr data 0D 4 PUSH A 2D 5
OR A,[expr] direct 0E 6 PUSH X 2E 5
OR A,[X+expr] index 0F 7 SWAP A,X 2F 5
AND A,expr data 10 4 SWAP A,DSP 30 5
AND A,[expr] direct 11 6 MOV [expr],A direct 31 5
AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6
XOR A,expr data 13 4 OR [expr],A direct 33 7
XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8
XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7
CMP A,expr data 16 5 AND [X+expr],A index 36 8
CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7
CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8
MOV A,expr data 19 4 IOWX [X+expr] index 39 6
MOV A,[expr] direct 1A 5 CPL 3A 4
MOV A,[X+expr] index 1B 6 ASL 3B 4
MOV X,expr data 1C 4 ASR 3C 4
MOV X,[expr] direct 1D 5 RLC 3D 4
reserved 1E RRC 3E 4
XPAGE 1F 4 RET 3F 8
MOV A,X 40 4 DI 70 4
MOV X,A 41 4 EI 72 4
MOV PSP,A 60 4 RETI 73 8
CALL addr 50-5F 10
JMP addr 80-8F 5 JC addr C0-CF 5
CALL addr 90-9F 10 JNC addr D0-DF 5
JZ addr A0-AF 5 JACC addr E0-EF 7
JNZ addr B0-BF 5 INDEX addr F0-FF 14

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