CYPRESS CY7C63221, CY7C63231A User Manual
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enCoRe™ USB
CY7C63221/31A
CY7C63221A/31A
enCoRe™ USB
Low-speed USB Peripheral Controller
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08028 Rev. *A Revised October 21, 2002
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enCoRe™ USB
CY7C63221/31A
TABLE OF CONTENTS
1.0 FEATURES .................................................. .. .. ...................................................... .. .. .....................5
2.0 FUNCTIONAL OVERVIEW ............................................................. .................... .. ................... .......6
2.1 enCoRe USB - The New USB Standard ....................................................................................6
3.0 LOGIC BLOCK DIAGRAM .............................................................................................................7
4.0 PIN CONFIGURATIONS ................................ .. ........................... .. .. .. ........................... .. .. ...............7
5.0 PIN ASSIGNMENTS ............................. ............................... .. ............................... ..........................7
6.0 PROGRAMM I N G M OD E L ....................... .. ............... .. ................ .. .. ................ .. ............... ... .............8
6.1 Program Counter (PC) ...............................................................................................................8
6.2 8-bit Accumulator (A) .................................................................................................................8
6.3 8-bit Index Register (X) .......................................... .................... ................................................8
6.4 8-bit Program Stack Pointer (PSP) ............................................................................................8
6.5 8-bit Data Stack Pointer (DSP) ............... ................................... .................................. ..............9
6.6 Address Modes ..................................... ........................ .. ............................................. ..............9
6.6.1 Data ..................................................................................................................................................9
6.6.2 Direct ................................................................................................................................................9
6.6.3 Indexed ............................................................................................................................................9
7.0 INSTRUCTION SET SUMMARY ................................................... .. ........................... .. .. .. .............10
8.0 MEMORY ORGANIZATION ..........................................................................................................11
8.1 Program Memory Organization ............................... ..................... .................... .................... ....11
8.2 Data Memor y Organization ......... ............... ... ............... .. ................ .. ............... ... ............... .. .....12
8.3 I/O Registe r S u m ma ry ......... ................ .. ............... ... ............... .. ................ .. ............... ... ...........13
9.0 CLOCKING ....................................................................................................................................14
9.1 Internal/External Oscillator Operation ......................................................................................15
9.2 External Oscillator ....................................................................................................................15
10.0 RESET ............................................................ ......................... ............................ ........................16
10.1 Low-volt a g e Re s e t (L V R ) ... .. ................ .. ................ .. .. ............... ... ............... .. ................ .. .......16
10.2 Brown-ou t R e se t (BOR) .............................. .. ............... .. ................ .. .. ................ .. ..................16
10.3 Watchdog Reset (WDR) ....................... .................................................................................17
11.0 SUSPEND MODE ........................................................................................................................17
11.1 Clocking Mode on Wake-up from Suspend ........................... ................................................18
11.2 Wake-up Tim e r ......... ................ .. .. ................ .. ............................... .. ................ .. .. ..................18
12.0 GENERAL PURPOSE I/O PORTS .............................................................................................19
12.1 Auxiliary Input Port .................................................................................................................21
13.0 USB SERIAL INTERFACE ENGINE (SIE) .................................................................................22
13.1 USB Enumeration ..................................................................................................................23
13.2 USB Port Status and Control .................................................................................................23
14.0 USB DEVICE ...............................................................................................................................25
14.1 USB Address Register ...........................................................................................................25
14.2 USB Control Endpoint ............................................................................................................25
14.3 USB Non-Control Endpoints ..................................................................................................26
14.4 USB Endpoint Counter Registers ........................................................ ...................... ............27
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15.0 USB REGULATOR OUTPUT ......................................................................................................27
16.0 PS/2 OPERATION .......................................................................................................................28
17.0 12-BIT FREE-RUNNING TIMER ......................... .. .......................... ......................... ...................28
18.0 PROCESSOR STATUS AND CONTROL REGISTER ........................................ .. .. ...................29
19.0 INTERRUPTS .................................... .. ......................... .. .. .. .. .......................................................31
19.1 Interrupt Vectors ....................................................................................................................31
19.2 Interrupt Latency ....................................................................................................................32
19.3 Interrupt Sources ...................................................................................................................32
20.0 USB MODE TABLES ..................................................................................................................36
21.0 REGISTER SUMMARY .................................................. .. .. .. .......................................................41
22.0 ABSOLUTE MAXIMUM RATINGS .............................................................................................42
23.0 DC CHARACTERISTICS ............................................................................................................42
24.0 SWITCHING CHARACTERISTICS ............................................. .. .. ............................. .. .............44
25.0 ORDERING INFORMATION .......................................................................................................47
26.0 PACKAGE DIAGRAMS .............................................................................................................47
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LIST OF FIGURES
Figure 8-1. Pro g ra m M e mory Space with In te rrupt Vector Table ........................... .. ................ .. .........11
Figure 9-1. Clo ck Os cillator On-chip C ir cu it ..... .. .. ................ .. ............... .. ................ .. .. ................ .........14
Figure 9-2. Clo ck C o n fig u r a tion Register (A dd r e ss 0 xF 8 ) .............. .. ............... ................ .. ............... ... 14
Figure 10-1. Watchdog Reset (WDR, Address 0x26) ..........................................................................17
Figure 12-1. Block Diagram of GPIO Port (one pin shown) .................................................................19
Figure 12-2. Port 0 Data (Address 0x 0 0 ) ........... .. ................ .. ............... .. ................ .. ................ .. .........19
Figure 12-3. Port 1 Data (Address 0x 0 1 ) ........... .. ................ .. ............... .. ................ .. ................ .. .........20
Figure 12-4. GPIO Port 0 Mode0 Re gister (Addres s 0 x 0A) ... ............... .. ................ .. ................ ...........20
Figure 12-5. GPIO Port 0 Mode1 Re gister (Addres s 0 x 0B) ... ............... .. ................ .. ................ ...........20
Figure 12-6. GPIO Port 1 Mode0 Re gister (Addres s 0 x 0C) .. .. ............... ... ............... .. ................ .. .......20
Figure 12-7. GPIO Port 1 Mode1 Re gister (Addres s 0 x 0D) .. .. ............... ... ............... .. ................ .. .......21
Figure 12-8. Port 2 Data Register (A d dr e s s 0 x 02 ) .................. .. ................ .. .. ................ .. ............... .. .. .22
Figure 13-1. USB Status and Control Register (Address 0x1F) ..........................................................23
Figure 14-1. USB Device Address Register (Address 0x10) ...............................................................25
Figure 14-2. Endpoint 0 Mode Register (Address 0x12) ................................................................. ....25
Figure 14-3. USB Endpoint EP1 Mode Registers (Address 0x14) ......................................................26
Figure 14-4. Endpoint 0 and 1 Counter Registers (Addresses 0x11 and 0x13) ..................... .............27
Figure 16-1. Diagram of USB - PS/2 System Connections ........................ .. ...................................... .28
Figure 17-1. Timer LSB Register (Address 0x24) ................................................................................29
Figure 17-2. Ti m e r MS B R eg i s te r (A d d ress 0x25) .......... .. ................ .. ................ .. .. ............... ... ...........29
Figure 17-3. Ti m e r Bl o c k D ia g r a m ............................ .. .. ............... ... ............... .. ................ .. .. ................29
Figure 18-1. Processor Status and Control Register (Address 0xFF) .................................................29
Figure 19-1. Global Interrupt Enable Register (Address 0x20) ............................................................32
Figure 19-2. Endpoint Interrupt Enable Register (Address 0x21) ........................ ................................33
Figure 19-3. Interrupt Controller Logic Block Diagram ........................................................................34
Figure 19-4. Port 0 Interrupt Enable Register (Address 0x04) ............................................................34
Figure 19-5. Port 1 Interrupt Enable Register (Address 0x05) ............................................................34
Figure 19-6. Port 0 Interrupt Polarity Register (Address 0x06) ............................................................35
Figure 19-7. Port 1 Interrupt Polarity Register (Address 0x07) ............................................................35
Figure 19-8. GP IO In terrupt Diagra m ..... .. ................ .. ............... .. ................ .. ................ .. ....................35
Figure 24-1. Cl o ck T imi n g ....... ................ .. ................ .. ............... .. ... ............... .. ................ .. ..................45
Figure 24-2. USB Data Signal Timing ..................................................................................................45
Figure 24-3. Rec e iv e r Jitter Toleranc e ... .. ................ .. ............... .. ... ............... .. ................ .. ..................45
Figure 24-4. Di ff erential to EOP Tra n s ition Skew and EOP Wid th .............. .. ................ .. ............... .. ... 46
Figure 24-5. Differential Data Jitter ......................................................................................................46
LIST OF TABLES
Table 8-1. I/O Register Summary .................................... .. ...................... ..................... .......................13
Table 11-1. Wake-up Timer Adjust Settings ........................................................................................18
Table 12-1. Ports 0 and 1 Output Control Truth Table .......................... ...................... ...................... ..21
Table 13-1. Control Modes to Force D+/D– Outputs ...........................................................................24
Table 19-1. Interrupt Vector Assignments ...........................................................................................31
Table 20-1. USB Register Mode Encoding for Control and Non-Control Endpoint ................... ..........36
Table 20-2. Decode table for Table 20-3: “Details of Modes for Differing Traffic Conditions” ............. 38
Table 20-3. Details of Modes for Differing Traffic Co nditions ...................................................... ........39
Table 26-1. CY7C63221A-XC Probe Pad Coordinates in microns ((0,0) to bond pad centers) ..........48
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1.0 Features
• enCoRe™ USB - enhanced Component Reduction
—Internal oscillator eliminates the need for an external crystal or resonator
—Interface can auto -configure to operate as PS/2 o r USB without the need for externa l components to switc h between
modes (no GPIO pins needed to manage dual mode capability)
—Internal 3.3V regulator for USB pull-up resistor
—Configurable GPIO for real-world interface without external components
• Flexible, cost-effective solution for applications that combine PS/2 and low-speed USB, such as mice, gamepads,
joysticks, and many others
• USB Specification Compliance
—Conforms to USB Specification, Version 2.0
—Conforms to USB HID Specification, Version 1.1
—Supports 1 low-speed USB device address
—Supports 1 control endpoint and 1 data endpoint
—Integrated USB transceiver
—3.3V regulated output for USB pull-up resistor
• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator or internal clock mode
—12-MHz internal CPU clock
—Internal memory
—96 bytes of RAM
—3 Kbytes of EPROM
—Interface can auto-configure to operate as PS/2 or USB
—No external components for switching between PS/2 and USB modes
• I/O ports
—Up to 10 versatile General Purpose I/O (GPIO) pins, individually configurable
—High current drive on any GPIO pin: 50 mA/pin current sink
—Each GPIO pin support s high-impedance input s, internal pull-ups, ope n drain outputs, or traditional CMOS outputs
—Maskable interrupts on all I/O pins
—XTALIN, XTALOUT and VREG can be configured as additional input pins
• Internal low-power wake-up timer during suspend mode
—Periodic wake-up with no external components
• Optional 6-MHz internal oscillator mode
—Allows fast start-up from suspend mode
• Watchdog timer (WDT)
• Low-voltage Reset at 3.75V
• Internal brown-out reset for suspend mode
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5VDC
• Operating temperature from 0 to 70 degrees Celsius
• CY7C63221A available in DIE form or 16-pin PDIP
• CY7C63231 available in 18-pin SOIC, 18-pin PDIP
• Industry-standard programmer support
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2.0 Functional Overview
2.1 enCoRe USB - The New USB Standard
Cypress has reinvented its leadership position in the low-speed USB market with a new family of innovative microcontrollers.
Introducing...enCoRe™ USB—“enhanced C ompon ent Reduc tio n.” Cypr ess h as l ev erag ed its design e xp erti se in USB so lutions
to create a new family of low-speed USB microcontrollers that enables peripheral developers to design new products with a
minimum number of components. At the heart of the Cypress enCoRe USB technology is the breakthrough design of a crystalless oscillator. By integrating the oscillator into the chip, an external crystal or resonator is no longer needed. We have also
integrated other ex ternal components commonly found i n low-speed USB appli cations such as pull-up resistors, wa ke-up circuitry ,
and a 3.3V regulator. All of this adds up to a lower system cost.
The CY7C632XX family is comprised of 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has
been optimized specifically for USB and PS/2 operations, although the microcontrollers can be used for a variety of other
embedded applications.
The CY7C632XX features up to 10 general-purpose I/O (GPIO) pins to support USB, PS/2 and other applications. The I/O pins
are grouped into two po rts (Po rt 0 to 1) wh ere each pin can be ind ividu ally c onfigu red as input s with interna l pull-u ps, open drain
outputs, or tr aditional CMOS ou tput s with p rogrammab le drive strength of up to 50 m A output drive. Add itionall y, each I/O pin can
be used to generate a GPIO interrupt to the microcontroller.
The CY7C632XX microcontrollers feature an internal oscillator. With the presence of USB traffic, the internal oscillator can be
set to precisely tune to U SB timing requirement s (6 MHz ± 1.5%). This clock gene rator has been optimize d to reduce clock-relate d
noise emissions (EMI), and provides the 6-MHz and 12-MHz clocks that remain internal to the microcontroller. When using the
internal oscillator, XTALIN and XTALOUT can be configured as additional input pins that can be read on port 2. Optionally, an
external 6-MHz ceramic resonator can be used to provide a higher precision reference if needed.
The CY7C632XX is offered with 3 Kbytes of EPROM to minimize cost, and has 96 bytes of data RAM for stack space, user
variables, and USB endpoint FIFOs.
The CY7C632XX family includes low-voltage reset logic, a watchdog timer, a vectored interrupt controller, and a 12-bit freerunning timer. The low-voltage reset (LVR) logic detects when power is applied to the device, resets the logic to a known state,
and begins executing instructions at EPROM address 0x0000. LVR will also reset the part when V
voltage range. The watchdog timer can be used to ensure the firmware never gets stalled for more than approximately 8 ms.
The microcontroller supports 7 maskable interrupts in the vectored interrupt controller. Interrupt sources include the USB BusReset, the 128-µs and 1.024-m s output s from the fre e-running timer, two USB endpoints, an in ternal wake-up timer and th e GPIO
port. The timers bits cause periodic interrupts when enabled. The USB endpoints interrupt after USB transactions complete on
the bus. The GPIO p ort h as a le ve l of mas k ing to s el ect w hic h G PIO in puts can cause a GPIO int errup t. For additional flexibi li ty,
the input transitio n polarity tha t causes an interrup t is progra mmable f or each GP IO pin. Th e interrupt p olarity can b e either rising
or falling edge.
The free-running 1 2-bi t t im er c lo cked at 1 MHz provides tw o inte rrup t s ou rces a s no ted above (128 µs and 1 .024 m s). Th e timer
can be used to measure the duration of an event under firmware control by reading the timer at the start and end of an event,
and subtracting the two values.
The CY7C63221/31A inclu des an integ rated USB serial interface eng ine (SIE). The hard ware support s one USB devi ce addres s
with two endpoints. The SIE allows the USB host to communicate with the function integrated into the microcontroller. A 3.3V
regulated output pin provides a pull-up source for the external USB resistor on the D– pin. When using an external voltage
regulator VREG can be configured as an input pin that can be read on port 2 (P2.0).
The USB D+ and D– USB pins can alternately be used as PS/2 SCLK and SDATA signals, so that products can be designed to
respond to either USB or PS/2 modes of operation. PS/2 operation is supported with internal pull-up resistors on SCLK and
SDA TA, the ability to disable the regulator output pin, and an in terrupt to signa l the start of PS/2 ac tivity. No external components
are necessary for dual USB and PS/2 systems, and no GPIO pins need to be dedicated to switching be tween modes . Slow edge
rates operate in both modes to reduce EMI.
drops below the operating
CC
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3.0 Logic Block Diagram
XTALIN/P2.1 XTALOUT/P2.2
XT ALIN/P2 .1 XT ALOUT
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Internal
Oscillator
EPROM
3 Kbytes
Brown-Out
Reset
Watch Dog
Timer
Low Voltage
Reset
4.0 Pin Configurations
CY7C63221A
16-pin PDIP
P0.0
P0.1
P0.2
P0.3
V
SS
V
PP
VREG/P2.0
XTALIN/P2.1
1
2
3
4
5
6
7
8
P0.4
16
15
P0.5
P0.6
14
P0.7
13
12
D+/SCLK
11
D–/SDATA
10
V
XTALOUT/P2.2
9
CC
Xtal
Os cillator
8-bit
RISC
Core
Wake-Up
Timer
Interru p t
Controller
3.3V
Regulator
RAM
96 Bytes
USB
Engine
USB &
PS/2
Xcvr
12-bit
Timer
Port 0
GPIO
VREG/P2.0 D+ D- P0.0-P0.7 P1.0-P1.1
(Top View)
CY7C63231A
18-pin SOIC/PDIP
P0.0
1
P0.1
2
P0.2
3
P0.3
4
P1.0
5
6
V
SS
7
V
PP
VREG/P2.0
XTALIN/P2.1
8
9
P0.4
18
17
P0.5
P0.6
16
P0.7
15
P1.1
14
13
D+/SCLK
12
D–/SDATA
11
V
XTALOUT/P2.2
10
CC
CY7C63221A-XC
DIE
P0.3
P1.0
Vss
Port 1
GPIO
4
5
6
3 P0.2
2 P0.1
7 8 9
Vpp
VREG/P2.0
1 P0.0
18 P0.4
101112
XTALIN/P2.1
XTALOUT/P2.2
17 P0.5
Vcc
16 P0.6
15
14
13
D-/SDATA
P0.7
P1.1
D+/SCLK
5.0 Pin Assignments
CY7C63221A
Name I/O
D–/SDAT A,
D+/SCLK
I/O 11
12
P0[7:0] I/O 1, 2, 3, 4,
13, 14, 15, 16
P1[1:0] I/O NA 5,14 IO Port 1 capabl e of sinking up to 50 mA/pin, o r sinking control led
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CY7C63231/
CY7C63221-XC
12
13
1, 2, 3, 4,
15, 16, 17, 18
Description16-Pin 18-Pin/Pad
USB differential data lines (D– and D+), or PS/2 clock and data
signals (SDATA and SCLK)
GPIO Port 0 capable of sinking up to 50 mA/pin, or sinking
controlled low or high programmable current. Can also source
2 mA current, provide a resistive pull-up, or serve as a highimpedance input.
low or high program mable current. Can also source 2 m A current,
provide a resistive pull-up, or serve as a high-impedance input.
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5.0 Pin Assignments (continued)
CY7C63221A
Name I/O
XTALIN/P2.1 IN 8 9 6-MHz ceramic resonator or external clock input, or P2.1 input
XTALOUT/P2.2 IN 9 10 6-MHz ceramic resonator return pin or internal oscillator output,
V
PP
V
CC
VREG/P2.0 7 8 Voltage supply for 1.3-kΩ USB pull-up resistor (3.3V nominal).
V
SS
6 7 Programming voltage supply, ground for normal operation
10 1 1 Volt age supply
5 6 Ground
6.0 Programming Model
Refer to the CYASM Assembler User’s Guide for more details on firmware operation with the CY7C632XX microcontrollers.
6.1 Program Counter (PC)
The 14-bit program coun ter (PC) allows access f or 3 Kbytes of EPROM usi ng the CY7C632XX arc hitecture. The prog ram counter
is cleared during rese t, such that the first instruct ion executed after a reset is at address 0x0000. This is typically a jump instruction
to a reset handler that initializes the application.
The lower 8 bits of the program counter are incre mented as instructi ons are loaded and exec uted. The upper 6 bit s of the program
counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page”
of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” will cause the assembler to insert
XPAGE instructions automatically. As instructions can be either one or two bytes long, the assembler may occasionally need to
insert a NOP followed by an XPAGE for correct execution.
The program counter of the next in struction to be ex ecuted, carry flag, and zero flag are saved as two by tes on the program st ack
during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the
program stack only during a RETI instruction.
Please note the program counter cannot be accessed directly by the firmware. The program stack can be examined by reading
SRAM from location 0x00 and up.
Note that there are rest rictions in using t he JMP , CALL, and INDEX instructi ons across the 4-KB boun dary of the program memo ry .
Refer to the CYASM Assembler User’s Guide for a detailed description.
CY7C63231/
CY7C63221-XC
Description16-Pin 18-Pin/Pad
or P2.2 input
Also serves as P2.0 input.
6.2 8-bit Accumulator (A)
The accumulator is the general-purpose, do-everything register in the architecture where results are usually calculated.
6.3 8-bit Index Register (X)
The index register “X” is available to the firmware a s an auxiliary accumulator. The X register also allow s the processo r to perform
indexed operations by loading an index value into X.
6.4 8-bit Program Stack Pointer (PSP)
During a reset, the program sta ck poin ter (PSP) i s set to ze ro. Th is means the pro gra m “stack” starts at R AM addre ss 0x 00 an d
“grows” upward from there. Note that the program stack pointer is directly addressable under firmware control, using the MOV
PSP,A instruction. The PSP supports interrupt service under hardware control and CALL, RET, and RETI instructions under
firmware control.
During an interrupt acknowledge, interrupts are disabled and the program counter, carry flag, and zero flag are written as two
bytes of data memory. The first byte is stored in the memory addressed by the program stack pointer, then the PSP is incremented.
The second byte is store d i n m em ory add res sed by th e pro gra m s t ac k poi nter and the PSP is incremented ag ain . Th e ne t effect
is to store the program counter and flags on the program “stack” and increment the program stack pointer by two.
The return from interrupt (RETI) instruction decrements the program stack pointer, then restores the second byte from memory
addressed by the PSP. The program stack pointer is decremented again and the first byte is restored from memory addressed
by the PSP. After the program counter and flags have be en restored from stack, the interrupts are enab led. The effect is to restore
the program counter and flags from the program stack, decrement the program stack pointer by two, and re-enable interrupts.
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The call subrou tine (CALL) instru ction stores the program co unter and flags o n the program s tack and increments th e PSP by two.
The return from subroutin e (RET) instructio n restores the p rogram cou nter , but not the flags, from pro gram stack a nd decrement s
the PSP by two.
6.5 8-bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH
instruction will pre-decrem ent the DSP, then wr ite dat a to the memory location addresse d by the D SP. A POP instruction will rea d
data from the memory location addressed by the DSP, then post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A PUSH instruction when DSP equals zero will write data at the top of
the data RAM (address 0xFF). This would write data to the memory area reserved for a FIFO for USB endpoint 0. In non-USB
applications, this works fine and is not a problem.
For USB applications , the firmw are shou ld set the DSP to a n appropriate location to avoid a memo ry confli ct with RAM dedic ated
to USB FIFOs. Since there are only 80 bytes of RAM available (except Endpoint FIFOs) the DSP should be set between 0x00
and 0x4Fh. The memory requirements for the USB endpoints are shown in Section 8.2. For example, assembly instructions to
set the DSP to 20h (giving 32 bytes for pr ogram and da ta stack combined) are shown bel ow:
MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less to avoid USB FIFOs)
SWAP A,DSP ; swap accumulator value into DSP register
6.6 Address Modes
The CY7C632XX microcontroller supports three addressing modes for instructions that require data operands: data, direct, and
indexed.
6.6.1 Data
The “Data” address mode refers to a da ta ope rand that is actua lly a cons tant encoded in the i nstruction . As an example , consid er
the instruction that loads A with the constant 0x30:
• MOV A, 30h
This instruction will require two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the constant “0xE8h”. A constant may be referred to by name if a prior
“EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown
above:
• DSPINIT: EQU 30h
• MOV A,DSPINIT
6.6.2 Direct
“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10h:
• MOV A, [10h]
In normal usage, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the
assembler source code. As an example, the following code is equivalent to the example shown above:
• buttons: EQU 10h
• MOV A,[buttons]
6.6.3 Indexed
“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. In normal usage, the constant will be the
“base” address of an array of data and the X register will contain an index that indicates which element of the array is actually
addressed:
• array: EQU 10h
• MOV X,3
• MOV A,[x+array]
This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10h. The fourth
element would be at address 0x13h.
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7.0 Instruction Set Summary
Refer to the CY ASM Assembler User’s Guide for detaile d information on thes e instructions. Note that conditional jump instructions
(i.e. JC, JNC, JZ, JNZ) take 5 cycles if jump is taken, 4 cycles if no jump.
MNEMONIC Operand Opcode Cycles
HALT 00 7
ADD A,expr data 01 4
ADD A,[expr] direct 02 6
ADD A,[X+expr] index 03 7
ADC A,expr data 04 4
ADC A,[expr] direct 05 6
ADC A,[X+expr] index 06 7
SUB A,expr data 07 4
SUB A,[expr] direct 08 6
SUB A,[X+expr] index 09 7
SBB A,expr data 0A 4
SBB A,[expr] direct 0B 6
SBB A,[X+expr] index 0C 7
OR A,expr data 0D 4
OR A,[expr] direct 0E 6
OR A,[X+expr] index 0F 7
AND A,expr data 10 4
AND A,[expr] direct 11 6
AND A,[X+expr] index 12 7
XOR A,expr data 13 4
XOR A,[expr] direct 14 6
XOR A,[X+expr] index 15 7
CMP A,expr data 16 5
CMP A,[expr] direct 17 7
CMP A,[X+expr] index 18 8
MOV A,expr data 19 4
MOV A,[expr] direct 1A 5
MOV A,[X+expr] index 1B 6
MOV X,expr data 1C 4
MOV X,[expr] direct 1D 5
reserved 1E
XPAGE 1F 4
MOV A,X 40 4
MOV X,A 41 4
MOV PSP,A 60 4
CALL addr 50 - 5F 10
JMP addr 80-8F 5
CALL addr 90-9F 10
JZ addr A0-AF 5 (or 4)
JNZ addr B0-BF 5 (or 4)
MNEMONIC Operand Opcode Cycles
NOP 20 4
INC A acc 21 4
INC X x 22 4
INC [expr] direct 23 7
INC [X+expr] index 24 8
DEC A acc 25 4
DEC X x 26 4
DEC [expr] direct 27 7
DEC [X+ex p r ] ind ex 28 8
IORD expr address 29 5
IOWR expr address 2A 5
POP A 2B 4
POP X 2C 4
PUSH A 2D 5
PUSH X 2E 5
SWAP A,X 2F 5
SWAP A,DSP 30 5
MOV [expr],A direct 31 5
MOV [X+expr],A index 32 6
OR [expr],A direct 33 7
OR [X+exp r],A index 34 8
AND [expr],A direct 35 7
AND [X+expr],A index 36 8
XOR [expr],A direct 37 7
XOR [X+expr],A index 38 8
IOWX [X+expr] index 39 6
CPL 3A 4
ASL 3B 4
ASR 3C 4
RLC 3D 4
RRC 3E 4
RET 3F 8
DI 70 4
EI 72 4
RETI 73 8
JC addr C0-CF 5 (or 4)
JNC addr D0-DF 5 (or 4)
JACC addr E0-EF 7
INDEX addr F0-FF 14
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8.0 Memory Organization
8.1 Program Memory Organization
After reset Address
14-bit PC 0x0000 Program execution begins here after a reset.
enCoRe™ USB
CY7C63221/31A
0x0002 USB Bus Reset interrupt vector
0x0004 128-µs timer interrupt vector
0x0006 1.024-ms timer interrupt vector
0x0008 USB endpoint 0 interrupt vector
0x000A USB endpoi nt 1 interrupt vector
0x000C Reserved
0x000E Reserved
0x0010 Reserved
0x0012 Reserved
0x0014 GPIO interrupt vector
0x0016 Wake-up interrupt vector
0x0018 Program Memory begins here
0x0BDF 3 KB PROM ends here (3K - 32 bytes). See Note 1 belo w
Figure 8-1. Program Memory Space with Interrupt Vector Table
Note:
1. The upper 32 bytes of the 3K PROM are reserved. Therefore, user’s program must not over-write this space.
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enCoRe™ USB
CY7C63221/31A
8.2 Data Memory Organization
The CY7C632XX microcontroller provides 96 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas:
program stack, data stack, user variables and USB endpoint FIFOs as shown below:
After reset Address
8-bit DSP 8-bit PSP 0x00 Progr am S tack Growth
(User’s firmware
moves DSP)
8-bit DSP User selected Data St ack Growth
User Variables
0x4F
0xF0
0xF8
Top of RAM Memory 0xFF
USB FIFO for Address A endpoint 1
USB FIFO for Address A endpoint 0
Document #: 38-08028 Rev. *A Page 12 of 49
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enCoRe™ USB
CY7C63221/31A
8.3 I/O Register Summary
I/O registers are accessed via the I/O Read (IO RD) and I/O W ri te (IOWR, IOW X) instru ction s. IORD reads the selecte d port into
the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X
to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that
specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.
Note: All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (Figure 18-
1). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always be
written as 0 and be treated as undefined by reads.
Table 8-1. I/O Register Summary
Register Name I/O Address Read/Write Function Fig.
Port 0 Data 0x00 R/W GPIO Port 0 12-2
Port 1 Data 0x01 R/W GPIO Port 1 12-3
Port 2 Data 0x02 R Auxiliary input register for D+, D–, VREG, XTALIN,
XTALOUT
Port 0 Interrupt Enable 0x04 W Interrupt enable for pins in Port 0 19-4
Port 1 Interrupt Enable 0x05 W Interrupt enable for pins in Port 1 19-5
Port 0 Interrupt Polarity 0x06 W Interrupt polarity for pins in Port 0 19-6
Port 1 Interrupt Polarity 0x07 W Interrupt polarity for pins in Port 1 19-7
Port 0 Mode0 0x0A W Controls output configuration for Port 0 12-4
Port 0 Mode1 0x0B W 12-5
Port 1 Mode0 0x0C W Controls output configuration for Port 1 12-6
Port 1 Mode1 0x0D W 12-7
USB Device Address 0x10 R/W USB Device Address register 14-1
EP0 Counter Register 0x11 R/W USB Endpoint 0 counter register 14-4
EP0 Mode Register 0x12 R/W USB Endpoint 0 configuration register 14-2
EP1 Counter Register 0x13 R/W USB Endpoint 1 counter register 14-4
EP1 Mode Register 0x14 R/W USB Endpoint 1 configuration register 14-3
USB Status & Control 0x1F R/W USB status and control register 13-1
Global Interrupt Enable 0x20 R/W Global interrupt enable register 19-1
Endpoint Interrupt Enable 0x21 R/W USB endpoint interrupt enables 19-2
Timer (LSB) 0x24 R Lower 8 bits of free-running timer (1 MHz) 17-1
Timer (MSB) 0x25 R Upper 4 bits of free-running timer 17-2
WDR Clear 0x26 W Watch Dog Reset clear -
Clock Configuration 0xF8 R/W Internal / External Clock configuration register 9-2
Processor Status & Control 0xFF R/W Processor status and control 18-1
12-8
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enCoRe™ USB
CY7C63221/31A
9.0 Clocking
The chip can be clocked from either the internal on-chip clock, or from an oscillator based on an external resonator/crystal, as
shown in Figure 9-1. No additional capacit ance is in clude d on c hip at the XTALIN/OUT pins. Operation is control led by the Cl ock
Configurat ion Register, Figure 9-2.
Internal Osc
Int Clk Output Disable
Port 2.2
XTALOUT
Ext Osc Enable
Clk2x (12 MHz)
(to Microcontroller)
Clock
Doubler
XTALIN
Clk1x (6 MHz)
(to USB SIE)
Port 2.1
Figure 9-1. Clock Oscillator On-chip Circuit
Bit # 76543210
Bit Name Ext. Clock
Resume
Delay
Wake-up Timer Adjust Bit [2:0] Low-voltage
Reset
Disable
Precision
USB
Clocking
Enable
Internal
Clock
Output
Disable
External
Oscillator
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 9-2. Clock Configuration Register (Address 0xF8)
Bit 7: Ext. Clock Resume Delay
External Clock Resume Delay bit selects the delay time when switching to the external oscillator from the internal oscillator
mode, or when waking from suspend mode with the external oscillator enabled.
1 = 4 ms delay.
0 = 128 µs delay.
The delay gives the oscillator time to start up. The shorter time is adequate for operation with ceramic resonators, while the
longer time is pre ferred for st art-up with a crystal . (These time s do not incl ude an initial oscillator start-up ti me which d epends
on the resonating element. This time is typically 50–100 µs for ceramic resonators and 1–10 ms for crystals). Note that this
bit only selects the del ay time for the extern al cloc k mode. When wak ing from suspend mo de with the interna l oscillat or (Bit 0
is LOW), the delay time is only 8 µs in addition to a delay of approximately 1 µs for the oscillator to start.
Bit [6:4]: Wake-up Timer Adjust Bit [2:0]
The Wake-up Timer Adjust Bits are used to adjust the Wake-up timer period.
If the Wak e-up interrupt is e nabled in the Global Inte rrupt Enable Regi ster , the mic rocontroller wi ll generate w ake-up interr upts
periodically. The frequency of these periodical wake-up interrupts is adjusted by setting the Wake-up Timer Adjust Bit [2:0],
as described in Section 11.2. One common use of the wake-up interrupts is to generate periodical wake-up events during
suspend mode to check for changes, such as looking for movement in a mouse, while maintaining a low average power.
Bit 3: Low-voltage Reset Disable
When V
microcontroller enters a partial suspend state for a period of t
drops below V
CC
(see Section 23.0 for the value of V
LVR
) and the Low-voltage Reset circuit is enabled, the
LVR
(see Sec tion 24.0 for th e value of t
START
START
). Program
Document #: 38-08028 Rev. *A Page 14 of 49
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enCoRe™ USB
CY7C63221/31A
execution begins from address 0x0000 after this t
executes code. See Section 10.1 for more details.
delay period. This provides time for VCC to stabilize before the part
START
1 = Disables the LVR circuit.
0 = Enables t he LVR circuit.
Bit 2: Precision USB Clocking Enable
The Precision USB Clocking Enable only affects operation in internal oscillator mode. In that mode, this bit must be set to
1 to cause the internal cloc k to automatically p recisely tune to U SB timing requireme nts (6 MH z ± 1.5%). The freque ncy
may have a looser initial tolerance at power-up, but all USB transmissions from the chip will meet the USB specification.
1 = Enabled. The internal clock accuracy is 6 MHz ±1.5% after USB traffic is received.
0 = Disabled. The internal clock accuracy is 6 MHz ±5%.
Bit 1: Internal Clock Output Disable
The Internal Clock Out put Disable is used to keep the internal c lock from drivi ng out to the XTALOUT pin. This bit has no ef fect
in the external oscillator mode.
1 = Disable internal clock output. XTALOUT pin will drive HIGH.
0 = Enable the internal clock output. The internal clock is driven out to the XTALOUT pin.
Bit 0: External Oscillator Enable
At power-up, the chip operat es from th e interna l cloc k by def ault. Setti ng the Ext ernal Osc illato r Enab le bit HIG H disabl es the
internal clock, and halts the part while the external resonator/crystal oscillator is started. Clearing this bit has no immediate
effect, although the state of this bit is used when waking out of suspend mode to select between internal and external clock.
In internal clock mode, XTALIN pin will be configured as an input with a weak pull-down and can be used as a GPIO input
(P2.1).
1 = Enable the external oscillator. The clock is switched to external clock mode, as described in Section 9.1.
0 = Enable the internal oscillator.
9.1 Internal/External Oscillator Operati on
The internal oscillator provides an operating clock, factory set to a nominal frequency of 6 MHz. This clock requires no external
components. At p ow er-u p, the ch ip operates from the in ternal clock. In this m ode , th e i nte rnal c loc k is bu ffered and driven t o the
XTALOUT pin by default, and the state of the XTALIN pin can be read at Port 2.1. While the internal clock is enabled, its output
can be disabled at the XTALOUT pin by setting the Internal Clock Output Disable bit of the Clock Configuration Register.
Setting the External Oscillat or Enable bi t of the Clock Confi guratio n Registe r HIGH disab les the inter nal clo ck, and ha lts the part
while the external re sonat or/crys tal osci llator i s st arted . The step s in volv ed in sw itchin g from I nternal to Exter nal Cloc k mo de a re
as follows:
1. At reset, chip begins operation using the internal clock.
2. Firmware sets Bit 0 of the Clock Configuration Register. For example,
mov A, 1h ; Set Bit 0 HIGH (External Oscillator Enable bit). Bit 7 cleared gives faster start-up
iowr F8h ; Write to Clock Configuration Register
3. Internal clocking is halted, the internal oscillator is disabled, and the external clock oscillator is enabled.
4. After the external clock becomes stable , chip cloc ks are re-ena bled using the external clo ck signa l. (Note that the tim e for the
external clock to become stable depends on the external resonating device; see next section.)
5. After an additional delay the CPU is released to run. This delay depends on the state of the Ext. Clock Resume Delay bit of
the Clock Configuration Register. The time is 128 µs if the bit is 0, or 4 ms if the bit is 1.
6. Once the chip has been set to ex ternal oscillator , i t can only return to internal clock w hen waking from suspend mode . Clearing
bit 0 of the Clock Configuration Register will not re-enable internal clock mode until suspend mode is entered. See Section
11.0 for more details on suspend mode operation.
If the Internal Clock is enabled, the XTALIN pin can serve as a general-purpose input, and its state can be read at Port 2, Bit 1
(P2.1). Refer to Figure 12-8 for the Port 2 Data Register. In this mode, there is a weak pull-down at the XTALIN pin. This input
cannot provide an interrupt source to the CPU.
9.2 External Oscillator
The user can connect a low-cost ceramic resonator or an external oscillator to the XTALIN/XTALOUT pins to provide a precise
reference frequency for the chip clock, as shown in Figure 9-1. The e xterna l compone nts requir ed are a c eramic reso nator or
crystal and any associated capacitors. To run from the external resonator, the External Oscillator Enable bit of the Clock Configuration Register must be set to 1, as explained in the previous section.
Document #: 38-08028 Rev. *A Page 15 of 49
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