5.1.1 Program Memory Organization ............................................................................................................7
5.1.2 Security Fuse Bit ...................................................................................................................................7
5.1.3 Data Memory Organization ...................................................................................................................8
5.3.2 Watch Dog Reset (WDR) .....................................................................................................................10
5.3.3 USB Bus Reset ....................................................................................................................................10
5.8.3 USB Interrupt .......................................................................................................................................16
5.11 External USB Pull-Up Resistor ............................................ .............................................. .. ......21
5.12 Instruc ti o n S e t S u mmary ....................... .. ............... ................ .. ................ ............... ..................22
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................23
—2 Kbytes of EPROM (CY7C63000A, CY7C63100A)
—4 Kbytes of EPROM (CY7C63001A, CY7C63101A)
•I/O ports
—Integrated USB transceiver
—Up to 16 Schmitt trigger I/O pins with internal pull-up
—Up to 8 I/O pins with LED drive capability
—Special purpose I/O mode supports optimization of photo transistor and LED in mouse application
—Maskable Interrupts on all I/O pins
• 8-bit free-running timer
• Watch dog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up Modes
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0 to 70 degree Celsius
• Available in space saving and low cost 20-pin PDIP, 20-pin SOIC, 24-pin SOIC and 24-pin QSOP packages
• Industry standard programmer support
2.0 Functional Overview
The CY7C630/1XXA is a fam ily of 8-bit RISC One Time Prog rammable (OTP) m icrocontrollers wi th a built -in 1.5-Mbps USB Serial
Interface Engine (SIE). The microcontroller features 35 instructions that are optimized for USB applications. In addition, the
microcontroller features 128 bytes of internal RAM and either 2 or 4 Kbytes of program memory space. The Cypress USB
Controller accepts a 6-MHz ceramic resonator as its clock source. This clock signal is doubled within the chip to provide a 12MHz clock for the microproc es so r.
The microcontroller features two ports of up to sixteen general purpose I/Os (GPIOs). Each GPIO pin can be used to generate
an interrupt to the microcont roll er. Additionally , all pins in Port 1 are equipped with programm able drivers strong enough to drive
LEDs. The GPIO ports feature low EMI emissions as a result of controlled rise and fall times and unique output driver circuits.
The Cypress microcontrollers have a range of GPIOs to fit various applications; the CY7C6300XA has twelve GPIOs and the
CY7C6310XA has six teen GP IOs. Noti ce tha t each p ar t has eight ‘low-current’ ports (Port 0) with the remaining ports (Port 1)
being ‘high-current’ ports.
The twelve GPIO CY7C6300XA is available in 20-pin PDIP (-PC) and 20-pin SOIC (-SC) packages. The sixteen GPIO
CY7C6310XA is available in 24-pin S OIC (-SC) and 24-pin QSOP (- QC) packages.
4
Logic Block Diagram
6-MHz
CERAMIC RESONATOR
FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
R/C
EXT
EPROM
2/4 KByte
Power-
on Reset
Watch
Dog
Timer
OSC
INSTANT-ON
8-bit
RISC
core
Interrupt
Controller
20-pin
DIP/SOIC
NOW™
USB
Engine
D+,D–
VCC/V
RAM
128-Byte
PORT
0
P0.0–P0.7
SS
Pin Configurations (Top View)
8-bit
Timer
PORT
1
P1.0–P1.7
24-pin
SOIC/QSOP
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
V
V
CEXT
XTALIN
P0.0
P0.4
20
1
19
18
17
16
15
14
13
12
11
P0.5
P0.6
P0.7
P1.1
P1.3
D+
D–
V
CC
XTALOUT
XTALIN
2
3
4
5
6
7
SS
8
PP
9
10
P0.1
P0.2
P0.3
P1.0
P1.2
P1.4
P1.6
V
V
CEXT
1
2
3
4
5
6
7
8
9
SS
10
PP
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
D+
D–
V
CC
XTALOUT
63xxxA–1
5
FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
3.0 Pin Definitions
NameI/O20-Pin24-pinDescription
P0.0I/O11Port 0 bit 0
P0.1I/O22Port 0 bit 1
P0.2I/O33Port 0 bit 2
P0.3I/O44Port 0 bit 3
P0.4I/O2024Port 0 bit 4
P0.5I/O1923Port 0 bit 5
P0.6I/O1822Port 0 bit 6
P0.7I/O1721Port 0 bit 7
P1.0I/O55Port 1 bit 0
P1.1I/O1620Port 1 bit 1
P1.2I/O66Port 1 bit 2
P1.3I/O1519Port 1 bit 3
P1.4I/O–7Port 1 bit 4
P1.5I/O–18Port 1 bit 5
P1.6I/O–8Port 1 bit 6
P1.7I/O–17Port 1 bit 7
XTALINI1012Ceramic resonator in
XTALOUTO1113Ceramic resonator out
CEXTI/O911Connects to external R/C timing circuit for optional ‘suspend’ wakeup
D+I/O1416USB data+
D–I/O1315USB data–
V
PP
V
CC
V
SS
–810Programming voltage supply, tie to ground during normal operation
–1214Voltage supply
–79Ground
4.0 Pin Description
NameDescription
V
CC
V
SS
V
PP
XTALIN1 pin. Input from an external ceramic resonator.
XT ALOUT1 pin. Return path for the ceramic resonator ( leave unco nnected if driving XTALIN from an e xternal oscillator).
P0.0–P0.7,
P1.0–P1.7
D+, D–2 pins. Bidirectional USB data lin es . An e x ternal pull-up resistor m us t be co nnecte d betw een the D pi n and
CEXT1 pin. Open-drain o utput with Schmitt trigger input. The in put is connected to a rising edge-t riggered interrupt.
1 pin. Connects to the USB power source or to a nominal 5V power supply. Actual VCC range can vary
between 4.0V and 5.25V.
1 pin. Connects to ground.
1 pin. Used in prog ramming the on-ch ip EPROM. This pin sh ould be tied to gr ound during normal operations .
16 pins. P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. P1.0–P1.3 are
supported in the CY7C6300XA. All I/O pins include bit-programmable pull-up resistors. However, the sink
current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each
pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
to select low-speed USB operation.
V
CC
CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See Section 5.4.
6
FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
5.0 Functional Description
The Cypress CY7C630/1XXA USB microcontrollers are optimized for human-interface computer peripherals such as a mouse,
joystic k, and game pad. These USB m icrocontroll ers conf orm to the low-s peed (1.5 Mb ps) requirem ents of the U SB Specifica tion
version 1.1. Each mic roc ont roll er is a sel f-co nta ine d un it w ith : a U SB int erface e ngi ne, US B tr ansc eivers, an 8-bit RIS C mi cro controller, a clock oscillator, timers, and program memory. Each microcontroller supports one USB device address and two
endpoints.
The 6 MHz clock is doubled to 12 MHz to drive the microcontroller. A RISC architecture with 35 instructions provides the best
balance between performance and product cost.
5.1Memory Organization
The memory in the USB C ontrol ler is organ iz ed in to us er prog ram mem ory in EPR OM space a nd dat a mem ory in SRAM s pace .
5.1.1Program Memory Organization
The program space of the CY7C63000A and CY7C63100A is 2 Kbytes each. For applications requiring more program space,
the CY7C63001A and CY7C63101A each offer 4 Kbytes of EPROM. The program memory space is divided into two functional
groups: interrupt vectors and program code.
The interrupt vectors occupy the first 16 bytes of the program space. Each vector is 2 bytes long. After a reset, the Program
Counter points to location zero of the program space.
Figure 5-1
shows the organization of the Program Memo ry Space.
5.1.2Security Fuse Bit
The Cypress USB microcontroller includes a security fuse bit. When the security fuse is programmed, the EPROM program
memory outputs 0xFF to the EPROM programmer, thus protecting the user’s cod e .
after resetAddress
PC0x0000Reset Vector
0x0002Interrupt Vector - 128 µs
0x0004Interrupt Vector - 1.024 ms
0x0006Interrupt Vector - USB Endpoint 0
0x0008Interrupt Vector - USB Endpoint 1
0x000AReserved
0x000CInterrupt Vector - GPIO
0x000EInterrupt Vector - Cext
0x0010On-chip program Memory
0x07FF2K ROM (CY7C63000A, CY7C63100A)
0x0FFF4K ROM (CY7C63001A, CY7C6310 1A)
Figure 5-1. Program Memory Space
7
FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
5.1.3Data Memory Organization
The USB Controller includes 128 b ytes of data RAM. The upper 16 byte s of the data memory are used as USB FIFOs for Endpoint
0 and Endpoint 1. Each endpoint is associated with an 8-byte FIFO.
The USB controller includes two pointers into data RAM, the Program Stack Pointer (PSP) and the Data Stack Pointer (DSP).
The value of PSP after reset is 0x00. The PSP increments by 2 whenever a CALL instruction is executed and it decrements by
2 whenever a RET instruction is used.
The DSP pre-decrements by 1 whenever a PUSH instruction is executed and it increments by 1 after a POP instruction is used.
The default v al ue of the DSP after rese t is 0x00 , which wou ld cause the fir st PUSH to write into USB FIFO space f or Endpoin t 1.
Therefore , the DSP sh oul d be m app ed to a loca tio n su ch as 0x 70 be fore initiating an y data s tack operations. Refer to the Res et
section for more information about DSP remapping after reset.
Figure 5-2
illustrates the Data Memory Space.
after reset
DSPPSP
Address
0x00
0x02
0x04
user
firmware
DSP
0x70USB FIFO - Endpoint 0
0x77
0x78USB FIFO - Endpoint 1
0x7F
Figure 5-2. Data Memory Space
8
FOR
FOR
CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A
5.2I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions.
T a b le 5-1. I/O Registe r Summ ary
Register NameI/O AddressRead/WriteFunctionPage
P0 Data0x00R/WGeneral purpose I/O Port (low current)12
P1 Data0x01R/WGeneral purpose I/O Port (high current)12
P0 IE0x04WInterrupt enable for Port 0 pins15
P1 IE0x05WInterrupt enable for Port 1 pins15
P0 Pull-up0x08WPull-up resistor control for Port 0 pins13
P1 Pull-up0x09WPull-up resistor control for Port 1 pins13
EP0 TX Config.0x10R/WUSB Endpoint 0 transmit configuration18
EP1 TX Config.0x11R/WUSB Endpoint 1 transmit configuration19
USB DA0x12R/WUSB device address17
USB SCR0x13R/WUSB status and control19
EP0 RX Status0x14R/WUSB Endpoint 0 receive status17
GIE0x20R/WGlobal Interrupt Enable14
WDT0x21WWatch Dog Timer clear10
Cext0x22R/WExternal R-C Timing circuit control11
Timer0x23RFree-running timer 11
P0 Isink0x30-0x37WInput sink current control for Port 0 pins. There is
one Isink register f or each pin. Address of th e Isink
register for pin 0 is located at 0x30 and the regis ter
address for pin 7 is located at 0x37.
P1 Isink0x38-0x3FWInput sink current control for Port 1 pins. There is
one Isink register f or each pin. Address of th e Isink
register for pin 0 is located at 0x38 and the regis ter
address fo r pin 7 is loca ted at 0x3F. The n umber of
Port 1 pins depends on package type.
SCR0xFFR/WProcessor status and control register10
13
13
5.3Reset
The USB Controller suppo rts three types of resets. All registers are restored to their defau lt states during a reset. The USB Device
Address is set to 0 and all interrupts are disab led. In ad dition, the Prog ram Stac k P oin ter (PSP) is set to 0x00 and th e Data Stack
Pointer (DSP) is set to 0x00. The user should set the DSP to a location such as 0x70 to reserve 16 bytes of USB FIFO space.
The assembly instructions to do so are:
MOV A, 70h; Move 70 hex int o Accum ulat or, use 70 instead of 6F because the dsp is
SWAP A, DSP; Move Accumulator value into dsp
The three reset types are:
1. Power-On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Reset
The occurrence of a reset is rec orde d in the Sta tus and Co ntro l R egi st er loc at ed at I /O a ddre ss 0xFF (
writing this regist er are sup ported by the IOR D and IO WR i nstructions . Bits 1 , 2, and 7 are reserve d and m ust be written as z eros
during a write. During a read, reserv ed bit positions sh ould be ignored . Bits 4, 5, and 6 are us ed to record the occ urrence of POR,
USB, and WDR Reset respectively. The firmware can interrogate these bits to determine the cause of a reset. If a Watch Dog
Reset occurs, f irmware m ust cle ar the WDR bit (b it 6) in the Statu s and Co ntrol Regi ster to re -enab le the USB tran smitter (please
refer to the Watch Dog Reset section for further details). Bit 0, the “Run” control, is set to 1 at POR. Clearing this bit stops the
microcontroller (firmware normally should not clear this bit). Once this bit is set to LOW, only a reset can set this bit HIGH.
The microcontroller resumes execution from ROM address 0x00 after a reset unless the Suspend bit (bit 3) of the Status and
Control Register is set. Setting the Suspend bit stops the cloc k oscill ator and the interrupt tim ers and po wers do wn the mi crocon-
; always decremented by 1 before the data transfer of the PUSH instruction occurs
Figure 5-3
9
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