CYPRESS CY7C63000A, CY7C63001A, CY7C63100A, CY7C63101A User Manual

3000A
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
CY7C63000A CY7C63001A CY7C63100A CY7C63101A Universal Serial Bus Microcontroller
Cypress Semiconductor Corporation
3901 North First Street San Jose CA 95134 408-943-2600 April 24, 2000
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
TABLE OF CONTENTS
1.0 FEATURES ......................................................................... .. .. ......................... .. .. .. ..........................4
2.0 FUNCTIONAL OVERVIEW ........................................................ .. .... .. .................................. .. .. ........4
3.0 PIN DEFINITIONS ............................................................................................................................6
4.0 PIN DESCRIPTION .............................. .. ............................... .. ............................... ..........................6
5.0 FUNCTIONAL DESCRIPTION ................................................. .. ...................... .. ..............................7
5.1 Memory Organization ................................................. ....................... ........................ .. .. .................7
5.1.1 Program Memory Organization ............................................................................................................7
5.1.2 Security Fuse Bit ...................................................................................................................................7
5.1.3 Data Memory Organization ...................................................................................................................8
5.2 I/O Register Summary ....................................................................................................................9
5.3 Reset ................................................................................................................................................9
5.3.1 Power-On Reset (POR) ........................................................................................................................10
5.3.2 Watch Dog Reset (WDR) .....................................................................................................................10
5.3.3 USB Bus Reset ....................................................................................................................................10
5.4 Instant-on Feature (Suspend Mode) .................................................. ...................... ...................10
5.5 On-Chip Timer ...............................................................................................................................11
5.6 General Purpose I/O Ports ........................................................................................................... 12
5.7 XTALIN/XTALOUT .........................................................................................................................13
5.8 Interrupts .......................................................................................................................................14
5.8.1 Interrupt Latency .................................................................................................................................15
5.8.2 GPIO Interrupt ......................................................................................................................................15
5.8.3 USB Interrupt .......................................................................................................................................16
5.8.4 Timer Interrupt .....................................................................................................................................16
5.8.5 Wake-Up Interrupt ...............................................................................................................................16
5.9 USB Engine ...................................................................................................................................16
5.9.1 USB Enumeration Process .................................................................................................................17
5.9.2 Endpoint 0 ............................................................................................................................................17
5.9.2.1 Endpoint 0 Receive ......................................................................................................................................17
5.9.2.2 Endpoint 0 Transmit .....................................................................................................................................18
5.9.3 Endpoint 1 ............................................................................................................................................19
5.9.3.1 Endpoint 1 Transmit .....................................................................................................................................19
5.9.4 USB Status and Control ......................................................................................................................19
5.10 USB Physical Layer Characteristics ........................................................... .. ...................... .. .. ..20
5.10.1 Low-Speed Driver Characteristics ...................................................................................................20
5.10.2 Receiver Characteristics ...................................................................................................................20
5.11 External USB Pull-Up Resistor ............................................ .............................................. .. ......21
5.12 Instruc ti o n S e t S u mmary ....................... .. ............... ................ .. ................ ............... ..................22
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................23
7.0 ELECTRICAL CHARACTERISTICS ................................... .. ...................... ...................................24
8.0 SWITCHING CHARACTERISTICS .............................................................................................. ..26
9.0 ORDERING INFORMATION ................................................................... .. .. ........................... .. .. ....28
10.0 PACKAGE DIAGRAMS ............................................................................................................... 29
2
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
LIST OF FIGURES
Figure 5-1. Program Memory Space ....................................................................................................7
Figure 5-2. Data Memory Space ...........................................................................................................8
Figure 5-4. Watch Dog Reset (WDR)........................ ...................... ...................... ..............................10
Figure 5-3. Status and Control Register (SCR - Address 0xFF)................. .................... .................10
Figure 5-5. The Cext Register (Address 0x22).................................................... .. ............................11
Figure 5-6. Timer Register (Address 0x23).................... .. .................... .................... .................... .. ....11
Figure 5-7. Timer Block Diagram........................................................................................................11
Figure 5-8. Port 0 Data Register (Address 0x00) ........................ .. .................... .................... .. ..........12
Figure 5-9. Port 1 Data Register (Address 0x01) ........................ .. .................... .................... .. ..........12
Figure 5-10. Bl o c k Dia g ram of an I/O Line..... .. ............... ................ ............... ................ .. ..................12
Figure 5-11. Port 0 Pull-Up Register (Address 0x08)............... .................. .................. .....................13
Figure 5-12. Port 1 Pull-Up Register (Address 0x09)............... .................. .................. .....................13
Figure 5-13. Port Isink Regist e r fo r On e GP IO Line............ ............... ................ ............... ................ 13
Figure 5-14. Clock Oscillator On-Chip Circuit...................................................................................14
Figure 5-16. Interrupt Controller Logic Block Diagram................................. .................... ...............14
Figure 5-15. Global Interrupt Enable Register (GIER - Address 0x20).................. .. .................... .. ..14
Figure 5-17. Port 0 Interrupt Enable Register (P0 IE - Address 0x04)................. .................... ........15
Figure 5-18. Port 1 Interrupt Enable Register (P1 IE - Address 0x05)................. .................... ........15
Figure 5-19. GPIO Interrupt Logic Block Diagram............................................................................16
Figure 5-20. USB Device Address Register (USB DA - Address 0x12).......................... .. ...............17
Figure 5-21. USB Endpoint 0 RX Register (Address 0x14).............. .. ...................... ........................17
Figure 5-22. USB Endpoint 0 TX Configuration Register (Address 0x10)......................................18
Figure 5-23. USB Endpoint 1 TX Configuration Register (Address 0x11)......................................19
Figure 5-24. USB Status and Control Register (USB SCR - Address 0x13).............. .. ...................19
Figure 5-25. Low Speed Driver Signal Waveforms........................... .................. .................. ............20
Figure 5-27. Application Showing 7.5kW±1% Pull-Up Resistor.......................................................21
Figure 5-26. Differential Input Sensitivity Over Entire Common Mode Range...............................21
Figure 5-28. Application Showing 1.5kW±5% Pull-Up Resistor.......................................................22
Figure 8-1. Clock Timing...................................... ............................................................ .. ................. 27
Figure 8-2. USB Data Signal Timing and Voltage Levels.................................................................27
Figure 8-3. Receiver Jitter Tolerance.................................. .................... .................... .. .....................27
Figure 8-4. Differential to EOP Transition Skew and EOP Width..................................... ...............28
Figure 8-5. Differential Data Jitter ......................................................................................................28
LIST OF TABLES
Table 5-1. I/O Register Summary .......................... ................ ................. ................................. ...............9
Table 5-2. Output Control Truth Table ................................. ..................... .................. .. ........................13
Table 5-3. Interrupt Vector Assignments ...................... ........................................................................15
Table 5-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0 ..........................18
Table 5-5. Instruction Set Map .................................. .. ..................................... .................. ...................22
2
3
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
1.0 Features
• Low-cost solution for low-speed USB peripherals such as mouse, joystick, and gamepad
• USB Specification Compliance —Conforms to USB 1.5 Mbps Specification, Version 1.1
—Supports 1 device address and 2 endpoints (1 control endpoint and 1 data endpoint)
• 8-bit RISC microcontroller —Harvard architecture
—6-MHz external ceramic resonator —12-MHz internal operation —USB optimized instruction set
• Internal memory —128 bytes of RAM
—2 Kbytes of EPROM (CY7C63000A, CY7C63100A) —4 Kbytes of EPROM (CY7C63001A, CY7C63101A)
•I/O ports —Integrated USB transceiver
—Up to 16 Schmitt trigger I/O pins with internal pull-up —Up to 8 I/O pins with LED drive capability —Special purpose I/O mode supports optimization of photo transistor and LED in mouse application —Maskable Interrupts on all I/O pins
• 8-bit free-running timer
• Watch dog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up Modes
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0 to 70 degree Celsius
• Available in space saving and low cost 20-pin PDIP, 20-pin SOIC, 24-pin SOIC and 24-pin QSOP packages
• Industry standard programmer support
2.0 Functional Overview
The CY7C630/1XXA is a fam ily of 8-bit RISC One Time Prog rammable (OTP) m icrocontrollers wi th a built -in 1.5-Mbps USB Serial Interface Engine (SIE). The microcontroller features 35 instructions that are optimized for USB applications. In addition, the microcontroller features 128 bytes of internal RAM and either 2 or 4 Kbytes of program memory space. The Cypress USB Controller accepts a 6-MHz ceramic resonator as its clock source. This clock signal is doubled within the chip to provide a 12­MHz clock for the microproc es so r.
The microcontroller features two ports of up to sixteen general purpose I/Os (GPIOs). Each GPIO pin can be used to generate an interrupt to the microcont roll er. Additionally , all pins in Port 1 are equipped with programm able drivers strong enough to drive LEDs. The GPIO ports feature low EMI emissions as a result of controlled rise and fall times and unique output driver circuits. The Cypress microcontrollers have a range of GPIOs to fit various applications; the CY7C6300XA has twelve GPIOs and the CY7C6310XA has six teen GP IOs. Noti ce tha t each p ar t has eight ‘low-current’ ports (Port 0) with the remaining ports (Port 1) being high-current ports.
The twelve GPIO CY7C6300XA is available in 20-pin PDIP (-PC) and 20-pin SOIC (-SC) packages. The sixteen GPIO CY7C6310XA is available in 24-pin S OIC (-SC) and 24-pin QSOP (- QC) packages.
4
Logic Block Diagram
6-MHz
CERAMIC RESONATOR
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
R/C
EXT
EPROM
2/4 KByte
Power-
on Reset
Watch
Dog
Timer
OSC
INSTANT-ON
8-bit
RISC
core
Interrupt Controller
20-pin
DIP/SOIC
NOW
USB
Engine
D+,D– VCC/V
RAM
128-Byte
PORT
0
P0.0–P0.7
SS
Pin Configurations (Top View)
8-bit
Timer
PORT
1
P1.0–P1.7
24-pin
SOIC/QSOP
P0.0 P0.1 P0.2 P0.3 P1.0 P1.2
V V
CEXT
XTALIN
P0.0
P0.4
20
1
19 18 17 16 15 14 13 12 11
P0.5 P0.6 P0.7 P1.1 P1.3 D+ D– V
CC
XTALOUT
XTALIN
2 3 4 5 6 7
SS
8
PP
9 10
P0.1 P0.2 P0.3 P1.0 P1.2 P1.4 P1.6
V V
CEXT
1 2 3 4 5 6 7 8 9
SS
10
PP
11 12
24 23 22 21 20 19 18 17 16 15 14 13
P0.4 P0.5
P0.6 P0.7
P1.1 P1.3 P1.5 P1.7 D+ D– V
CC
XTALOUT
63xxxA–1
5
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
3.0 Pin Definitions
Name I/O 20-Pin 24-pin Description
P0.0 I/O 1 1 Port 0 bit 0 P0.1 I/O 2 2 Port 0 bit 1 P0.2 I/O 3 3 Port 0 bit 2 P0.3 I/O 4 4 Port 0 bit 3 P0.4 I/O 20 24 Port 0 bit 4 P0.5 I/O 19 23 Port 0 bit 5 P0.6 I/O 18 22 Port 0 bit 6 P0.7 I/O 17 21 Port 0 bit 7 P1.0 I/O 5 5 Port 1 bit 0 P1.1 I/O 16 20 Port 1 bit 1 P1.2 I/O 6 6 Port 1 bit 2 P1.3 I/O 15 19 Port 1 bit 3 P1.4 I/O 7 Port 1 bit 4 P1.5 I/O 18 Port 1 bit 5 P1.6 I/O 8 Port 1 bit 6 P1.7 I/O 17 Port 1 bit 7 XTALIN I 10 12 Ceramic resonator in XTALOUT O 11 13 Ceramic resonator out CEXT I/O 9 11 Connects to external R/C timing circuit for optional ‘suspend’ wakeup D+ I/O 14 16 USB data+ D– I/O 13 15 USB data– V
PP
V
CC
V
SS
8 10 Programming voltage supply, tie to ground during normal operation 12 14 Voltage supply 7 9 Ground
4.0 Pin Description
Name Description
V
CC
V
SS
V
PP
XTALIN 1 pin. Input from an external ceramic resonator. XT ALOUT 1 pin. Return path for the ceramic resonator ( leave unco nnected if driving XTALIN from an e xternal oscillator). P0.0–P0.7,
P1.0–P1.7
D+, D– 2 pins. Bidirectional USB data lin es . An e x ternal pull-up resistor m us t be co nnecte d betw een the D pi n and
CEXT 1 pin. Open-drain o utput with Schmitt trigger input. The in put is connected to a rising edge-t riggered interrupt.
1 pin. Connects to the USB power source or to a nominal 5V power supply. Actual VCC range can vary between 4.0V and 5.25V.
1 pin. Connects to ground. 1 pin. Used in prog ramming the on-ch ip EPROM. This pin sh ould be tied to gr ound during normal operations .
16 pins. P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. P1.0–P1.3 are supported in the CY7C6300XA. All I/O pins include bit-programmable pull-up resistors. However, the sink current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
to select low-speed USB operation.
V
CC
CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See Section 5.4.
6
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
5.0 Functional Description
The Cypress CY7C630/1XXA USB microcontrollers are optimized for human-interface computer peripherals such as a mouse, joystic k, and game pad. These USB m icrocontroll ers conf orm to the low-s peed (1.5 Mb ps) requirem ents of the U SB Specifica tion version 1.1. Each mic roc ont roll er is a sel f-co nta ine d un it w ith : a U SB int erface e ngi ne, US B tr ansc eivers, an 8-bit RIS C mi cro ­controller, a clock oscillator, timers, and program memory. Each microcontroller supports one USB device address and two endpoints.
The 6 MHz clock is doubled to 12 MHz to drive the microcontroller. A RISC architecture with 35 instructions provides the best balance between performance and product cost.
5.1 Memory Organization
The memory in the USB C ontrol ler is organ iz ed in to us er prog ram mem ory in EPR OM space a nd dat a mem ory in SRAM s pace .
5.1.1 Program Memory Organization
The program space of the CY7C63000A and CY7C63100A is 2 Kbytes each. For applications requiring more program space, the CY7C63001A and CY7C63101A each offer 4 Kbytes of EPROM. The program memory space is divided into two functional groups: interrupt vectors and program code.
The interrupt vectors occupy the first 16 bytes of the program space. Each vector is 2 bytes long. After a reset, the Program Counter points to location zero of the program space.
Figure 5-1
shows the organization of the Program Memo ry Space.
5.1.2 Security Fuse Bit
The Cypress USB microcontroller includes a security fuse bit. When the security fuse is programmed, the EPROM program memory outputs 0xFF to the EPROM programmer, thus protecting the users cod e .
after reset Address
PC 0x0000 Reset Vector
0x0002 Interrupt Vector - 128 µs
0x0004 Interrupt Vector - 1.024 ms
0x0006 Interrupt Vector - USB Endpoint 0
0x0008 Interrupt Vector - USB Endpoint 1
0x000A Reserved
0x000C Interrupt Vector - GPIO
0x000E Interrupt Vector - Cext
0x0010 On-chip program Memory
0x07FF 2K ROM (CY7C63000A, CY7C63100A)
0x0FFF 4K ROM (CY7C63001A, CY7C6310 1A)
Figure 5-1. Program Memory Space
7
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
5.1.3 Data Memory Organization
The USB Controller includes 128 b ytes of data RAM. The upper 16 byte s of the data memory are used as USB FIFOs for Endpoint 0 and Endpoint 1. Each endpoint is associated with an 8-byte FIFO.
The USB controller includes two pointers into data RAM, the Program Stack Pointer (PSP) and the Data Stack Pointer (DSP). The value of PSP after reset is 0x00. The PSP increments by 2 whenever a CALL instruction is executed and it decrements by 2 whenever a RET instruction is used.
The DSP pre-decrements by 1 whenever a PUSH instruction is executed and it increments by 1 after a POP instruction is used. The default v al ue of the DSP after rese t is 0x00 , which wou ld cause the fir st PUSH to write into USB FIFO space f or Endpoin t 1. Therefore , the DSP sh oul d be m app ed to a loca tio n su ch as 0x 70 be fore initiating an y data s tack operations. Refer to the Res et section for more information about DSP remapping after reset.
Figure 5-2
illustrates the Data Memory Space.
after reset
DSP PSP
Address
0x00
0x02
0x04
user
firmware
DSP
0x70 USB FIFO - Endpoint 0
0x77
0x78 USB FIFO - Endpoint 1
0x7F
Figure 5-2. Data Memory Space
8
FOR
CY7C63000A/CY7C63001A CY7C63100A/CY7C63101A
5.2 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions.
T a b le 5-1. I/O Registe r Summ ary
Register Name I/O Address Read/Write Function Page
P0 Data 0x00 R/W General purpose I/O Port (low current) 12 P1 Data 0x01 R/W General purpose I/O Port (high current) 12 P0 IE 0x04 W Interrupt enable for Port 0 pins 15 P1 IE 0x05 W Interrupt enable for Port 1 pins 15 P0 Pull-up 0x08 W Pull-up resistor control for Port 0 pins 13 P1 Pull-up 0x09 W Pull-up resistor control for Port 1 pins 13 EP0 TX Config. 0x10 R/W USB Endpoint 0 transmit configuration 18 EP1 TX Config. 0x11 R/W USB Endpoint 1 transmit configuration 19 USB DA 0x12 R/W USB device address 17 USB SCR 0x13 R/W USB status and control 19 EP0 RX Status 0x14 R/W USB Endpoint 0 receive status 17 GIE 0x20 R/W Global Interrupt Enable 14 WDT 0x21 W Watch Dog Timer clear 10 Cext 0x22 R/W External R-C Timing circuit control 11 Timer 0x23 R Free-running timer 11 P0 Isink 0x30-0x37 W Input sink current control for Port 0 pins. There is
one Isink register f or each pin. Address of th e Isink register for pin 0 is located at 0x30 and the regis ter address for pin 7 is located at 0x37.
P1 Isink 0x38-0x3F W Input sink current control for Port 1 pins. There is
one Isink register f or each pin. Address of th e Isink register for pin 0 is located at 0x38 and the regis ter address fo r pin 7 is loca ted at 0x3F. The n umber of Port 1 pins depends on package type.
SCR 0xFF R/W Processor status and control register 10
13
13
5.3 Reset
The USB Controller suppo rts three types of resets. All registers are restored to their defau lt states during a reset. The USB Device Address is set to 0 and all interrupts are disab led. In ad dition, the Prog ram Stac k P oin ter (PSP) is set to 0x00 and th e Data Stack Pointer (DSP) is set to 0x00. The user should set the DSP to a location such as 0x70 to reserve 16 bytes of USB FIFO space. The assembly instructions to do so are:
MOV A, 70h ; Move 70 hex int o Accum ulat or, use 70 instead of 6F because the dsp is SWAP A, DSP ; Move Accumulator value into dsp
The three reset types are:
1. Power-On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Reset
The occurrence of a reset is rec orde d in the Sta tus and Co ntro l R egi st er loc at ed at I /O a ddre ss 0xFF ( writing this regist er are sup ported by the IOR D and IO WR i nstructions . Bits 1 , 2, and 7 are reserve d and m ust be written as z eros during a write. During a read, reserv ed bit positions sh ould be ignored . Bits 4, 5, and 6 are us ed to record the occ urrence of POR, USB, and WDR Reset respectively. The firmware can interrogate these bits to determine the cause of a reset. If a Watch Dog Reset occurs, f irmware m ust cle ar the WDR bit (b it 6) in the Statu s and Co ntrol Regi ster to re -enab le the USB tran smitter (please refer to the Watch Dog Reset section for further details). Bit 0, the “Run” control, is set to 1 at POR. Clearing this bit stops the microcontroller (firmware normally should not clear this bit). Once this bit is set to LOW, only a reset can set this bit HIGH.
The microcontroller resumes execution from ROM address 0x00 after a reset unless the Suspend bit (bit 3) of the Status and Control Register is set. Setting the Suspend bit stops the cloc k oscill ator and the interrupt tim ers and po wers do wn the mi crocon-
; always decremented by 1 before the data transfer of the PUSH instruction occurs
Figure 5-3
9
). Reading and
Loading...
+ 21 hidden pages