CYPRESS CY7C63001C, CY7C63101C User Manual
r
CY7C63001C
CY7C63101C
Universal Serial Bus Microcontrolle
1.0 Features
• Low-cost solution for low-speed USB peripherals such
as mouse, joystick, and gamepad
• USB Specification Compliance
—Conforms to USB 1.5 Mbps Specification, Version 1.1
—Supports 1 device address and 2 endpoints (1
control endpoint and 1 data endpoint)
• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator
—12-MHz internal operation
—USB optimized instruction set
• Internal memory
—128 bytes of RAM
—4 Kbytes of EPROM
Logic Block Diagram
6-MHz
CERAMIC RESONATOR
R/C
EXT
—Integrated USB transceiver
—Up to 16 Schmitt trigger I/O pins with internal pull-up
—Up to 8 I/O pins with LED drive capability
—Special purpose I/O mode supports optimization of
photo transistor and LED in mouse application
—Maskable Interrupts on all I/O pins
• 8-bit free-running timer
• Watch dog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up
Modes
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0 to 70 degree Celsius
• Available in space saving and low cost 20-pin PDIP,
20-pin SOIC, and 24-pin QSOP packages
• Industry standard programmer support
EPROM
2/4 KByte
Power-
on Reset
Watch
Dog
Timer
OSC
INSTANT-ON
8-bit
RISC
core
Interrupt
Controller
NOW™
USB
Engine
D+,D–
VCC/V
SS
RAM
128-Byte
PORT
P0.0–P0.7
8-bit
Timer
PORT
0
1
P1.0–P1.7
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-08026 Rev. *B Revised November 28, 2005
2.0 Pin Configurations
(Top View)
CY7C63001C
CY7C63101C
24-pin
SOIC/QSOP
P0.0
1
P0.1
2
P0.2
3
P0.3
4
P1.0
5
P1.2
6
P1.4
7
P1.6
8
V
9
SS
V
10
PP
11
12
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
V
V
CEXT
XTALIN
20-pin
DIP/SOIC
1
2
3
4
5
6
7
SS
8
PP
9
10
20
19
18
17
16
15
14
13
12
11
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
D+
D–
V
CC
XTALOUT
CEXT
XTALIN
3.0 Functional Overview
The CY7C630/101C is a family of 8-bit RISC One Time
Programmable (OTP) microcontrollers with a built-in 1.5-Mbps
USB Serial Interface Engine (SIE). The microcontroller
features 35 instructions that are optimized for USB applications. In addition, the microcontroller features 128 bytes of
internal RAM and 4 Kbytes of program memory space. The
Cypress USB Controller accepts a 6-MHz ceramic resonator
as its clock source. This clock signal is doubled within the chip
to provide a 12- MHz clock for the microprocessor.
The microcontroller features two ports of up to sixteen general
purpose I/Os (GPIOs). Each GPIO pin can be used to
generate an interrupt to the microcontroller. Additionally, all
P0.4
24
23
P0.5
P0.6
22
21
P0.7
P1.1
20
P1.3
19
18
P1.5
17
P1.7
16
D+
D–
15
V
14
CC
XTALOUT
13
pins in Port 1 are equipped with programmable drivers strong
enough to drive LEDs. The GPIO ports feature low EMI
emissions as a result of controlled rise and fall times and
unique output driver circuits. The Cypress microcontrollers
have a range of GPIOs to fit various applications; the
CY7C63001C has twelve GPIOs and the CY7C63101C has
sixteen GPIOs. Notice that each part has eight ‘low-current’
ports (Port 0) with the remaining ports (Port 1) being
‘high-current’ ports.
The 12-GPIO CY7C63001C is available in 20-pin PDIP (-PXC)
and 20-pin SOIC (-SXC) packages. The 16-GPIO
CY7C63101C is available in 24-pin QSOP (-QXC) package.
4.0 Pin Definitions
Name I/O 20-Pin 24-pin Die Pad # Description
P0.0 I/O 1 1 1 Port 0 bit 0
P0.1 I/O 2 2 2 Port 0 bit 1
P0.2 I/O 3 3 3 Port 0 bit 2
P0.3 I/O 4 4 4 Port 0 bit 3
P0.4 I/O 20 24 24 Port 0 bit 4
P0.5 I/O 19 23 23 Port 0 bit 5
P0.6 I/O 18 22 22 Port 0 bit 6
P0.7 I/O 17 21 21 Port 0 bit 7
P1.0 I/O 5 5 5 Port 1 bit 0
P1.1 I/O 16 20 20 Port 1 bit 1
P1.2 I/O 6 6 6 Port 1 bit 2
P1.3 I/O 15 19 19 Port 1 bit 3
P1.4 I/O – 7 7 Port 1 bit 4
P1.5 I/O – 18 18 Port 1 bit 5
P1.6 I/O – 8 8 Port 1 bit 6
P1.7 I/O – 17 17 Port 1 bit 7
XTALIN I 10 12 12 Ceramic resonator in
XTALOUT O 11 13 13 Ceramic resonator out
Document #: 38-08026 Rev. *B Page 2 of 28
CY7C63001C
CY7C63101C
4.0 Pin Definitions (continued)
Name I/O 20-Pin 24-pin Die Pad # Description
CEXT I/O 9 11 11 Connects to external R/C timing circuit for optional
D+ I/O141616USB data+
D– I/O131515USB data–
V
PP
V
CC
V
SS
– 8 10 10 Programming voltage supply, tie to ground during normal
– 12 14 14 Voltage supply
–799Ground
5.0 Pin Description
Name Description
V
CC
V
SS
V
PP
XTALIN 1 pin. Input from an external ceramic resonator.
XT ALOUT 1 pin. Return path for the ceramic resonator (leave unconnected if driving XTALIN from an external oscillator).
P0.0–P0.7,
P1.0–P1.7
D+, D– 2 pins. Bidirectional USB data lines. An external pull-up resistor must be connected between the D pin and
CEXT 1 pin. Open-drain output with Schmitt trigger input. The input is connected to a rising edge-triggered interrupt.
1 pin. Connects to the USB power source or to a nominal 5V power supply. Actual VCC range can vary
between 4.0V and 5.25V.
1 pin. Connects to ground.
1 pin. Used in programming the on-chip EPROM. This pin should be tied to ground during normal operations.
16 pins. P0.0–P0.7 are the 8 I/O lines in Port 0. P1.0–P1.7 are the 8 I/O lines in Port 1. P1.0–P1.3 are
supported in the CY7C63001C. All I/O pins include bit-programmable pull-up resistors. However, the sink
current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each
pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
V
to select low-speed USB operation.
CC
CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See Section 6.4.
‘suspend’ wakeup
operation
6.0 Functional Description
The Cypress CY7C630/101C USB microcontrollers are
optimized for human-interface computer peripherals such as
a mouse, joystick, and gamepad. These USB microcontrollers
conform to the low-speed (1.5 Mbps) requirements of the USB
specification version 1.1. Each microcontroller is a
self-contained unit with: a USB interface engine, USB transceivers, an 8-bit RISC microcontroller, a clock oscillator,
timers, and program memory. Each microcontroller supports
one USB device address and two endpoints.
The 6-MHz clock is doubled to 12 MHz to drive the microcontroller. A RISC architecture with 35 instructions provides the
best balance between performance and product cost.
6.1 Memory Organization
The memory in the USB Controller is organized into user
program memory in EPROM space and data memory in SRAM
space.
6.1.1 Program Memory Organization
The CY7C63001C and CY7C63101C each offer 4 Kbytes of
EPROM. The program memory space is divided into two
functional groups: interrupt vectors and program code.
The interrupt vectors occupy the first 16 bytes of the program
space. Each vector is 2 bytes long. After a reset, the Program
Counter points to location zero of the program space.
Figure 6-1 shows the organization of the Program Memory
Space.
6.1.2 Securi ty Fu se Bit
The Cypress USB microcontroller includes a security fuse bit.
When the security fuse is programmed, the EPROM program
memory outputs 0xFF to the EPROM programmer, thus
protecting the user’s code.
Document #: 38-08026 Rev. *B Page 3 of 28
after reset Address
PC 0x0000 Reset Vector
0x0002 Interrupt Vector - 128 µs
0x0004 Interrupt Vector - 1.024 ms
0x0006 Interrupt Vector - USB Endpoint 0
0x0008 Interrupt Vector - USB Endpoint 1
0x000A Reserved
0x000C Interrupt Vector - GPIO
0x000E Interrupt Vector - Cext
0x0010 On-chip program Memory
CY7C63001C
CY7C63101C
0x0FFF 4K ROM
Figure 6-1. Program Memory Space
Document #: 38-08026 Rev. *B Page 4 of 28
CY7C63001C
CY7C63101C
6.1.3 Data Memory Organization
The USB Controller includes 128 bytes of data RAM. The
upper 16 bytes of the data memory are used as USB FIFOs
for Endpoint 0 and Endpoint 1. Each endpoint is associated
with an 8-byte FIFO.
The USB controller includes two pointers into data RAM, the
Program Stack Pointer (PSP) and the Data Stack Pointer
(DSP). The value of PSP after reset is 0x00. The PSP increments by 2 whenever a CALL instruction is executed and it
decrements by 2 whenever a RET instruction is used.
after reset
DSP PSP
user
firmware
DSP
The DSP pre-decrements by 1 whenever a PUSH instruction
is executed and it increments by 1 after a POP instruction is
used. The default value of the DSP after reset is 0x00, which
would cause the first PUSH to write into USB FIFO space for
Endpoint 1. Therefore, the DSP should be mapped to a
location such as 0x70 before initiating any data stack operations. Refer to the Reset section for more information about
DSP remapping after reset. Figure 6-2 illustrates the Data
Memory Space.
Address
0x00
0x02
0x04
0x70 USB FIFO - Endpoint 0
0x77
0x78 USB FIFO - Endpoint 1
0x7F
Figure 6-2. Data Memory Space
Document #: 38-08026 Rev. *B Page 5 of 28
CY7C63001C
CY7C63101C
6.2 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O
Write (IOWR, IOWX) instructions.
Table 6-1. I/O Register Summary
Register Name I/O Address Read/Write Function Page
P0 Data 0x00 R/W General purpose I/O Port (low current) 9
P1 Data 0x01 R/W General purpose I/O Port (high current) 9
P0 IE 0x04 W Interrupt enable for Port 0 pins 12
P1 IE 0x05 W Interrupt enable for Port 1 pins 12
P0 Pull-up 0x08 W Pull-up resistor control for Port 0 pins 10
P1 Pull-up 0x09 W Pull-up resistor control for Port 1 pins 10
EP0 TX Config. 0x10 R/W USB Endpoint 0 transmit configuration 15
EP1 TX Config. 0x11 R/W USB Endpoint 1 transmit configuration 15
USB DA 0x12 R/W USB device address 14
USB SCR 0x13 R/W USB status and control 16
EP0 RX Status 0x14 R/W USB Endpoint 0 receive status 14
GIE 0x20 R/W Global Interrupt Enable 11
WDT 0x21 W Watch Dog Timer clear 7
Cext 0x22 R/W External R-C Timing circuit control 8
Timer 0x23 R Free-running timer 8
P0 Isink 0x30-0x37 W Input sink current control for Port 0 pins. There is
P1 Isink 0x38-0x3F W Input sink current control for Port 1 pins. There is
SCR 0xFF R/W Processor status and control register 7
one Isink register for each pin. Address of the Isink
register for pin 0 is located at 0x30 and the register
address for pin 7 is located at 0x37.
one Isink register for each pin. Address of the Isink
register for pin 0 is located at 0x38 and the register
address for pin 7 is located at 0x3F. The number
of Port 1 pins depends on package type.
10
10
6.3 Reset
The USB Controller supports three types of resets. All
registers are restored to their default states during a reset. The
USB Device Address is set to 0 and all interrupts are disabled.
In addition, the Program Stack Pointer (PSP) is set to 0x00 and
the Data Stack Pointer (DSP) is set to 0x00. The user should
set the DSP to a location such as 0x70 to reserve 16 bytes of
USB FIFO space. The assembly instructions to do so are:
MOV A, 70h ; Move 70 hex into Accumulator, use 70
instead of 6F because the dsp is
; always decremented by 1 before the
data transfer of the PUSH instruction occurs
SWAP A, DSP ; Move Accumulator value into dsp
The three reset types are:
1. Power-On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Reset
The occurrence of a reset is recorded in the Status and Control
Register located at I/O address 0xFF (Figure 6-3). Reading
Document #: 38-08026 Rev. *B Page 6 of 28
and writing this register are supported by the IORD and IOWR
instructions. Bits 1, 2, and 7 are reserved and must be written
as zeros during a write. During a read, reserved bit position s
should be ignored. Bits 4, 5, and 6 are used to record the
occurrence of POR, USB, and WDR Reset respectively. The
firmware can interrogate these bits to determine the cause of
a reset. If a Watch Dog Reset occurs, firmware must clear the
WDR bit (bit 6) in the Status and Control Register to re-enable
the USB transmitter (please refer to the Watch Dog Reset
section for further details). Bit 0, the “Run” control, is set to 1
at POR. Clearing this bit stops the microcontroller (firmware
normally should not clear this bit). Once this bit is set to LOW,
only a reset can set this bit HIGH.
The microcontroller resumes execution from ROM address
0x00 after a reset unless the Suspend bit (bit 3) of the Status
and Control Register is set. Setting the Suspend bit stops the
clock oscillator and the interrupt timers and powers down the
microcontroller. The detection of any USB activity, the occurrence of a GPIO Interrupt, or the occurrence of the Cext
Interrupt terminates the suspend condition.
CY7C63001C
CY7C63101C
b7 b6 b5 b4 b3 b2 b1 b0
Reserved WDR USBR POR SUSPEND Reserved Reserved RUN
R/W R/W R/W R/W R/W
0 0 0 1 0 0 0 1
Figure 6-3. Status and Control Register (SCR - Address 0xFF)
6.3.1 Power-On Reset (POR)
Power-On Reset (POR) occurs every time the power to the
device is switched on. Bit 4 of the Status and Control Register
is set to record this event (the register contents are set to
00011001 by the POR). The USB Controller is placed in
suspended mode at the end of POR to conserve power (the
clock oscillator, the timers, and the interrupt logic are turned
off in suspend mode). After POR, only a non-idle USB Bus
state terminates the suspend mode. The microcontroller then
begins execution from ROM address 0x00.
6.3.2 Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most
Significant Bit of the 4-bit Watch Dog Timer Register transitions from LOW to HIGH. Writing any value to the write-only
Watch Dog Rest art Register at 0x21 clears the tim er (firmware
should periodically write to the Watch Dog Restart Register in
the ‘main loop’ of firmware). The Watch Dog timer is clocked
by a 1.024-ms clock from the free-running timer. If 8 clocks
occur between writes to the timer, a WDR occurs and bit 6 of
the Status and Control Register is set to record the event. A
Watch Dog Timer Reset lasts for 8.192 ms, at which time the
microcontroller begins execution at ROM address 0x00. The
USB transmitter is disabled by a Watch Dog Reset because
the USB Device Address Register is cleared (otherwise, the
USB Controller would respond to all address 0 transactions).
The transmitter remains disabled until the WDR bit (bit 6) in
the Status and Control Register is reset to 0 by firmware.
6.3.3 USB Bus Reset
The USB Controller recognizes a USB Reset when a Sin gle
Ended Zero (SE0) condition persists for at least 8–16 µs (the
Reset may be recognized for an SE0 as short as 8 µs, but it is
always recognized for an SE0 longer than 16 µs). SE0 is the
condition in which both the D+ line and the D– line are LOW.
Bit 5 of the Status and Control Register is set to record this
event. If the USB reset happens while the device is
suspended, the suspend condition is cleared and the clock
oscillator is restarted. However, the microcontroller is not
released until the USB reset is removed.
6.4 Instant-on Feature (Suspend Mode)
The USB Controller can be placed in a low-power state by
setting the Suspend bit (bit 3) of the Status and Control
register. All logic blocks in the device are turned off except the
USB receiver, the GPIO interrupt logic, and the Cext interrupt
logic. The clock oscillator and the free-running and watch dog
timers are shut down.
The suspend mode is terminated when one of the following
three conditions occur:
1. USB activity
2. A GPIO interrupt
3. Cext interrupt
The clock oscillator, GPIO, and timers restart immediately
upon exiting suspend mode. The USB engine and microcontroller return to a fully functional state no more than 256 µs
later. Before servicing any interrupt requests, the microcontroller executes the instruction following the I/O write that
placed the device into suspend mode.
Both the GPIO interrupt and the Cext interrupt allow the USB
Controller to wake-up periodically and poll potentiometers,
optics, and other system components while maintaining a very
low average power consumption. The Cext Interrupt is
preferred for lowest power consumption.
For Cext to generate an “Instant-on” interrupt, the pin must be
connected to ground with an external capacitor and connected
to V
with an external resistor. A “0” is written to the Cext
CC
register located at I/O address 0x22 to discharge the capacitor.
Then, a “1” is written to disable the open-drain output driver. A
Schmitt trigger input circuit monitors the input and generates
a wake-up interrupt when the input voltage rises above the
input threshold. By changing the values of the external resistor
and capacitor, the user can fine tune the charge rate of the R-C
timing circuit. The format of the Cext register is shown in
7.168 to
8.192 ms
Last write to
Watchdog Timer
Register
Document #: 38-08026 Rev. *B Page 7 of 28
No write to WDT
register, so WDR
goes HIGH
Figure 1. Watch Dog Reset (WDR)
8.192 ms
Execution begins at
Reset Vector 0x00
CY7C63001C
CY7C63101C
Figure 6-4. Reading the register returns the value of the Cext
pin. During a reset, the Cext pin is HIGH.
b7 b6 b5 b4 b3 b2 b1 b0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved CEXT
0 0 0 0 0 0 0 1
Figure 6-4. The Cext Register (Address 0x22)
R/W
6.5 On-Chip Timer
The USB Controller is equipped with a free-running timer
driven by a clock one-sixth the resonator frequency. Bits 0
through 7 of the counter are readable from the read-only Timer
Register located at I/O address 0x23. The Timer Register is
cleared during a Power-On Reset and whenever Suspend
b7 b6 b5 b4 b3 b2 b1 b0
T.7 T.6 T.5 T.4 T.3 T.2 T.1 T.0
R R R R R R R R
0 0 0 0 0 0 0 0
Figure 6-5. Timer Register (Address 0x23)
mode is entered. Figure 6-5 illustrates the format of this
register and Figure 6-6 is its block diagram.
With a 6 MHz resonator, the timer resolution is 1 µs.
The timer generates two interrupts: the 128-µs interrupt and
the 1.024-ms interrupt.
1.024-ms interrupt
µs interrupt
128-
9
8
7
6
5
4
3
2
1
0
Resonator Clock/6
8
To Timer Register
Figure 6-6. Timer Block Diagram
Document #: 38-08026 Rev. *B Page 8 of 28
CY7C63001C
CY7C63101C
6.6 General Purpose I/O Ports
Interface with peripherals is conducted via as many as 16
GPIO signals. These signals are divided into two ports: Port 0
and Port 1. Port 0 contains eight lines (P0.0–P0.7) and Port 1
contains up to eight lines (P1.0–P1.7). The number of external
I/O pins depends on the package type. Both ports can be
accessed by the IORD, IOWR, and IOWX instructions. The
Port 0 data register is located at I/O address 0x00 while the
Port 1 data register is located at I/O address 0x01. The
contents of both registers are set HIGH during a reset. Refer
to Figures 6-7 and 6-8 for the formats of the data registers. In
addition to supporting general input/output functions, each I/O
line can trigger an interrupt to the microcontroller. Please refer
to the interrupt section for more details.
Each GPIO line includes an internal R
provides both the pull-up function and slew control. Two
factors govern the enabling and disabling of each resistor: the
state of its associated Port Pull-up register bit and the state of
the Data Register bit. NOTE: The control bits in the Port
Pull-up register are active LOW.
b7 b6 b5 b4 b3 b2 b1 b0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1
resistor. This resistor
up
Figure 6-7. Port 0 Data Register (Address 0x00)
A GPIO line is HIGH when a “1” is written to the Data Register
and a “0” is written to the respective Port Pull-up register.
Writing a “0” to the port Data Register disables the port’s
Pull-up resistor and outputs a LOW on the GPIO line
regardless of the setting in the Port Pull-up Register. The
output goes to a high-Z state if the Data Register bit and the
Port Pull-up Register bit are both “1”. Figure 6-9 illustrates the
block diagram of one I/O line. The Port Isink Register is used
to control the output current level and it is described later in
this section. NOTE: The Isink logic block is turned off during
suspend mode (please refer to the Instant-on Feature section
for more details). Therefore, to prevent higher I
during USB suspend mode, firmware must set ALL Port 0 and
Port 1 Data Register bits (which are not externally driven to a
known state), including those that are not bonded out on a
particular package, to “1” and all Port 0 and Port 1 Pull-Up
Register data bits to “0” to enable port pull-ups before setting
the Suspend bit (bit 3 of the Status and Control Register).
Table 6-2 is the Output Control truth table.
currents
CC
b7 b6 b5 b4 b3 b2 b1 b0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1
Figure 6-8. Port 1 Data Register (Address 0x01)
V
CC
Port Pull-Up
Register
R
Port Data
Register
Port Isink
Register
Suspend
Bit
Data Bus
Isink
DAC
Disable
Schmitt
Trigger
up
GPIO
Pin
Figure 6-9. Block Diagram of an I/O Line
Document #: 38-08026 Rev. *B Page 9 of 28
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