CYPRESS CY7C63001A, CY7C63101A User Manual
er
CY7C63001
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CY7C63101
Universal Serial Bus Microcontroll
1.0 Features
• Low-cost solution for low-speed USB peripherals such
as mouse, joystick, and gamepad
• USB Specification Compliance
—Conforms to USB 1.5-Mbps Specification,
Version 1.1
—Supports one device address and two endpoints
(one control endpoint and one data endpoint)
• 8-bit RISC microcontroller
—Harvard architecture
—6-MHz external ceramic resonator
—12-MHz internal operation
—USB optimized instruction set
• Internal memory
—128 bytes of RAM
—4 Kbytes of EPROM
Logic Block Diagram
6-MHz
CERAMIC RESONATOR
R/C
EXT
—Integrated USB transceiver
—Up to 16 Schmitt trigger I/O pi ns with internal pull-up
—Up to eight I/O pins with LED drive capability
—Special p urpose I/O m ode supp orts optimization of
photo transistor and LED in mouse application
—Maskable Interrupts on all I/O pins
• 8-bit free-running timer
• Watchdog timer (WDT)
• Internal power-on reset (POR)
• Instant-On Now™ for Suspend and Periodic Wake-up
Modes
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.25 VDC
• Operating temperature from 0–70°C
• Available in space saving and low-cost 20-pin PDIP,
20-pin SOIC, and 24-pin QSOP packages
• Industry-standard programmer support
EPROM
2/4 KByte
Power-
on Reset
Watch
Dog
Timer
OSC
INSTANT-ON
8-bit
RISC
core
Interrupt
Controller
NOW™
USB
Engine
D+,D–
VCC/V
SS
RAM
128-Byte
PORT
P0.0–P0.7
8-bit
Timer
PORT
0
1
P1.0–P1.7
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-08026 Rev. *A Revised October 5, 2004
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2.0 Pin Configurations
(Top View)
CY7C63001
CY7C63101
24-pin
SOIC/QSOP
P0.0
1
P0.1
2
P0.2
3
P0.3
4
P1.0
5
P1.2
6
P1.4
7
P1.6
8
V
9
SS
V
10
PP
11
12
P0.0
P0.1
P0.2
P0.3
P1.0
P1.2
V
V
CEXT
XTALIN
20-pin
DIP/SOIC
1
2
3
4
5
6
7
SS
8
PP
9
10
20
19
18
17
16
15
14
13
12
11
P0.4
P0.5
P0.6
P0.7
P1.1
P1.3
D+
D–
V
CC
XTALOUT
CEXT
XTALIN
3.0 Functional Overview
The CY7C630/101A is a family of 8-bit RISC One Time
Programmable (OTP) microc ontrollers with a built-in 1.5-Mbp s
USB Serial Interface Engine (SIE). The microcontroller
features 35 instructions that are optimized for USB applications. In addition, the microcontroller features 128 bytes of
internal RAM and four Kby tes of program memory sp ace. Th e
Cypress USB Controller accepts a 6-MHz ceramic resonator
as its cloc k source . This clock signal i s double d withi n the chi p
to provide a 12- MHz clock for the microprocessor.
The microcontroller features two ports of up to sixteen general
purpose I/Os (GPIOs). Each GPIO pin can be used to
generate an interrupt to the microcontroller. Additionally, all
CY7C63101A
DIE
P0.4
24
23
22
21
20
19
18
17
16
15
14
13
P0.5
P0.6
P0.7
P1.1
P1.3
P1.5
P1.7
D+
D–
V
CC
XTALOUT
4 3 2 1 24 23 22 21
5
6
7
8
13 14 15 16
9101112
20
19
18
17
pins in Port 1 are equipped with programmable drivers strong
enough to drive LEDs. The GPIO ports feature low EMI
emissions as a result of controlled rise and fall times and
unique output driver circuits. The Cypress microcontrollers
have a range of GPIOs to fit various applications; the
CY7C6300XA has twelve GPIOs and the CY7C6310XA has
sixteen GPIOs. Notice that each part has eight ‘low-current’
ports (Port 0) with the remaining ports (Port 1) being ‘highcurrent’ ports.
The 12-GPIO CY7C6300XA is available in 20-pin PDIP (-PC)
and 20-pin SOIC (-SC) packages. The 26-GPIO
CY7C6310XA is available in 24-pin QSOP (-QC) package.
4.0 Pin Definitions
Name I/O 20-Pin 24-pin Die Pad # Description
P0.0 I/O 1 1 1 Port 0 bit 0
P0.1 I/O 2 2 2 Port 0 bit 1
P0.2 I/O 3 3 3 Port 0 bit 2
P0.3 I/O 4 4 4 Port 0 bit 3
P0.4 I/O 20 24 24 Port 0 bit 4
P0.5 I/O 19 23 23 Port 0 bit 5
P0.6 I/O 18 22 22 Port 0 bit 6
P0.7 I/O 17 21 21 Port 0 bit 7
P1.0 I/O 5 5 5 Port 1 bit 0
P1.1 I/O 16 20 20 Port 1 bit 1
P1.2 I/O 6 6 6 Port 1 bit 2
P1.3 I/O 15 19 19 Port 1 bit 3
P1.4 I/O – 7 7 Port 1 bit 4
P1.5 I/O – 18 18 Port 1 bit 5
P1.6 I/O – 8 8 Port 1 bit 6
P1.7 I/O – 17 17 Port 1 bit 7
XT ALI N I 10 12 12 Ceramic resonator in
XT ALO UT O 11 13 13 Ceramic resona tor out
Document #: 38-08026 Rev. *A Page 2 of 25
CY7C63001
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4.0 Pin Definitions (continued)
Name I/O 20-Pin 24-pin Die Pad # Description
CEXT I/O 9 11 11 Connects to external R/C timing circuit for optional
‘suspend’ wakeup
D+ I/O 14 16 16 USB data+
D– I/O 13 15 15 USB data–
V
PP
V
CC
V
SS
5.0 Pin Description
Name Description
V
CC
V
SS
V
PP
XTALIN One pin. Input from an external ceramic resonator.
XTALOUT One pin. Return path for the ceramic resonator (leave unconnected if driving XTALIN from an external
P0.0–P0.7,
P1.0–P1.7
D+, D– Two pins. Bidirectional USB data lines. An external pull-up resistor must be connected between the D pin
CEXT One pin. Open-drain output with Schmitt trigger input. The input is connected to a rising edge-triggered
– 8 1 0 10 Programming volt age supp ly , tie to groun d during no rmal
– 12 14 14 Voltage supply
– 7 9 9 Ground
One pin. Connects to the USB power source or to a nominal 5V power supply. Actual VCC range can vary
between 4.0V and 5.25V.
One pin. Connects to ground.
One pin. Used in prog ramming the o n-chip EPROM . This pin should be tied to groun d during norm al opera-
tions.
oscillator).
Sixteen pins. P0.0– P0.7 are t he 8 I/O l ines in Po rt 0. P1 .0–P1.7 are t he 8 I/O l ines in Port 1. P1 .0–P1.3 are
supported in the CY7C6300XA. All I/O pins include bit-programmable pull-up resistors. However, the sink
current of each pin can be programmed to one of sixteen levels. Besides functioning as GPIO lines, each
pin can be programmed as an interrupt input. The interrupt is edge-triggered, with programmable polarity.
and V
interrupt. CEXT may be connected to an external RC to generate a wake-up from Suspend mode. See
Section 6. 4.
to select low-speed USB operation.
CC
operation
CY7C63101
6.0 Functional Description
The Cypress CY7C630/101A USB microcontrollers are
optimized for human-interface computer peripherals such as
a mouse, joystic k, and ga mepad . These USB microcon trollers
conform to the low-spe ed (1.5 Mbps) req uirement s of the USB
Specification version 1.1. Each microcontroller is a selfcontained unit w ith: a USB interface engine, USB transceivers,
an 8-bit RISC microcontroller, a clock oscillator, timers, and
program memory. Each microcontroller supports one USB
device address and two endpoints.
The 6-MHz clock is doubled to 12 MHz to drive the microcontroller. A RISC architecture with 35 instructions provides the
best balance between performance and product cost.
6.1.1 Program Memory Organization
The CY7C63001A and CY7C63101A each offer 4 Kbytes of
EPROM. The program memory space is divided into two
functional groups: interrupt vectors and program code.
The interrupt vectors occupy the first 16 bytes of the program
space. Each vec to r is 2 by tes l ong . Af t er a res et, th e Pro gram
Counter points to location zero of the program space. Figure
6-1 shows the organization of the Program Memory Space.
6.1.2 Security Fuse Bit
The Cypress USB microc ont roll er i ncl udes a security fus e bi t.
When the security fuse is programmed, the EPROM program
memory outputs 0xFF to the EPROM programmer, thus
protecting the user’s code.
6.1 Memory Organization
The memory in the USB Controller is organized into user
program memory in EPROM space and data memory in SRAM
space.
Document #: 38-08026 Rev. *A Page 3 of 25
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after reset Address
PC 0x0000 Reset Vector
0x0002 Interrupt Vector – 128 µs
0x0004 Interrupt Vector – 1.024 ms
0x0006 Interrupt Vector – USB Endpoint 0
0x0008 Interrupt Vector – USB Endpoint 1
0x000A Reserved
0x000C Interrupt Vector – GPIO
0x000E Interrupt Vector – Cext
0x0010 On-chip program Memory
CY7C63001
CY7C63101
0x07FF 2K ROM (CY7C63000A, CY7C63100A)
0x0FFF 4K ROM (CY7C63001A, CY7C63101A)
Figure 6-1. Program Memory Space
6.1.3 Data Memory Organization
The USB Controller includes 128 bytes of data RAM. The
upper 16 bytes of the data memory are used as USB FIFOs
for Endpoint 0 and Endpoint 1. Ea ch endpoint is as sociated
with an 8-byte FIFO.
The USB controller includes two pointers into data RAM, the
Program Stack Pointer (PSP) and the Data Stack Pointer
(DSP). The value of PSP after reset is 0x00. The PSP increments by two whenever a CALL instruction is executed and it
decrements by two whenever a RET instru ction is used .
The DSP pre-decrements by one whenever a PUSH
instruction is executed and it increments by one after a POP
instruction is used. The defau lt v alu e of the DSP af ter res et i s
0x00, which would cause the first PUSH to write into USB
FIFO space for Endpoint 1. Therefore, the DSP should be
mapped to a location such as 0x70 before initiating any data
stack operations. Refer to the Reset section for more information about DSP remapping af ter reset. Figure 6-2 i llustrates
the Data Memory Space.
Document #: 38-08026 Rev. *A Page 4 of 25
CY7C63001
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CY7C63101
after reset
DSP PSP
user
firmware
DSP
0x77
0x7F
Figure 6-2. Data Memory Space
Address
0x00
0x02
0x04
0x70 USB FIFO – Endpoint 0
0x78 USB FIFO – Endpoint 1
6.2 I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O
Write (IOWR, IOWX) instruc tions.
Table 6-1. I/O Register Summary
Register Name I/O Address Read/Write Function Page
P0 Data 0x00 R/W General purpose I/O Port (low current) Figure 6-8
P1 Data 0x01 R/W General purpose I/O Port (high current) Figure 6-9
P0 IE 0x04 W Interrupt enable for Port 0 pins Figure 6-17
P1 IE 0x05 W Interrupt enable for Port 1 pins Figure 6-18
P0 Pull-up 0x08 W Pull-up resistor control for Port 0 pins Figure 6-11
P1 Pull-up 0x09 W Pull-up resistor control for Port 1 pins Figure 6-12
EP0 TX Config. 0x10 R/W USB Endpoint 0 transmit configuration Figure 6-22
EP1 TX Config. 0x11 R/W USB Endpoint 1 transmit configuration Figure 6-23
USB DA 0x12 R/W USB device address Figure 6-20
USB SCR 0x13 R/W USB status and control Figure 6-24
EP0 RX Status 0x14 R/W USB Endpoint 0 receive status Figure 6-21
GIE 0x20 R/W Global Interrupt Enable Figure 6-15
WDT 0x21 W Watchdog Timer clear Figure 6-4
Cext 0x22 R/W External R-C Timing circuit control Figure 6-5
Timer 0x23 R Fre e-ru nni ng timer Figure 6-6
P0 Isink 0x30-0x37 W Input sink current control for Port 0 pins. There is one
Isink register for each pin. Address of the Isink register
for pin 0 is located at 0x30 and the register address for
pin 7 is located at 0x37.
Figure 6-13
Document #: 38-08026 Rev. *A Page 5 of 25
CY7C63001
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Table 6-1. I/O Register Summary (continued)
Register Name I/O Address Read/Write Function Page
P1 Isink 0x38-0x3F W Input sink current control for Port 1 pins. There is one
Isink register for each pin. Address of the Isink register
for pin 0 is located at 0x38 and the register address for
pin 7 is located at 0x3F. The number of Port 1 pins
depends on package type.
SCR 0xFF R/W Processor status and control register Figure 6-3
CY7C63101
Figure 6-13
6.3 Reset
The USB Controller supports three types of resets. All
registers are restored to theirW atchdog defaul t states during a
reset. The USB Device Address is set to 0 and all interrupts
are disabled. In addition, the Program Stack Pointer (PSP) is
set to 0x00 and the Data Stack Pointer (DSP) is set to 0x00.
The user should set the DSP to a location such as 0x70 to
reserve 16 bytes of USB F IFO spac e. The assem bly in struc tions to do so are:
MOV A, 70h ; Move 70 hex into Accumulator, use 70
instead of 6F because the dsp is
; always decremented by 1 befo re the
data transfer of the PUSH instruction occurs
SWAP A, DSP ; Move Accumulator value into dsp
The three reset types are:
1. Power-On Reset (POR)
2. Watchdog Reset (WDR)
3. USB Reset
b7 b6 b5 b4 b3 b2 b1 b0
Reserved WDR USBR POR SUSPEND Reserved Reserved RUN
R/W R/W R/W R/W R/W
00010001
Figure 6-3. Status and Control Register (SCR – Address 0xFF)
The occurrence of a reset is rec orded in the St atus and Control
Register located at I/O address 0xFF (Figure 6-3). Reading
and writing this re gister are supported by the IORD and IOWR
instructions. Bit s 1, 2 , an d 7 are re served and must be written
as zeros during a write. During a read, reserved bi t positions
should be ignored. Bits 4, 5, and 6 are used to record the
occurrence of POR, USB, and WDR Reset respectively. The
firmware can interrogate these bits to determine the cause of
a reset. If a Watchdog Rese t occurs, firmware must clear the
WDR bit (bit 6) in the S tatu s and Control Regi ster to re-enabl e
the USB transmitter (please refer to the Watchdog Reset
section for further details). Bit 0, the “Run” control, is set to 1
at POR. Clearing this bit stops the microcontroller (firmware
normally should n ot cl ear thi s bit). Once this bit is set to LOW,
only a reset can set this bit HIGH.
The microcontroller resumes execution from ROM address
0x00 after a reset unless the Suspend bit (bit 3) of the Status
and Control Register is set. Setting the Suspend bit stops the
clock oscillator and the interrupt timers and powers down the
microcontroller. The detection of any USB activity, the occurrence of a GPIO Interrupt, or the occurrence of the Cext
Interrupt terminates the suspend condition.
6.3.1 Power-On Reset
Power-On Reset (POR) occurs every time the power to the
device is switche d on. Bit 4 o f the Status and Control Register
is set to record this event (the register contents are set to
00011001 by the POR). The USB Controller is placed in
Document #: 38-08026 Rev. *A Page 6 of 25
suspended mode at the end of POR to conserve power (the
clock oscillator, the timers, and the interrupt logic are turned
off in suspend mode). After POR, only a non-idle USB Bus
state terminates the suspend mode. The microcontroller then
begins execution from ROM address 0x00.
CY7C63001
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CY7C63101
7.168 to
8.192 ms
Last write to
Watchdog Timer
Register
6.3.2 Watchdog Reset (WDR)
The Watchdog Timer Reset (WDR) occurs when the Most
Significant Bit of the 4- bit W atchdog T imer Register transition s
from LOW to HIGH. Writing any value to the write-only
Watchdog Restart Register at 0x21 clears the timer (firmware
should periodically write to the Watchdog Restart Register in
the ‘main loop’ of fir mware). The W atchdog ti mer is clocked b y
a 1.024-ms clock from the fre e-runni ng tim er. If 8 clocks occur
between writes to the timer, a WDR occurs and bit 6 of the
Status and Control Register is set to record the event. A
Watchdog Timer Reset lasts for 8.192 ms, at which time the
microcontroller begins execution at ROM address 0x00. The
USB transmitter is disab led by a Watch dog Reset becau se the
USB Device Address Regist er is cleared (otherwise, the USB
Controller would respond to all address 0 transactions). The
transmitter remains disabled until the WDR bit (bit 6) in the
Status and Control Register is reset to 0 by firmware.
6.3.3 USB Bus Reset
The USB Controller recognizes a USB Reset when a Single
Ended Zero (SE0) condition persists for at least 8–16 µs (the
Reset may be reco gn ized f or an SE0 as s hort as 8 µs, but it is
always recognized for an SE0 longer than 16 µs). SE0 is the
condition in which both the D+ line and the D– line are LOW.
Bit 5 of the Status and Control Register is set to record this
event. If the USB reset happens while the device is
suspended, the suspend condition is cleared and the clock
oscillator is restarted. However, the microcontroller is not
released until the USB reset is removed.
No write to WDT
register, so WDR
goes HIGH
Figure 6-4. Watchdog Reset
6.4 Instant-on Feature (Suspend Mode)
The USB Controller can be placed in a low-power state by
setting the Suspend bit (bit 3) of the Status and Control
8.192 ms
Execution begins at
Reset Vector 0x00
register . Al l log ic bl ocks in the de vice are t urned of f e xcept the
USB receiver, the GPIO interrupt logic, and the Cext interrupt
logic. The clock oscil lat or and the fre e-running and Watchdog
timers are shut down.
The suspend mode is terminated when one of the following
three conditions occur:
1. USB activity
2. A GPIO interrupt
3. Cext interrupt
The clock oscillator, GPIO, and timers restart immediately
upon exiting suspend mode. The USB engine and microcontroller return to a fully functional state no more than 256 µs
later. Before servicing any interrupt requests, the microcontroller executes the instruction following the I/O write that
placed the device into suspend mode.
Both the GPIO interrupt and the Cext interrupt allow the USB
Controller to wake-up periodically and poll potentiometers,
optics, and othe r system com ponents while maint aining a very
low average power consumption. The Cext Interrupt is
preferred for lowest power consum ption.
For Cext to generate an “I nst ant-on” i nterrupt , the pin must b e
connected to groun d with an external c apacitor and co nnected
with an external resistor. A “0” is written to the Cext
to V
CC
register located at I/O address 0x22 to discharge the capacitor .
Then, a “1” is w ritten to d isabl e the open -drain output driv er. A
Schmitt trigger input circuit monitors the input and generates
a wake-up interrupt when the input voltage rises above the
input threshold. By changing the va lues of the external resistor
and capacitor, the user can fine tune th e c ha r ge rate of the R C timing circuit. The format of the Cext register is shown in
Figure 6-5. Reading the register returns the value of the Cext
pin. During a reset, the Cext pin is HIGH.
b7 b6 b5 b4 b3 b2 b1 b0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved CEXT
R/W
00000001
Figure 6-5. The Cext Register (Address 0x22)
Document #: 38-08026 Rev. *A Page 7 of 25
CY7C63001
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CY7C63101
6.5 On-Chip Timer
The USB Controller is equipped with a free-running timer
driven by a c lock one-sixth the resonator frequency. Bits 0
through 7 of the cou nter are readable fr om the read-only T imer
Register located at I/O address 0x23. The Timer Register is
cleared during a Power-On Reset and whenever Suspend
Figure 6-6. Timer Register (Address 0x23)
b7 b6 b5 b4 b3 b2 b1 b0
T.7 T.6 T.5 T.4 T.3 T.2 T.1 T.0
RRRRRRRR
00000000
mode is entered. Figure 6-6 illustrates the format of this
register and Figure 6-7 is its block diagram.
With a 6 MHz resonator, the timer resolution is 1 µs.
The timer generates two interrupts: the 128-µs interrupt and
the 1.024-ms interrupt.
1.024-ms interrupt
128-
m
s interrupt
9
8
7
6
5
4
3
2
1
0
Resonator Clock/6
8
To Timer Register
Figure 6-7. Timer Block Diagram
6.6 General Purpose I/O Ports
Interface with peripherals is conducted via as many as 16
GPIO signals. Th es e s ig nal s are d iv ide d into two ports: Port 0
and Port 1. Port 0 contains eig ht li nes (P0.0 –P0. 7) and P ort 1
contains up to eig ht lines (P1.0– P1.7). The numb er of external
I/O pins depends on the package type. Both ports can be
accessed by the IORD, IOWR, and IOWX instructions. The
b7 b6 b5 b4 b3 b2 b1 b0
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1
Figure 6-8. Port 0 Data Register (Address 0x00)
b7 b6 b5 b4 b3 b2 b1 b0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
R/W R/W R/W R/W R/W R/W R/W R/W
1 1 1 1 1 1 1 1
Figure 6-9. Port 1 Data Register (Address 0x01)
Port 0 data register is located at I/O address 0x00 while the
Port 1 data register is located at I/O address 0x01. The
contents of both registers are set HIGH during a reset. Refer
to Figures 6-8 and 6-9 for the formats of the data registers. In
addition to supporting general inp ut/output fu nctions, each I/O
line can trigger an in terrupt to th e microcon troller. Please refer
to the interrupt section for more details.
Document #: 38-08026 Rev. *A Page 8 of 25
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