Cypress CY7C604XX User Manual
enCoRe™ V Low Voltage Microcontroller
CY7C604XX
Features
System Bus
6/12/24 MHz Internal Main Oscillator
CPU Core
(M8C)
SROM Flash 32K
SYSTEM RESOURCES
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
Port 1 Port 0
Sleep and
Watchdog
Port 3 Por t 2
Prog. LDO
SRAM
2048 Bytes
Interrupt
Controller
enCoRe V
Low Voltage
CORE
3 16-Bit
Timers
Port 4
enCoRe V LV Block Diagram
■ Powerful Harvard Architecture Processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 1.71V to 3.6V operating voltage
❐ Temperature range: 0°C to 70°C
■ Flexible On-Chip Memory
❐ Up to 32K Flash program storage
• 50,000 Erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-System Serial Programming (ISSP)
■ Complete Development Tools
❐ Free development tool (PSoC Designer™)
❐ Full featured, in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128K trace memory
■ Precision, Programmable Clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator
❐ Internal low speed oscillator at 32 kHz for watchdog and
sleep.The frequency range is 19 to 50 kHz with a 32 kHz
typical value
■ Programmable Pin Configurations
❐ 25 mA sink current on all GPIO
❐ Pull Up, High Z, Open Drain, CMOS drive modes on all GPIO
❐ Configurable inputs on all GPIO
❐ Low dropout voltage regulator for Port 1 pins. Programmable
to output 3.0, 2.5, or 1.8V at the I/O pins
❐ Selectable, regulated digital I/O on Port 1
• Configurable input threshol d for Port 1
• 3.0V, 20 mA total Port 1 source current
• Hot-swappable
❐ 5 mA strong drive mode on Ports 0 and 1
■ Additional System Resources
❐ Configurable communication speeds
2
❐ I
C Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 mA
• Hardware address detection
❐ SPI master and SPI slave
• Configurable between 93.75 kHz and 12 MHz
❐ Three 16-bit timers
❐ 8-bit ADC used to monitor battery voltage or other signals -
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-12395 Rev *H Revised January 30, 2009
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CY7C604XX
Functional Overview
The enCoRe V LV family of devices are designed to replace
multiple traditional low voltage microcontroller system components with one, low cost single chip programmable component.
Communication peripherals (I2C/SPI), a fast CPU, Flash
program memory, SRAM dat a memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as illustrated in enCoRe
V LV Block Diagram, is comprised of two main areas: the CPU
core and the system resources. Depending on the enCoRe V LV
package, up to 36 general purpose IO (GPIO) are also included.
Enhancements over the Cypress’s legacy low voltage microcontrollers include faster CPU at lower voltage operation, lower
current consumption, twice the RAM and Flash, hot-swapable
I/Os, I2C hardware address recognition, new very low current
sleep mode, and new package options.
The enCoRe V LV Core
The enCoRe V LV Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.
System Resources provide additional capability, such as a
configurable I
interface and various system resets supported by the M8C.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. The following statements describe the merits of each
system resource:
■ 8-bit on-chip ADC shared betwe en System Performance
manager (used to calculate parameters based on temperature
for flash write operations) and the user.
■ The I
or 400 kHz communication over two wires. SPI communication
over three or four wires runs at speeds of 46.9 kHz to 3 MHz
(lower for a slower system clock).
2
■ In I
C slave mode, the hardware address recognition feature
reduces the already low power consumption by eliminating the
need for CPU intervention until a packet addressed to the target
device has been received.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■ The 5V maximum input, 1.8, 2.5, or 3V selectable output, low
dropout regulator (LDO) provides regulation for I/Os. A register
controlled bypass mode enables the user to disable the LDO.
■ Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V LV family of parts.
2
C slave and SPI master-slave communication
2
C slave and SPI master-slave module provides 50, 100,
Getting Started
The quickest way to understanding the enCoRe V silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the enCoRe V integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, reference the
PSoC Programmable System-on-Chip Technical Reference
Manual, for CY8C28xxx PSoC devices.
For up-to-date Ordering, Packaging, and Electrical Specification
information, reference the latest enCoRe V device data sheets
on the web at http://www.cypress.com.
Development Kits
Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Training
Free technical training (on demand, webinars, and workshops)
is available online at www.cypress.com/training. The training
covers a wide variety of topics and skill levels to assist you in
your designs.
CyPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various appli-
cation designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Document Number: 001-12395 Rev *H Page 2 of 30
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CY7C604XX
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the enCoRe and PSoC families.
PSoC Designer Software Subsystems
Chip-Level View
The chip-level view is a traditional integrated development
environment (IDE) based on PSoC Designer 4.4. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for the chosen application and connect them to each other and to the proper pins.
Then generate your project. This prepopulates your project with
APIs and libraries that you can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
enables changing configurations at run time.
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Designer.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share common code
editor, builder , and common debug, emulation, and programming
tools.
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the enCoRe and PSoC families of devices. The
products allow you to create complete C programs for the PSoC
family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program flash, read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural help and quick reference,
each functional subsystem has its own context-sensitive help.
This system also provides tutorials and links to FAQs and an
Online Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all enCoRe and PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (24 MHz) operation.
Document Number: 001-12395 Rev *H Page 3 of 30
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CY7C604XX
Designing with PSoC Designer
The development process for the enCoRe V device differs from
that of a traditional fixed function microprocessor. Powerful
PSoC Designer tools get the core of your design up and running
in minutes instead of hours.
The development process can be summarized in the following
four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
The chip-level views provide a library of pre-built, pre-tested
hardware peripheral components. These components are called
“user modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed-signal varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application.
The chip-level user modules are documented in data sheets that
are viewed directly in PSoC Designer. These data sheets explain
the internal operation of the component and provide performance specifications. Each data sheet describes the use of each
user module parameter and contains other information you may
need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions. In the chip-level view, you perform the
selection, configuration, and routing so that you have complete
control over the use of all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the In-Circuit
Emulator (ICE) where it runs at full speed. PSoC Designer
debugging capabilities rival those of systems costing many times
more. In addition to traditional single-step, run-to-breakpoint and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events
that include monitoring address and data bus values, memory
locations and external signals.
Document Number: 001-12395 Rev *H Page 4 of 30
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CY7C604XX
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Acronym Description
API application programming interface
CPU central processing unit
GPIO general purpose IO
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
LSb least significant bit
LVD low voltage detect
MSb most significant bit
POR pow er on rese t
PPOR precision power on reset
PSoC® Programmable System-on-Chip™
SLIMO slow IMO
SRAM static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 14 lists all the abbreviations used to
measure the enCoRe V LV devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
Document Number: 001-12395 Rev *H Page 5 of 30
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CY7C604XX
Pin Configuration
16-Pin Part Pinout
Figure 1. CY7C60413 16-Pin enCoRe V LV Device
Table 1. 16-Pin Part Pinout (QFN)
Pin No. Type Name Description
1 I/O P2[5] Digital I/O, Crystal Out (Xout)
2 I/O P2[3] Digital I/O, Crystal In (Xin)
3 IOHR P1[7] Digital I/O, I2C SCL, SPI SS
4 IOHR P1[5] Digital I/O, I2C SDA, SPI MISO
5 IOHR P1[3] Digital I/O, SPI CLK
6 IOHR P1[1] Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
7 Power Vss Ground Pin
8 IOHR P1[0] Digital I/O, ISSP DATA, I2C SDA, SPI CLK
9 IOHR P1[2] Digital I/O
10 IOHR P1[4] Digital I/O, optional external clock input (EXTCLK)
11 Input XRES Active high external reset with internal pull down
12 IOHR P0[4] Digital I/O
13 Power Vdd Power Pin
14 IOHR P0[7] Digital I/O
15 IOHR P0[3] Digital I/O
16 IOHR P0[1] Digital I/O
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12395 Rev *H Page 6 of 30
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CY7C604XX
32-Pin Part Pinout
Notes
1. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.
2. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR)
P0 [1 ]
P2[7]
P2[5]
P2[3]
P2[1]
P3[3]
QFN
(Top View)
9
10111213141516
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32313029282726
25
Vss
P0[3]
P0[7]
Vdd
P0[6]
P0[4]
P0[2]
P3[1]
P1[7 ]
P0[0]
P2[6]
P3[0]
XRES
P1[5]
P1[3]
P1[1]
Vss
P1[0]
P1[2]
P1[4]
P1[6]
P2[4]
P2[2]
P2[0]
P3[2]
P0[5]
Figure 2. CY7C60445 32-Pin enCoRe V LV Device
Table 2. 32-Pin Part Pinout (QFN)
Pin No. Type Name Description
1 IOH P0[1] Digital I/O
2 I/O P2[7] Digital I/O
3 I/O P2[5] Digital I/O, Crystal Out (Xout)
4 I/O P2[3] Digital I/O, Crystal In (Xin)
5 I/O P2[1] Digital I/O
6 I/O P3[3] Digital I/O
7 I/O P3[1] Digital I/O
8 IOHR P1[7] Digital I/O, I2C SCL, SPI SS
9 IOHR P1[5] Digital I/O, I2C SDA, SPI MISO
10 IOHR P1[3] Digital I/O, SPI CLK
11 IOHR P1[1]
12 Power Vss Ground connection
13 IOHR P1[0]
14 IOHR P1[2] Digital I/O
15 IOHR P1[4] Digital I/O, optional external clock input (EXTCLK)
16 IOHR P1[6] Digital I/O
(3, 4)
(3, 4)
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Digital I/O, ISSP DATA, I2C SDA, SPI CLK
Document Number: 001-12395 Rev *H Page 7 of 30
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Table 2. 32-Pin Part Pinout (QFN) (continued)
Notes
3. During power up or reset event, device P1[0] and P1[1] may disturb the I2C bus. Use alternate pins if issues are encountered.
4. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR)
Pin No. Type Name Description
17 Reset Input XRES Active high external reset with internal pull down
18 I/O P3[0] Digital I/O
19 I/O P3[2] Digital I/O
20 I/O P2[0] Digital I/O
21 I/O P2[2] Digital I/O
22 I/O P2[4] Digital I/O
23 I/O P2[6] Digital I/O
24 IOH P0[0] Digital I/O
25 IOH P0[2] Digital I/O
26 IOH P0[4] Digital I/O
27 IOH P0[6] Digital I/O
28 Power Vdd Supply voltage
29 IOH P0[7] Digital I/O
30 IOH P0[5] Digital I/O
31 IOH P0[3] Digital I/O
32 Power Vss Ground connection
CP Power Vss Center pad must be connected to ground
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12395 Rev *H Page 8 of 30
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CY7C604XX
48-Pin Part Pinout
QFN
(Top V ie w )
P0[1]
Vss
P0[3]
P0[5]
P0[7]
Vdd
P0[6]
10
11
12
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
35
34
33
32
31
30
29
28
27
26
25
36
4847464544
43424140393837
P0[2]
P0[0]
P2[6]
P2[4]
P2[2]
P2[0]
P3[2]
P3[0]
XRES
P1[6]
P0[4]
1
2
3
4
5
6
7
8
9
131415161718192021
22
23
24
NC
NC
P1[3]
P1[1]
Vss
NC
NC
Vdd
P1[0]
P1[2]
P1[4]
NC
P3[1]
P1[7]
P1[5]
P3[4]
P3[6]
P4[0]
P4[2]
NC
NC
Figure 3. CY7C60455/CY7C60456 48-Pin enCoRe V LV Device
Table 3. 48-Pin Part Pinout (QFN)
Pin No. Type Name Description
1NCNC No connection
2 I/O P2[7] Digital I/O
3 I/O P2[5] Digital I/O, Crystal Out (Xout)
4 I/O P2[3] Digital I/O, Crystal In (Xin)
5 I/O P2[1] Digital I/O
6 I/O P4[3] Digital I/O
7 I/O P4[1] Digital I/O
8 I/O P3[7] Digital I/O
9 I/O P3[5] Digital I/O
10 I/O P3[3] Digital I/O
11 I/O P3[1] Digital I/O
12 IOHR P1[7] Digital I/O, I2C SCL, SPI SS
13 IOHR P1[5] Digital I/O, I2C SDA, SPI MISO
14 NC NC No connection
15 NC NC No connection
16 IOHR P1[3] Digital I/O, SPI CLK
17 IOHR P1[1]
(3, 4)
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Document Number: 001-12395 Rev *H Page 9 of 30
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