CYPRESS CY7C603xx User Manual

CY7C603xx

enCoRe™ III Low Voltage

Features

• Powerful Harvard Architecture Processor
— M8C Processor Speeds to 12 MHz
— Low Po wer at High Speed
— 2.4V to 3.6V Operating Voltage
— Operating Voltages Down to 1.0V Using On-Chip Switch

Mode Pump (SMP)

— Commercial Temperature Range: 0°C to +70°C

• Configurable Peripherals
— 8-bit Timers/Counters/PWM
— Full Duplex Master or Slave SPI
—10-bit ADC
— 8-bit Successive Approximation ADC
—Comparator

• Flexible On-Chip Memory
— 8K Flash Program Storage 50,000 Erase/Write Cycles
— 512 Bytes SRAM Data Storage
— In-System Serial Programming (ISSP)
— Partial Flash Updates
— Flexible Protection Modes
— EEPROM Emulation in Flash

• Complete Development Tools
— Free Development Software (PSoC Designer™)
— Full-Featured, In-Circuit Emulator and Programmer
— Complex Breakpoint Structure
— 128K Trace Memory

• Precision, Programmable Clocking
— Internal ±2.5% 24-/48-MHz Oscil lator
— Internal Oscillator for Watchdog and Sleep

• Programmable Pin Configurations
— 10 mA Drive on All GPIO
— Pull-up, Pull-down, High Z, Strong, or Open Drain Drive

Modes on All GPIO
— Up to 8 Analog Inputs on GPIO
— Configura ble Interrupt on All GPIO

• Versatile Analog Mux
— Commo n Internal Analog Bus
— Simultaneous Connection of IO Combinations

• Additional System Resources

2

—I

C Master, Slave and Multi-Master to 400 kHz
— Watchdog and Sleep Timers
— User-Configurable Low Voltage Detection
— Integrated Supervisory Circuit
— On-Chip Pre c ision Voltage Reference

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-16018 Rev. *D Revised October 10, 2006

Figure 1. enCoRe III Low Voltage Block Diagram

CY7C603xx

System Bus

Global Digital

Interconnect

SRAM

512 Bytes

Interrupt

Controller

Clock Sources (Includes IMO and ILO)

DIGITAL SYSTEM

Digital

PSoC

Block

Array

Digital
Clocks

I2C

Port 3 Port 2

enCoRe II LV Core

POR and LVD

System Resets

SYSTEM RESOURCES

Port 1 Port 0

Global Analog Interconnect

SROM Flash 8K

CPU Core

(M8C)

ANALOG SYSTEM

Analog

PSoC
Block
Array

Switch

Mode

Pump

Sleep and

Watchdog

Internal
Voltage

Ref.

Analog

Ref.

Analog

Mux

Applications

•Wireless mice

• Wireless gamepads

• Wireless Presenter tools

• Wireless keypads

®

•PlayStation

2 wired gamepads

• PlayStation 2 bridges for wireless gamepads

• Applications requiring a cost effective low voltage 8-bit
microcontroller.

enCoRe III Low Voltage Functional Overview

The enCoRe III Low Voltage (enCoRe III LV) CY7C603xx
device is based on the flexible PSoC
set of peripherals is supported that can be configured as
required to match the needs of each application. Additional ly,
a fast CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts.

This architecture allows the user to create customized
peripheral configurations that match the requirements of each
individual application. Additionally, a fast CPU, Flash program
memory, SRAM data memory, and configurable IO are
included in both a 28-pin SSOP and 32-pin QFN packages.

®

architecture. A simple

enCoRe III LV architecture, as illustrated in Figure 1, is
composed of four main areas: the enCoRe III LV Core, the
System Resources, Digital System, Analog System and
System Resources. Configurable global bus resources allow
all the device resources to be combined into a complete
custom system. Each enCoRe III LV device support s a limited
set of digital and analog peripherals. Depending on the
package, up to 28 general purpose IOs (GPIOs) are also
included. The GPIOs provide access to the global digital and
analog interconnects.

enCoRe III LV Core

The enCoRe III LV core is a powerful engine that supports a
rich feature set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low-speed oscil­lator).

The CPU core, called the M8C, is a powerful p rocessor with
speeds up to 12 MHz. The M8C is a four MIPS 8-bit Harvard
architecture microprocessor. The core includes a CPU,
memory, clocks, and configurable GPIO (General Purpose
IO).

System Resources provide additional capability, such as
digital clocks to increase flexibility, I2C functionality for imple­menting an I2C master, slave, MultiMaster , an internal voltage
reference that provides an absolute value of 1.3V to a number
of subsystems, a switch mode pump (SMP) that generates

Document #: 38-16018 Rev. *D Page 2 of 29

CY7C603xx

normal operating voltages off a single battery cell, and various
system resets supported by the M8C.

The Digital System

The Digital System is composed of 4 digital enCoRe III LV
blocks. Each block is an 8-bit resource. Digital peripheral
configurations include those listed below.

• PWM usable as Timer/Counter

• SPI master and slave

• I2C slave and multi-master

•CMP

•ADC10

• SARADC

Figure 2. Digital System Block Diagram

Port 3

Port 2

D

c

o

l

C

l

a

t

i

g

i

o

r

F

s

k

To System Bus

r

o

m

C

e

Port 1

Port 0

To Analog

System

DIGITAL SYSTEM

Digital enCoRe II LV Block Array

Row 0

Configuration

Row Output

4

Analog blocks are provided in columns of two, which includes
one CT (Continuous Time - ACE00 or ACE01) and one SC
(Switched Capacitor - ASE10 or ASE11) blocks.

Figure 3. Analog System Block Diagram

Array Input

Configuration

ACI0[1:0] ACI1[1:0]

All IO

X

X
X

X

X

ACOL1MUX

Analog Mux Bus

Array

ACE00 ACE01

ASE10 ASE11

DBB00 DBB01 DCB02 DCB03

Row Input

8

Configuration

GIE[7:0]
GIO[7:0]

Global Digital

Interconnect

4

8

GOE[7:0]
GOO[7:0]

The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing
logic operations. This configurability frees your designs from
the constraints of a fixed peripheral controller.

The Analog System

The Analog System is composed of two configurable blocks.
Analog peripherals are very flexible and can be customized to
support specific application requirements. Some of the
common analog functions for this device (most available as
user modules) are listed below.

• Analog-to-digital converters (single with 8-bit resolution)

• Pin-to-pin comparators

• Single-ended comparators with absolute (1.3V) reference

• 1.3V reference (as a System Resource)

The Analog Multiplexer System

88

The Analog Mux Bus can connect to every GPIO pin. Pins can
be connected to the bus individually or in any combination.
The bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional
8:1 analog input multiplexer provides a second path to bring
Port 0 pins to the analog array.

Additional System Resources

System Resources, some of which have been previously
listed, provide additional capability useful to complete
systems. Additional resources include a switch mode pump,
low voltage detection, and power on reset. Brief statements
describing the merits of each system resource are presented
below.

• Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be
routed to both the digital and analog systems. Additional
clocks can be generated using digital blocks as clock
dividers.

• The I2C module provides 100- and 400-kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.

• Low Voltage Detection (L VD) interrupts can signal the appli­cation of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.

Document #: 38-16018 Rev. *D Page 3 of 29

CY7C603xx

• An internal 1.3 voltage reference provides an absolute
reference for the analog system.

• An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing
a low-cost boost converter.

• Versatile analog multiplexer system.

enCoRe III LV Device Characteristics

enCoRe III L V devices have four digital b locks and four analog
blocks. The following table lists the resources available for
specific enCoRe III LV devices.

Part

Number

CY7C60323

-PVXC
CY7C60323

-LFXC
CY7C60333

-LFXC

Rows

Digital IODigital

24 1 4 24 0 2 4 512

28 1 4

28 1 4

Inputs

Digital

Blocks

Analog

Analog

Analog

Outputs

Columns

28 0 2 4 512

26 0 2 4 512

Analog

Blocks

Bytes

Bytes

Bytes

SRAM

Size

Flash

8K

8K

8K

Getting Started

The quickest path to understanding the enCoRe III LV silicon
is by reading this data sheet and using the PSoC Designer
Integrated Development Environment (IDE). This data sheet
is an overview of the enCoRe III LV and presents specific pin,
register, and electrical specifications. enCoRe III LV is based
on the architecture of the CY8C21x34. For in-depth infor­mation, along with detailed programming information, refer to
the PSoC Mixed-Signal Array Technical Reference Manual,
which can be found on http://www.cypress.com/psoc.

For up-to-date Ordering, Packaging, and Electrical Specifi­cation information, refer to the latest device data sheets on the
web at http://www.cypress.com.

integrated debugger with In-Circuit Emulator, in-system
programming support, and the CYASM macro assembler for
the CPUs.

PSoC Designer also supports a high-level C language
compiler developed specifically for the devices in the family.

Figure 4. PSoC Designer Subsystems

PSoC

TM

Graphical Designer

Interface

Sensitive

Designer

Results

Size

Importable

Des ign

Databas e

Device

Databas e

Application

Databas e

Project

Databas e

User

Modules

Library

Emulation

Pod

Commands

TM

PSoC

Designer

Core

Engine

In-Circuit

Emulator

Configuration

M a nufacturing

Inf ormation

Device

Programmer

Context

Help

PSoC
Sheet

File

Development Kits

PSoC Designer Software Subsystems

Development Kits are available from the following distributors:
Digi-Key, A vnet, Arrow , and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories
for enCoRe III LV development. Go to the Cypress Online
Store web site at http://www.cypress.com, click the Online
Store shopping cart icon at the bottom of the web page, and
click USB (Universal Serial Bus) to view a current list of
available items.

Development Tools

Device Editor

The device editor subsystem allows the user to select different
on-board analog and digital components called user modules
using the blocks. Examples of user modules are ADCs,
PWMs, and SPI.

PSoC Designer sets up power-on initialization tables for
selected block configurations and creates source code for an
application framework. The framework contains software to

operate the selected components and, if the project uses more
PSoC Designer is a Microsoft® Windows®-based, integrated
development environment for the enCoRe III LV. The PSoC
Designer IDE and application runs on Windows NT 4.0,
Windows 2000, Windows Millennium (Me), or Windows XP.
(Refer to the PSoC Designer Functional Flow diagram below.)

PSoC Designer helps the customer to select an operating
configuration, write application code that uses the
enCoRe III LV, and debug the application. This system

than one operating configuration, contains routines to switch

between different sets of block configurations at run time.

PSoC Designer can print out a configuration sheet for a given

project configuration for use during application p rogramming

in conjunction with the Device Data Sheet. Once the

framework is generated, the user can add application-specific

code to flesh out the framework. It is also possible to change

the selected components and regenerate the framework.
provides design database management by project, an

Document #: 38-16018 Rev. *D Page 4 of 29

CY7C603xx

Application Editor

In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.

Assembler. The macro assembler allows the assembly code
to be merged seamlessly with C code. The link libraries
automatically use absolute addressing or can be compiled in
relative mode and linked with other software modules to get
absolute addressing.

C Language Compiler. A C language compiler is available
that supports the enCoRe III LV family of devices. Even if you
have never worked in the C language before, the product
quickly allows you to create complete C programs.

The embedded, optimizing C compiler provides all the
features of C tailored to the enCoRe III LV architecture. It
comes complete with embedded libraries providing port and
bus operations, standard keypad and display support, and
extended math functionality.

Debugger

The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the progra m
in a physical system while providing an internal view of the
device. Debugger commands allow the designer to read the
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break­points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.

Online Help System

The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference,
each functional subsystem has its own context-sensitive help.
This system also provides tutorials and links to FAQs and an
Online Support Forum to aid the designer in getting started.

Hardware Tools

In-Circuit Emulator

A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.

The emulator consists of a base unit that connects to the PC
by way of a USB port. The base unit is universal and will
operate with enCoRe III LV, enCoRe III, and all PSoC devices.
Emulation pods for each device family are available
separately. The emulation pod takes the place of the
enCoRe III LV device in the target board and performs full
speed (12 MHz) operation.

Designing with User Modules

The development process for the enCoRe III LV device differs

from that of a traditional fixed-function microprocessor. The

configurable analog and digital hardware blocks provide a

unique flexibility that pays dividends in managing specification

change during development and by lowering inventory costs.

These configurable resources have the ability to implement a

wide variety of user-selectable functions. Each block has

several registers that determine its function and connectivity

to other blocks, multiplexers, buses and to the IO pins.

Iterative development cycles permit you to adapt the hardware

as well as the software. This substantially lowers the risk of

having to select a different part to meet the final design require-

ments.

To speed the development process, the PSoC Designer

Integrated Development Environment (IDE) provides a library

of prebuilt, pretested hardware peripheral functions, called

“User Modules.” User Modules make selecting and imple-

menting peripheral devices simple, and come in analog,

digital, and mixed signal varieties. The standard User Module

library contains seven common peripherals such as ADCs,

SPI, I2C and PWMs to configure the enCoRe III LV periph-

erals.

Each user module establishes the basic register settings that

implement the selected function. It also provides parameters

that allow you to tailor its precise configuration to your

particular application. For example, a Pulse Width Modulator

User Module configures a digital enCoRe III LV block for 8 bits

of resolution. The user module parameters permit you to

establish the pulse width and duty cycle. User modules also

provide tested software to cut your development time. The

user module application programming interface (API) provides

high-level functions to control and respond to hardware events

at run time. The API also provides optional interrupt service

routines that you can adapt as needed.

The API functions are documented in user module data sheets

that are viewed directly in the PSoC Designer IDE. These

data sheets explain the internal operation of the user module

and provide performance specifications. Each data sheet

describes the use of each user module parameter and

documents the setting of each register controlled by the user

module.

The development process starts when you open a new project

and bring up the Device Editor, a graphical user interface

(GUI) for configuring the hardware. Y ou pick the user modules

you need for your project and map them onto the

enCoRe III LV blocks with point-and-click simplicity. Next, you

build signal chains by interconnecting user modules to each

other and the IO pins. At this stage, you also configure the

clock source connections and enter parameter values directly

or by selecting values from drop-down menus. When you are

ready to test the hardware configuration or move on to devel-

oping code for the project, you perform the “Generate Appli-

cation” step. This causes PSoC Designer to generate source

code that automatically configures the device to your specifi -

cation and provides the high-level user module API functions.

Document #: 38-16018 Rev. *D Page 5 of 29

CY7C603xx

Figure 5. User Module and Source Code Development

Flows

Device Editor

User

Module

Selection

Placement

and

Parameter

-ization

Source

Code

Generator

Generate
Application

Application Editor

Project

Manager

Source

Code

Editor

Build

Manager

Build
All

Debugger

Interface

to ICE

Storage

Inspector

Event &

Breakpoint

Manager

The next step is to write your main program, and any subrou­tines using PSoC Designer’s Application Editor subsystem.
The Application Editor includes a Project Manager that allows
you to open the project source code files (including all
generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities
include simple string searches and recursive “grep-style”
patterns. A single mouse click invokes the Build Manager. It
employs a professional-strength “makefile” system to
automatically analyze all file dependencies and run the
compiler and assembler as necessary. Project-level options
control optimization strategies used by the compiler and linker.
Syntax errors are displayed in a console window. Double
clicking the error message takes you directly to the offending
line of source code. When all is correct, the linker builds a HEX
file image suitable for programming.

The last step in the development process takes place inside
the PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE)
where it runs at full speed. Debugger capabilities rival those of
systems costing many times more. In addition to traditional
single-step, run-to-breakpoint and watch-variable features,
the Debugger provides a large trace buffer and allows you
define complex breakpoint events that include monitoring
address and data bus values, memory locations and external
signals.

Document Conventions

Acronyms Used

Acronym Description

AC alternating current
ADC analog-to-digital converter
API application programming interface
CPU central processing unit
CT continuous time
ECO external crystal oscillator
EEPROM el ectrically erasable programmable read-only

memory
FSR full scale range
GPIO general purpose IO
GUI graphical user interface
HBM human body model
ICE in-circuit emulator
ILO internal low speed oscillator
IMO internal main oscillator
IO input/output
IPOR imprecise power on reset
LSb least-significant bit
LVD low voltage detect
MSb most-significant bit
PC program counter
PLL phase-locked loop
POR power on reset

PPOR precision power on reset
PSoC Programmable System-on-Chip™
PWM pulse width modulator
SC switched capacitor
SRAM static random access memory

Units of Measure

A units of measure table is located in the Electrical Specifica­tions section. Table 5 on page 13 lists all the abbreviations
used to measure the enCoRe III LV devices.

Numeric Naming

Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’
or ‘3Ah’). Hexidecimal numbers may also be represented by a
‘0x’ prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’ or ‘b’ are decimal.

Document #: 38-16018 Rev. *D Page 6 of 29

CY7C603xx

Packages/Pinouts

The enCoRe III LV device is available in 28-pin SSOP and 32-pin QFN packages, which are listed and illustrated in the following
tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd,
SMP, and XRES are not capable of Digital IO.

Table 1. 28-Pin Part Pinout (SSOP)

Pin
No.

Type

Digital Analog

Name Description

1 IO I, M P0[7] Analog column mux input.
2 IO I, M P0[5] Analog column mux input and column output.
3 IO I, M P0[3] Analog column mux input and column output,

integrating input.
4 IO I, M P0[1] Analog column mux input, integrating input.
5 IO M P2[7]
6 IO M P2[5]
7 IO I, M P2[3] Direct switched capacitor block input.
8 IO I, M P2[1] Direct switched capacitor block input.
9 Power Vss Ground connection.

10 IO M P1[7] I2C Serial Clock (SCL).
11 IO M P1[5] I2C Serial Data (SDA).
12 IO M P1[3]
13 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
14 Power Vss Ground connection.
15 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA.
16 IO M P1[2]
17 IO M P1[4] Optional External Clock Input (EXTCLK).
18 IO M P1[6]
19 Input XRES Active HIGH external reset with internal pull

down.

20 IO I, M P2[0] Direct switched capacitor block input.
21 IO I, M P2[2] Direct switched capacitor block input.
22 IO M P2[4]
23 IO M P2[6]
24 IO I, M P0[0] Analog column mux input.
25 IO I, M P0[2] Analog column mux input.
26 IO I, M P0[4] Analog column mux input
27 IO I, M P0[6] Analog column mux input.
28 Power Vdd Supply voltage.

LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.

M, I2C S C L, P 1 [7]
M, I2C S D A , P1 [5]

M, I2C S C L, P 1 [1]

CY7C60323-PVXC Device

A, I, M, P0 [7]
A, I, M, P0 [5]
A, I, M, P0 [3]
A, I, M, P0 [1]

M, P2[7]
M, P2[5]

M, P2[3]

M, P2[1]

M, P1[3]

Vss

Vss

10
11
12
13
14

1
2
3
4
5
6
7
8
9

SSOP

Vdd

28

P0[6], A , I, M

27

P0[4], A , I, M

26

P0[2], A , I, M

25

P0[0], A , I, M

24

P2[6], M

23

P2[4], M

22

P2[2], M

21

P2[0], M

20

XRES

19

P1[6], M

18

P1[4], E X TCLK, M

17

P1[2], M

16

P1[0], I2C SDA, M

15

Document #: 38-16018 Rev. *D Page 7 of 29

32-Pin Part Pinout

Ta ble 2. 32-Pin Part Pinout (QFN*)

Pin
No.

1 IO I, M P0[1] Analog column mux input, integrating input.
2 IO M P2[7]
3 IO M P2[5]
4 IO M P2[3]
5 IO M P2[1]
6 IO M P3[3] In CY7C60323 part.
6 Power SMP Switch Mode Pump (SMP) connection to re-

7 IO M P3[1] In CY7C60323 part.
7 Power Vss Ground connection in CY7C60333 part.
8 IO M P1[7] I2C Serial Clock (SCL).

9 IO M P1[5] I2C Serial Data (SDA).
10 IO M P1[3]
11 IO M P1[1] I2C Serial Clock (SCL), ISSP-SCLK.
12 Power Vss Ground connection.
13 IO M P1[0] I2C Serial Data (SDA), ISSP-SDATA.

14 IO M P1[2]
15 IO M P1[4] Optional External Clock Input (EXTCLK).
16 IO M P1[6]
17 Input XRES Active HIGH external reset with internal pull

18 IO M P3[0]
19 IO M P3[2]
20 IO M P2[0]
21 IO M P2[2]
22 IO M P2[4]
23 IO M P2[6]
24 IO I, M P0[0] A nalog column mux input.
25 IO I, M P0[2] A nalog column mux input.
26 IO I, M P0[4] A nalog column mux input.
27 IO I, M P0[6] A nalog column mux input.
28 Power Vdd Supply voltage.
29 IO I, M P0[7] A nalog column mux input.
30 IO I, M P0[5] A nalog column mux input.
31 IO I, M P0[3] Analog column mux input, integrating input.
32 Power Vss Ground connection.

Type

Digital Analog

Name Description

quired external components in CY7C60333
part.

down.

A, I, M, P0[1]

M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, P3[1]

M, I2C SCL, P1[7]

A, I, M, P0[1]

M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]

SMP

Vss

M, I2C SCL, P1[7]

CY7C603xx

CY7C60323-LFXC Device

P0[5], A, I, M

Vss

P0[3], A, I, M

P0[7], A, I, M

Vdd

P0[6], A, I, M

P0[4], A, I, M

P0[2], A, I, M

131415

M, P1[2]

M, I2C SDA, P1[0]

M, EXTCLK, P1[4 ]

Vdd

P0[6], A , I, M

131415

M, P1[2]

M, I2C SDA, P1[0]

25

24
23
22
21
20
19
18
17

16

M, P1[6]

P0[4], A , I, M

P0[2], A , I, M

25

24
23
22
21
20
19
18
17

16

P1[4]

M, P1[6]

M, EXTCLK,

32313029282726

1
2
3
4
5
6
7
8

(Top View)

9

101112

M, P1[3]

M, I2C SDA, P1[5]

QFN

Vss

M, I2C SCL, P1[1]

CY7C60333-LFXC Device

P0[5], A , I, M

Vss

P0[3], A , I, M

P0[7], A , I, M

32313029282726

1
2
3
4
5
6
7
8

(Top View)

9

101112

M, P1[3]

M, I2C SDA, P1[5]

QFN

Vss

M, I2C S CL, P1[ 1 ]

P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES

P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES

LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The QFN package has a center pad that must be connected to ground (Vss).

Document #: 38-16018 Rev. *D Page 8 of 29

CY7C603xx

Register Reference

This section lists the registers of the enCoRe III LV device. For
detailed register information, reference the PSoC
Mixed-Signal Array Technical Reference Manual.

Register Conventions

The register conventions specific to this section are listed in
the following table.

Register Mapping Tables

The enCoRe III LV device has a total register address space
of 512 bytes. The register space is referred to as IO space and
is divided into two banks. The XOI bit in the Flag register
(CPU_F) determines which bank the user is currently in. When
the XOI bit is set the user is in Bank 1.

Note: In the following register mapping tables, blank fields are
Reserved and should not be accessed.

Convention Description

R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific

Table 3. Register Map 0 Table: User Space

Name

PRT0DR 00 RW 40 ASE10CR0 80 RW C0
PRT0IE 01 RW 41 81 C1
PRT0GS 02 RW 42 82 C2
PRT0DM2 03 RW 43 83 C3
PRT1DR 04 RW 44 ASE11CR0 84 RW C4
PRT1IE 05 RW 45 85 C5
PRT1GS 06 RW 46 86 C6
PRT1DM2 07 RW 47 87 C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
PRT3DR 0C RW 4C 8C CC
PRT3IE 0D RW 4D 8D CD
PRT3GS 0E RW 4E 8E CE
PRT3DM2 0F RW 4F 8F CF

Blank fields are Reserved and should not be accessed. # Access is bit specific.

Addr

(0,Hex) Access Name

10 50 90 CUR_PP D0 RW
11 51 91 STK_PP D1 RW
12 52 92 D2
13 53 93 IDX_PP D3 RW
14 54 94 MVR_PP D4 RW
15 55 95 MVW_PP D5 RW
16 56 96 I2C_CFG D6 RW
17 57 97 I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW

Addr

(0,Hex) Access Name

Addr

(0,Hex) Access Name

Addr

(0,Hex) Access

Document #: 38-16018 Rev. *D Page 9 of 29