CYPRESS CY7C43644AV, CY7C43664AV, CY7C43684AV User Manual
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CY7C43644AV
PRELIMINARY
3.3V 1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO w/ Bus Matching
Features
• 3.3V high-speed, l ow-power, bidirectional, First-I n FirstOut (FIFO) memori es w/ bus matching capabil it ies
• 1Kx36x2 (CY7C43644 AV)
• 4Kx36x2 (CY7C43664 AV)
• 16Kx36x2 (CY7C43684AV)
• 0.25-micr on CMOS for optimum speed/powe r
• High-speed 133- MHz operat ion (7.5- ns read /write c ycle
times)
• Low power
= 60 mA
—I
CC
= 12 mA
—I
SB
Logic Block Diagram
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
Por t A
Control
Logic
FIFO1,
Mail1
Reset
Logic
Input
Register
Write
Pointer
Mail1
Register
1K/4K/16K
Dual Ported
Memory
Status
Flag Logic
x36
CY7C43664AV/CY7C43684AV
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel and Serial Programmable Almost Full and
Almost Empty flags
• Ret ra n smit func tion
• Standard or FW FT mod e user sel ectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-Pin TQFP packaging
• 3.3V pin-compatible, feature enhanced, density upgrade to IDT723624/34/44 family
• Easily expandable in width and depth
Port B
Control
Logic
Read
Pointer
Bus Matching
Output
Register
MBF1
CLKB
CSB
W/RB
ENB
MBB
RTI
BE
BM
SIZE
EFB/ORB
AEB
SPM
FS0/SD
FS1/SEN
A
0–35
EFA/ORA
AEA
36
MBF2
Cypress Semiconductor Corporation
Programmable
Flag Offset
Registers
Output
Register
Write
Pointer
Status
Flag Logic
1K/4K/16K
x36
Dual Ported
Memory
Mail2
Register
Timing
Mode
Read
Pointer
Input
36
FIFO1,
Mail1
Reset
Logic
Register
B
BE/FWFT
FFB/IRB
AFB
MRS2
PRS2
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
August 30, 1999
0–35
CY7C43644AV
Pin Configuration
W/RA
ENA
CLKA
GND
A
A
A
A
V
A
A
GND
A
A
A
A
A
A
A
BE/FWFT
GND
A
V
A
A
A
A
GND
A
A
A
A
A
RT2
A
GND
A
A
PRELIMINARY
CY7C43664AV/CY7C43684AV
TQFP
Top View
/RB
GND
FFB/IRB
MBF2
AEA
AFA
VCCPRS1
EFA/ORA
FFA/IRA
CSA
128
127
126
125
124
123
1
2
3
122
121
MBA
120
MRS1
119
FS0/SD
118
GND
117
GND
116
FS1/SEN
115
MRS2
114
MBB
113
112
VCCMBF1
111
AEB
110
AFB
109
4
5
35
6
34
33
7
32
8
9
CC
10
31
11
30
12
29
13
14
28
15
27
26
16
25
17
24
18
19
23
20
21
22
22
CC
23
21
24
20
25
19
26
18
27
28
17
29
16
30
15
31
14
32
13
33
34
12
35
36
11
37
10
38
CY7C43644AV
CY7C43664AV
CY7C43684AV
39404142434445464748495051525354555657585960616263
5
6A7A8A9
A
GND
2
A
A3A4A
CC
V
SPM
0
0A1
A
B
GND
5B4B3B2B1
B
EFB/ORB
108
CSB
ENB
W
107
106
105
104
103
102
CLKB
101
PRS2
V
100
CC
99
B
35
98
B
34
97
B
33
96
B
32
GND
95
GND
94
93
B
31
92
B
30
91
B
29
90
B
28
89
B
27
88
B
26
RT1
87
86
B
25
B
85
24
BM
84
83
GND
82
B
23
81
B
22
80
B
21
B
79
20
B
78
19
77
B
18
76
GND
B
75
17
74
B
16
SIZE
73
V
72
CC
B
71
15
B
14
70
B
69
13
B
68
12
GND
67
B
66
11
B
65
10
64
7
6
B
GND
B9B8B
CC
V
2
CY7C43644AV
PRELIMINARY
Functional Description
The CY7C436X4AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports cloc k freque ncies up to 133 M Hz an d h as read
access times as fast as 6 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be input and
output in 36-bit, 18-bit, or 9-bit fo rmats wit h a choice of Big or
Little Endian configurations.
The CY7C436X4AV is a synchronous (clocked) FIFO, meaning each port emplo ys a sync hron ous int erf ace . All data t ransfers th rough a port are gate d to the LO W - to-HI GH trans iti on of
a port clock by enable signals. The clocks for each port are
independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a
simple bidi rectional i nterfac e between microproces sors and/or
buses with synchronous control.
Communication b etw een each port ma y b ypas s the FIF Os via
two mailbox registers. The mailbox registers’ width matches
the selected P ort B bus width. Each mailbo x register has a f lag
(MBF1
and MBF2) to signal when new mail has been stored.
T w o kinds of reset are a vailab le on th e CY7C436X4A V : Master
Reset and Partial Reset . Master Rese t init ializ es t he read and
write pointers to the fi rst location of the memory array, configures the FIFO for Big or Little Endian byte arrangement and
selects serial flag programming, parallel flag program m ing, or
one of the three possible default flag offset settings, 8, 16, or
64. Each FIFO has its own independent Master Reset pin,
MRS1
and MRS2.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike M aster Reset, any set tings existing prior to P artial Reset ( i.e., progr amming meth od and partial flag default offsets) are retained. Partial Reset is useful
since it permits fl ushing of the FI FO memory witho ut chang in g
any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1
The CY7C436X4AV have two modes of operation: In the CY
Standard mode, the first word writt en to an empty FIFO is deposited into the memory array. A read operation is required to
access that word (along with all other words residing in memory). In the First-Word Fall-Through mode (FW FT), the first
and PRS2.
CY7C43664AV/CY7C43684AV
long-word (36-bit wide) written to an empty FIFO appears automatically on the out puts, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT
operation dete rmines t he mod e in use.
Each FIFO has a combined Empty/Output Ready flag (EFA
ORA and EFB
(FFA
/IRA and F FB/IRB). The EF a nd FF func tions ar e select ed
in the CY Standard mode. EF
is full or not. The IR and OR functions are sele cted in the First Word F all- Through mode. IR indi cates whet her or not the FIFO
has ava il able memory locations. OR shows whet her the FIFO
has data available for read ing or not. It marks the presence of
valid data on the outputs.
Each FIFO has a programmable Al mo st Empty flag (AEA
AEB
) and a programmable Almost Full flag (AFA and AFB).
AEA
and AEB indicate when a selected number of words written to FIFO memory achieve a predetermined “almost empty
state.” AFA
words written t o the m emory achi ev e a predet ermined “almost
full sta te.”
IRA, IRB, AFA
writes data into its array. ORA, ORB, AEA
chronized to th e port clock that reads data from its arr ay. Programmable offset for AEA
parallel usi ng Port A or i n serial v ia the SD i nput. Three d efault
offset settings are also pro vided . The AEA
can be set at 8, 16, or 64 locations from the empty boundary
and AF A
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO is not actively performing a
function, the chip will automatically power down. During the
power down state, supply current consumption (I
minimum. Init iating any oper ati on (b y act iv atin g contr ol inputs )
will immediately take the device out of the Power Down state.
A Retransmit feature is available on these devices.
The CY7C436X4AV are characterized for operation from 0
°
to 70
C. Input ESD protect ion is g reater than 2001V, and latch-
up is prevented by the use of guard rings.
/ORB) and a combined Full/Input Ready flag
indicates whether the memory
and AFB indicate when a selected number of
, and AFB are synchro nized to the port clock tha t
, AEB, AFA, and AFB are loaded in
and AFB threshol d can be se t at 8, 16, or 64 locat ions
pin during F IFO
and
, and AEB are syn-
and AEB threshold
) is at a
CC
°
/
C
Selectio n Gu ide
CY7C43644/64/84AV
Maximum Frequency (MHz) 133 100 66.7
Maximum Access Time (ns) 6 8 10
Minimum Cycle Time (ns) 7.5 10 15
Minimum Data or Enable Set-Up (ns) 3 4 5
Minimum Data or Enable Hold (ns) 0 0 0
Maximum Flag Delay (ns) 6 8 10
Active Power Supply
Current (I
Density 1K x 36 x2 4K x 36 x2 16K x 3 6 x 2
Package 128 TQFP 128 TQFP 128 TQFP
CC1
) (mA)
Commercial 60 60 60
Industrial 60
CY7C43644AV CY7C43664AV CY7C43684AV
7
−
3
CY7C43644/64/84AV
10
−
CY7C43644/64/84AV
15
−
CY7C43644AV
PRELIMINARY
CY7C43664AV/CY7C43684AV
Pin Definitions
Signal Name Description I/O Function
A
0–35
AEA
AEB
AF A Port A Almost
AFB
B
0–35
BE/FWFT
BM Bus Match
CLKA Port A Clock I CLKA is a continuous clock t hat synchr onizes al l data tr ansf ers through P ort A a nd can
CLKB Port B Clock I CLKB is a continuous clock t hat synchr onizes al l data tr ansf ers through P ort B a nd can
CSA
CSB
EFA
/ORA Port A Empty/
EFB
/ORB Port B Empty/
ENA Port A Enable I ENA must be HIGH to enable a L O W -to- HIGH tra nsition of CLKA to rea d or write dat a
ENB Port B Enable I ENB must be HIGH to enable a L O W -to- HIGH tra nsition of CLKB to rea d or write dat a
FFA
/IRA Port A Full/Input
Port A Data I/O 36-bit bidirectional data port for side A.
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Full Flag
Port B Almost
Full Flag
Port B Data I/O 36-bit bidirect ional data port for side B.
Big Endian/
First-Word FallThrough Select
Select (Port A)
Port A Chip
Select
Port B Chip
Select
Output Ready
Flag
Output Ready
Flag
Ready Flag
O Programmab le Almost Empty flag sy nchroni zed to CLKA. It is LO W when the numb er
of words in FIFO2 is less t han or equa l to the val ue in the Alm ost Empty A of fset register ,
X2.
O Programmab le Almost Empty flag sync hroni zed to CLKB . It is LO W when the nu mber
of words in FIFO1 is less t han or equa l to the val ue in the Alm ost Empty B of fset register ,
X1.
O Programmab le Almost Full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.
O Programmab le Almost Full flag synchronized to CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
I This is a dual-purpose pin. During Maste r Reset, a HIGH on BE will selec t Big Endian
operation. In thi s case, depe nding on the bus size, the most signi ficant byt e or word on
Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data
flow). A LO W on BE will select Little Endia n operati on. In this case , the lea st significant
byte or word on Port A is read from P ort B fir st ( for A-to-B da ta f low) or written to Port
B first (B-to -A data flo w). Af ter Mast er Reset , th is pi n selec ts th e timi ng mode . A HI GH
on FWFT
Once the timing mode has be en selecte d, the le ve l on FWFT
device operation.
I A HIGH on this pin enables either b yte or wor d bus widt h on Po rt B, dependin g on the
state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to
select the bus size and endian arrangement for Port B. The lev el of BM must be st ati c
throughout device operation.
be asynchronous or coincident to CLKB. FFA
synchronized t o the LOW-to-HIGH transition of CLKA.
be asynchronous or coincident to CLKA. FFB
synchronized t o the LOW-to-HIGH transition of CLKB.
ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
O This is a dual -function pin. In the CY Stand ard mode , the EF A func tion is selected. EF A
indicates whether or not the FIFO2 memo ry is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
able for reading. EFA
O This is a dual-funct ion pin. In the CY Standard mode , the EFB functio n is selected. EFB
indicates whether or not the FIFO1 memo ry is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
able for reading. EFB
on Port A.
on Port B.
O This is a dual-fu nction pi n. In the CY Stand ard mode, the FFA function is selecte d. FF A
indicates whether or not t he FIFO1 memory is full. In the FWFT mode , the IRA function
is selected. IRA indicat es whether or not there is space av ailable fo r writing to the FIFO1
memory. FFA
selects CY Standard mode , a LOW selects First-Word Fall-Thro ugh m ode.
outputs are in the high-impedance state when CSA is HIGH.
0–35
outputs are in the high- impedance state when CSB is HIGH.
0–35
/ORA is synchronized to t he LOW-to-HIGH transition of CLKA.
/ORB is synchronized to t he LOW-to-HIGH transition of CLKB.
/IRA is syn ch r on i ze d to th e L OW-to-H IG H tra n s iti o n o f CLK A .
must be stati c through out
/IRA, E FA/ORA, AFA, and AEA are all
/IRB, EFB /ORB, AFB, and AEB are all
outputs, avail-
0–35
outputs, avail-
0–35
4
CY7C43644AV
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
FFB/IRB Port B Full/Input
FS1/SEN
FS0/SD Flag Offset
MBA Port A Mailbox
MBB Port B Mailbox
MBF1
MBF2
MRS1
MRS2
PRS1
PRS2
RT1
RT2
SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9- bit) size on P ort B. A LOW
(continued)
Ready Flag
Flag Offset
Select 1/Serial
Enable
Select 0/Serial
Data
Select
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
FIFO1 Partial
Reset
FIFO2 Partial
Reset
Retransmit
FIFO1
Retransmit
FIFO2
O This is a du al-functi on pin. I n the CY St andard m ode, th e FFB funct ion is selected. FFB
indicates whether or not t he FIFO2 memory is full. In the FWFT mode , the IRB function
is selected. IRB indicat es whether or not there is space av ailable fo r writing to the FIFO2
memory. FFB
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During Master Reset , FS1/ SEN
offset program ming method. Three offs et register prog ramming methods are a vailab le:
automatically load one of three preset values (8, 16, or 64), parallel l oad from Port A,
I
and serial load. When serial load i s selec ted f or fl ag offs et regi ster p rogr amming, FS1/
SEN
is used as an enab le synchron ous to the LO W -to-HIGH tr ansition of CLKA. When
FS1/SEN
and Y registers. The number of bi t writes r equir ed to pr ogr am the of fset re gisters i s 4 0
for the CY7C43644AV, 48 for the CY7C43664AV, and 56 f or the CY7C43684AV. The
first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
I A HIGH lev el on MBA chooses a mailbox regi ster for a Port A read or write operation.
When the A
register for output and a LOW level select s FIFO2 output register data for output.
I A HIGH lev el on MBB chooses a mailbox regi ster for a Port B read or write operation.
When the B
register for output and a LOW level select s FIFO1 output register data for output.
OMBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail 1
register. Writes to the Mail1 register are inhibited while MBF1
HIGH by a LOW- to-HI GH transiti on of CLKB when a Po rt B read is selected and MBB
is HIGH. MBF1
OMBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail 2
register. Writes to the Mail2 register are inhibited while MBF2
HIGH by a LOW- to-HI GH transiti on of CLKA when a Po rt A read is selected and MBA
is HIGH. MBF2
I A LOW on this pin initializes the FIFO1 read and write pointers to the first locati on of
memory and sets the P ort B output register to a ll zeroes. A LOW puls e on MRS1
the programmi ng method (serial or parallel ) and one of th ree programmab le flag def ault
offsets f or FIFO1. It al so confi gures Port B for bus siz e and endian arr a ngement. F ou r
LOW-t o-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must
occur while MRS1
I A LOW on this pin initializes the FIFO2 read and write pointers to the first locati on of
memory and sets the P ort A output register to a ll zeroes. A LOW puls e on MRS2
one of three program ma ble flag default offsets for FIFO2. Four LOW-to- HIGH transitions of CLKA and four LOW-to-H IGH transitions of CLKB must occur whi le MRS2
LOW.
I A LOW on this pin initializes the FIFO1 read and write pointers to the first locati on of
memory and sets the Port B output register to all zeroes. During Partial Reset, the
currently selected bus size , endian arrangement, programmi ng me thod (serial or parallel), and progr am m able flag settings are all retained.
I A LOW on this pin initializes the FIFO2 read and write pointers to the first locati on of
memory and sets the Port A output register to all zeroes. During Partial Reset, the
currently selected bus size , endian arrangement, programmi ng me thod (serial or parallel), and progr am m able flag settings are all retained.
I A LOW strobe on this pin will retransmit data on FIFO1 fro m the location of the write
pointer at the last P artial or Master reset.
I A LOW strobe on this pin will retransmit data on FIFO2 fro m the location of the write
pointer at the last P artial or Master reset.
on this pin when BM is HIGH sele cts word (18-bit) bus size. SI ZE works with BM and
BE to select the bus size and endian arrangement for Port B. The level of SIZE must
be static throughout device operation.
/IRB is syn ch r on i ze d to th e L OW-to-H IG H tra n s iti o n o f CLK B.
is LOW, a rising edge on CLKA loads t he bit present on FS0/SD into the X
outputs are active, a HIGH level on MBA selects data from the Mail2
0–35
outputs are active, a HIGH level on MBB selects data from the Mail1
0–35
is set HIGH following either a Master or Partial Reset of FIFO1.
is set HIGH following either a Master or Partial Reset of FIFO2.
is LOW.
CY7C43664AV/CY7C43684AV
and FS0/SD , toget her with SPM, sel ect the f lag
is LOW. MBF1 is se t
is LOW. MBF2 is se t
selects
selects
is
5
CY7C43644AV
CY7C43664AV/CY7C43684AV
Pin Definitions
PRELIMINARY
(continued)
Signal Name Description I/O Function
SPM
W/RA
W/
RB Port B Write/
Maximum Ratings
Serial
Programming
Port A Write/
Read Select
Read Select
[1]
I A LOW on this pin se lects serial prog ramming o f partial flag offs ets. A HIGH on thi s pin
selects paral lel programming or default off sets (8, 16, or 64).
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LOW-t o-HIGH transition of CLKA. The A
when W/RA
is HIGH.
0–35
I A LOW selects a write operation and a HIGH sel ects a read operation on Port B for a
LOW-to-HIGH transitio n o f CLKB . T h e B
when W
/RB is LOW.
0–35
Static Discharge Voltage ........... ............ .. ............ .. ....>2001V
(per MIL-STD-883, Method 3015)
(Abov e which the useful life may be impaired. For user guidelines, not tested.)
Latch-Up Current .....................................................>200 mA
Storage Temperature .......... ............ .............–65°C to +150°C
Ambient Temperature with
Operating Range
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[2]
......................................–0.5V to VCC+0.5V
[2]
...................................–0.5V to VCC+0.5V
Range
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
Output C ur re n t in to O u tp u ts (LOW) ..... ......... .......... .....20 mA
outputs are i n the high-impedance state
outputs are in the high-impedance state
Ambient
Temperature
[3]
V
CC
Electrical Characteristics
Over the Operating Range
CY7C43644/64/84AV
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZL
I
OZH
[4]
I
CC1
[5]
I
SB
Capacitance
Output HIGH Voltage VCC = 3.0V ,
I
= –2.0 mA
OH
Output LOW Voltage VCC = 3.0V ,
I
= 8.0 mA
OL
Input HIGH Volta g e 2.0 V
Input LOW Voltage –0.5 0.8 V
Input Leakage Current V
Output OFF, High Z
= Max. –10 +10 µA
CC
VSS < VO< V
Current
Active Power Supply
Current
Ave rage Standby
Current
[6]
2.4 V
0.5 V
CC
–10 +10
Com’l 60 mA
Ind 60 mA
Com’l 12 mA
Ind 12 mA
CC
UnitMin. Max.
µA
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
3. Operating V
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded.
5. All inputs = V
6. Tested initially and after any design or process changes that may affect these parameters.
Range for -7 speed is 3.3V ± 5%.
CC
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
CC
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 3.3V
Output Capacitance 8 pF
CC
4 pF
V
6
CY7C43644AV
PRELIMINARY
AC Test Loads and Waveforms (-10 & -15)
R1=330
3.3V
OUTPUT
CL=30 pF
INCLUDING
JIG AND
SCOPE
AC Test Loads and Waveforms (-7)
I/O
Z0=50
Ω
R2=680
Ω
VCC/2
50Ω
Ω
3.0V
GND
3.0V
GND
CY7C43664AV/CY7C43684AV
ALL INPUT PULSES
90%
90%
10%
10%
3
ns
≤
3
ns
≤
≤
≤
90%
10%
3ns
ALL INPUT PULSES
90%
10%
3ns
Switching Characteristics
Over the Operating Range
Parameter Description
f
S
t
CLK
t
CLKH
t
CLKL
t
DS
t
ENS
t
RSTS
t
FSS
t
BES
t
SPMS
t
SDS
t
SENS
t
FWS
t
DH
t
ENH
Note:
7. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
Clock Frequency, CLKA or CLKB 133 100 67 MHz
Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns
Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns
Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns
Set-U p Tim e, A
CLKB↑
before CLKA↑ and B
0–35
0–35
before
Set-Up Time, CSA, W/RA, ENA, and MBA before
CLKA↑; CSB
Set-Up Time, M RS1, MRS2, PRS1, or PRS2 LOW
before CLKA↑ or CLKB↑
, W/RB, ENB, and MBB be for e CLKB↑
[7]
Set-Up Time , FS0 and FS1 bef ore MRS1 a nd MRS2
HIGH
Set-Up Time, BE/FWFT before MRS1 and MRS2
HIGH
Set-Up Time, SPM before MRS 1 and MRS2 HIGH 5 7 7.5 ns
Set-Up Time, FS0/SD before CLKA↑ 3 4 5 ns
Set-Up Time, FS1/SEN before CL K A ↑ 3 4 5 ns
Set-Up Time, BE/FWFT before CLKA↑ 0 0 0 ns
Hold Time, A
CLKB↑
after CLKA↑ and B
0–35
0–35
after
Hold Time, CSA, W/RA, ENA, and MBA after
CLKA↑; CSB
, W/RB, ENB, and MBB after CLKB↑
CY7C43644/
64/84AV
–7
CY7C43644/
64/84AV
–10
CY7C43644/
64/84AV
–15
UnitMin. Max. Min. Max. Min. Max.
3 4 5 ns
3 4 5 ns
2.5 4 5 ns
5 7 7.5 ns
5 7 7.5 ns
0 0 0 ns
1 2 0 ns
7
CY7C43644AV
CY7C43664AV/CY7C43684AV
CY7C43644/
64/84AV
–7
CY7C43644/
64/84AV
–10
CY7C43644/
64/84AV
–15
Switching Characteristics
PRELIMINARY
Over the Operating Range (continued)
Parameter Description
t
RSTH
t
FSH
t
BEH
t
SPMH
t
SDH
t
SENH
t
SPH
t
SKEW1
t
SKEW2
t
A
t
WFF
t
REF
t
PAE
t
PAF
Hold Time, MRS1, MRS 2, PRS1, or PRS2 LOW
after CLKA↑ or CLKB↑
[7]
Hold Time, FS0 and FS1 after MRS1 and MRS2
1 1 4 ns
1 1 2 ns
HIGH
Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 0 0 2 ns
Hold Time, SPM after MRS1 and MRS2 HIGH 0 0 2 ns
Hold Time, FS0/SD after CLKA↑ 0 1 0 ns
Hold Time, FS1/SEN after CLKA↑ 5 5 0 ns
Hold Time, FS1/SEN HIGH after MRS1 and MRS2
2 2 2 ns
HIGH
[8]
Skew Time between CLKA↑ and CLKB↑ for EFA/
ORA, EFB
[8]
Skew Time between CLKA↑ and CLKB↑ for AEA,
AEB
Access Time, CLKA↑ to A
/ORB, FFA/IRA, and FFB/IRB
, AFA, AFB
and CLKB↑ to B
0–35
Propagation Delay Time, CLKA↑ to FFA/IRA a n d
CLKB↑ to FFB
/IRB
Propagation Delay Time, CLKA↑ to EFA/ORA and
CLKB↑ to EFB
/ORB
Propagation Delay Time, CLKA↑ to AEA and
0–35
7.5 7.5 7.5 ns
7 8 12 ns
1 6 1 8 3 10 ns
1 6 1 8 2 10 ns
1 6 1 8 1 10 ns
1 6 1 8 1 10 ns
CLKB↑ to AEB
Propagation Dela y Time, CLKA↑ to AFA and CLKB↑
1 6 1 8 1 10 ns
to AFB
t
PMF
Propagation Delay Time, CLKA↑ to MBF 1 LOW or
MBF2
HIGH and CLKB↑ to MBF2 LOW or MBF 1
0 6 0 8 0 10 ns
HIGH
t
PMR
t
MDV
t
RSF
t
EN
t
DIS
Propagation Delay Time, CLKA↑ to B
CLKB↑ to A
0–35
[10]
Propagation Delay Time, MBA to A
MBB to B
0–35
Va lid
Propagation Delay Time, MRS1 or PRS1 LOW to
AEB
LOW, AFA HIGH, FFA / IRA LOW, EFB /ORB
LOW and MBF1
AEA
LOW, AFB HIGH, FFB / IRB LOW, EFA /ORA
LOW and MBF2
HIGH and MRS2 or PRS2 LOW t o
HIGH
Enable Time, CSA or W/RA LOW to A
and CSB
LOW and W/RB HIGH to B
Disable Time , CSA or W/RA HIGH to A
Impedance an d CSB
HIGH or W/RB LOW to B
at High Impedance
t
PRT
t
RTR
Notes:
8. Ske w time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
9. Writing data to the Mail1 register when the B
10. Writing data to the Mail2 register when the A
Retransmit pulse Width 60 60 60 ns
Retransmit Recovery Time 90 90 90 ns
outputs are active and MBB is HIGH.
0–35
outputs are active and MBA is HIGH.
0–35
0–35
Valid and
0–35
0–35
0–35
0–35
[9]
and
Active
Active
at High
0–35
1 7 2 11 3 12 ns
1 6 2 9 3 11 ns
1 6 1 10 1 15 ns
1 5 2 8 2 10 ns
1 5 1 6 1 8 ns
UnitMin. Max. Min. Max. Min. Max.
8
CY7C43644AV
PRELIMINARY
Switching Waveforms
FIFO1 Master Reset Loading X1 and Y1 with a Preset Value of Eight
CLKA
CLKB
t
RSTS
MRS1
BE/FWFT
SPM
FS1/SEN
FS0/SD
FFA
EFB
/IRA
/ORB
,
t
RSF
t
RSF
CY7C43664AV/CY7C43684AV
[11, 12]
t
RSTS
t
FWS
FWFT
t
WFF
t
SPMS
t
t
BES
FSS
BE
t
BEH
t
SPMH
t
FSH
t
RSF
AEB
t
RSF
AFA
t
RSF
MBF1
Notes:
11. Master Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
12. PRS1
must be HIGH during Master Reset.
9
CY7C43644AV
PRELIMINARY
Switching Waveforms
FIFO1 Partial Reset (CY Stan dard and FW FT Mo des)
CLKA
CLKB
PRS1
FFA/IRA
EFB
/ORB
AEB
AFA
MBF1
(continued)
t
RSTS
t
RSF
t
RSF
t
RSF
t
RSF
t
RSF
[13, 14]
CY7C43664AV/CY7C43684AV
t
RSTH
t
WFF
Parallel Program ming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
[15]
CLKA
, MRS2
MRS1
t
FSS
t
FSH
SPM
t
FSS
t
FSH
FS1/SEN,
FS0/SD
FFA/
IRA
t
WFF
t
ENS
t
ENH
ENA
t
DS
DH
AEB Offset (X1)
AFB
Offset (Y2)
AEA
Offset (X2)
A
0 − 35
t
AFA Offset (Y1)
CLKB
/IRB
FFB
Notes:
13. Partial Reset is performed in the same manner for FIFO2.
14. MRS1
15. CSA
16. t
must be HIGH during Partial Reset.
=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
SKEW1
edge of CLKA and rising edge of CLKB is less than t
, then FFB/IRB may transition HIGH one cycle later than shown.
SKEW1
[16]
t
SKEW1
First Word to FIFO1
10
CY7C43644AV
PRELIMINARY
t
FSH
(continued)
t
SPH
t
SDS
AFA Offset (Y1) MSB
t
SENS
[17]
t
SENH
t
SDH
t
SENS
t
SDS
AEA Offset (X2) LSB
Switching Waveforms
Serial Programming of the Almost -Full Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Modes)
CLKA
MRS1
, MRS2
t
FSS
SPM
FFA/IRA
FS1/SEN
FS0/SD
CLKB
FFA/
IRA
[18]
t
FSS
CY7C43664AV/CY7C43684AV
t
WFF
t
SKEW1
t
SENH
t
SDH
t
WFF
Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)
t
CLK
CLKA
FFA
CSA
/IRA
HIGH
t
CLKH
t
CLKL
t
ENS
t
ENStENH
t
ENH
W/RA
t
t
ENH
ENS
MBA
t
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
ENH
ENA
t
t
DS
A
0–35
Notes:
17. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
18. Programmable offsets are written serially to the SD input in the order AFA
19. Written to FIFO1.
W1
[19]
DH
[19]
W2
offset (Y1), AEB offset (X1), AFB offset (Y2), and AEA offset (X2).
11
CY7C43644AV
CY7C43664AV/CY7C43684AV
Switching Waveforms
PRELIMINARY
(continued)
Port B Long-Word Write Cycle Timing for FIFO2 (CY Standard and FW FT Modes)
t
CLKH
CLK
t
CLKL
t
CLKB
/IRB
FFB
HIGH
t
ENS
t
ENH
CSB
t
t
ENH
ENS
W/RB
t
t
ENS
ENH
MBB
t
ENS
t
ENH
t
ENS
t
ENH
ENB
tDSt
B
0−35
W1
[20]
DH
W2
[20]
t
ENStENH
Port B Word Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)
CLKB
/IRB
FFB
HIGH
t
ENS
t
CSB
t
ENS
W/RB
t
ENStENH
t
ENS
t
MBB
t
t
ENS
t
ENH
t
ENS
ENB
t
B
0–17
Note:
20. Written to FIFO2.
DStDH
ENH
ENH
ENH
12
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