CYPRESS CY7C277 User Manual
77
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CY7C277
32K x 8 Reprogrammable Registered PROM
Features
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
—30-ns address set-up
—15-ns clock to output
• Low power
—60 mW (commercial)
—715 mW (military)
• Programmable address latch enable input
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered output registers
• EPROM technology, 100% programmable
• Slim 300-mil, 28-pin plastic or hermetic DIP
• 5V ±10% V
, commercial and military
CC
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of wi thstanding greater than 2001V static dis-
charge
Logic Block Diagram Pin Configurations
A
A
A
A
A
14
13
12
11
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ALE
15-BIT
ADDRESS
TRANSPARENT/
LATCH
ALE
PROGRAMMABLE
CP/ALE
OPTIONS
E/E
S
CP
X
ADDRESS
Y
ADDRESS
ROW
DECODER
256
1OF
COLUMN
DECODER
32
1OF
D
C
256 x 1024
PROGRAMMABLE
ARRAY
Q
8-BIT
1 OF 128
MUX
PROGRAMMABLE
MULTIPLEXER
8-BIT
EDGE-
TRIGGERED
REGISTER
CP
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
DIP/Flatpack
Top View
1
28
2
27
3
26
4
25
5
24
6
23
22
7
21
8
9
20
10
19
11
18
12
17
13
16
14
15
GND
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
LCC/PLCC (Opaque Only)
Top V iew
CC
V
A9A10A
NC
31
32
1
181920
3
O
O
NC
GND
11
30
29
28
27
26
25
24
23
22
21
4
NC
8
7
A
A
4
6
5
4
3
2
1
0
0
5
6
7
8
9
10
11
12
13
14151617
32
1
O2O
A
A
A
A
A
A
A
O
V
A
A
A
A
A
ALE
CP
E
O
O
O
O
O
5
O
CC
10
11
12
13
14
/E
S
7
6
5
4
3
A
12
A
13
A
14
NC
ALE
CP
E/E
S
O
7
O
6
Selection Guide
7C277-30 7C277-40 7C277-50
Minimum Address Set-Up Time (ns) 30 40 50
Maximum Clock to Output (ns) 15 20 25
Maximum Operat ing
Current (mA)
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-04006 Rev. ** Revised March 4, 2002
Com’l 120 120 120
Mil 130 130
CY7C277
Functional Description
The user may define the polarity of the ALE signal, with the
default being active HIGH.
The CY7C277 is a hi gh-performance 32 K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package.
Maximum Ratings
The ceramic package may be equipped with an erasure window; when exposed to UV l igh t, the PRO M is erased and can
then be reprogrammed. The memory cells utilize proven
EPROM floating-gate technology and byte-wide algorithms.
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current requirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
location is written into, era sed, and repeated ly exercis ed prior
to encapsulation. Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC
specification limits after customer programming.
On the 7C277, the outputs are pipelined through a master-slave register. On the rising edge of CP, data is loaded into
the 8-bit edge triggered output register. The E
/ES input provides a programmable bit to select between asynchronous
and synchronous oper ation. The default cond ition is asynchronous. When the as ynchronou s mod e is s elect ed, the E
/ES pin
operates as an asynchronous output enable. If the synchronous mode is selected, the E
/ES pin is sampled on the rising
edge of CP to ena ble and disa ble the outpu ts. The 7C2 77 also
provides a programmable bit to enable the Address Latch input. If this bit is not pr ogrammed, the device w ill ignore the ALE
pin and the address will enter the device asynchron ously . If the
ALE function is selected, the address enters the PROM while
the ALE pin is active, and is captured when ALE is deasserted.
Electrical Characteristics Over the Operating Range
(Above which the usef ul life ma y be impaire d. For user g uidelines, not tested.)
Storage Temperature ....................................−65°C to +150°C
Ambient Temperature with
Power Applied.................................................−55°C to +125°C
Supply Voltage to Ground Potential.................−0.5V to +7.0V
(Pin 24 to Pin 12)
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 7, 18, 20)...........................13.0V
UV Erasure ...................................................7258 Wsec/cm
Static Discharge Voltage ...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range Ambient Temperature V
Commercial 0°C to +70°C 5V ±10%
[2]
[1]
−40°C to +85°C 5V ±10%
−55°C to +125°C 5V ±10%
Industrial
Military
[3, 4]
7C277-30 7C277-40, 50
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
V
CD
I
OZ
I
OS
I
CC
V
PP
I
PP
V
IHP
V
ILP
Notes:
1. Contact a Cypress representative for industrial temperature range specifications.
2. T
is the “instant on ” case temperatu re.
A
3. See the last page of this specification for Gro up A subgro up testing information.
4. See “Introduction to CMOS PROMs” in this Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Output HIGH Voltage VCC = Min., IOH = − 2.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Level Guaranteed Input Logical HIGH
Input LOW Level Guaranteed Input Logical LOW
Input Leakage Current GND < VIN < V
Input Clamp Diode Voltage Note 4
Output Leakage Current 0 < V
Output Short Circuit Current VCC = Max., V
Power Supply Current VCC = Max., CS > V
Programming Supply Voltage 12 13 12 13 V
Programming Supply Current 50 50 mA
Input HIGH Programming Voltage 3.0 3.0 V
Input LOW Programming Voltage 0.4 0.4 V
Description Test Conditions Min. Max. Min. Max. Unit
Voltage for All Inputs
2.0 V
CC
0.8 0.8 V
Voltage for All Inputs
−10 +10 −10 +10 µA
[5]
−40 +40 −40 +40 µA
−20 −90 −20 −90 mA
I
OUT
CC
< VCC, Output Disabled
OUT
= 0.0V
OUT
= 0 mA
[6]
Commercial 120 120 mA
IH
Military 130
2.0 V
CC
2
CC
V
Document #: 38-04006 Rev. ** Page 2 of 13
CY7C277
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
AC Test Loads and Wavefor ms
R1 500Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(658
(a) NormalLoad
Equivalent to: THÉ VENIN EQUIVALENT
OUTPUT 2.0V
CY7C277 Switching Characteristics Over the Operating Range
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
R1 500
Load
Ω
CC
R2
333
3.0V
Ω
GND
<5ns
OUTPUT 1.9V
250Ω
Military
[3, 4]
Output Capacitance 10 pF
[4]
Ω MIL)
R2
333
Ω
Ω MIL) (403Ω MIL)
(403
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
(658Ω MIL)
5pF
(b) HighZ
Ω
200
Commercial
10 pF
ALL INPUT PULSES
90%
10%
90%
10%
<5ns
7C277-30 7C277-40 7C277-50
Parameter Description Min. Max. Min. Max. Min. Max. Unit
t
AL
t
LA
t
LL
t
SA
t
HA
t
SES
t
HES
t
CO
t
PWC
[7]
t
LZC
t
HZC
[8]
t
LZE
[8]
t
HZE
Notes:
7. Applies only when the synchronous (E
8. Applies only when the asynchronous (E
Address Set-Up to ALE Inactive 5 10 10 ns
Address Hold from ALE Inactive 10 10 15 ns
ALE Pulse Width 10 10 15 ns
Address Set-Up to Clock HIGH 30 40 50 ns
Address Hold from Clock HIGH 0 0 0 ns
ES Set-Up to Clock HIGH 12 15 15 ns
ES Hold from Clock HIGH 5 10 10 ns
Clock HIGH to Output Valid 15 20 25 ns
Clock Pulse Width 15 20 20 ns
Output Valid from Clock HIGH 15 20 30 ns
Output High Z from Clock HIGH 15 20 30 ns
Output Valid from E LOW 15 20 30 ns
Output High Z from E HIGH 15 20 30 ns
) function is used.
S
) function is us ed.
Document #: 38-04006 Rev. ** Page 3 of 13
Architecture Configuration Bits
Architecture Bit Architecture Verify D7 - D
ALE D
ALEP D
E/E
S
D
0 = DEFAULT Input Transparent
1
1 = PGMED Input Latched
0 = DEFAULT ALE = Active HIGH
2
1 = PGMED ALE = Active LOW
0 = DEFAULT Asynchronous Output Enable (E)
0
1 = PGMED Synchronous Output Enable (ES)
CY7C277
0
Function
Bit Map
Programmer Address
(Hex.) RAM Data
0000
.
.
.
7FFF
8000
Timing Diagram (Input Latched)
A0-A
14
t
SES
t
HZC
t
LA
ALE
(SYNCH)
O
-O
0
E
CP
t
AL
t
LL
S
7
t
t
CO
HES
Data
.
.
.
Data
Control Byte
[9]
t
PWC
t
HES
t
PWC
HIGHZ
Architecture Byte (8000
)
D7 D0
C
7C6C5C4 C3
t
SES
t
LZC
C2 C1 C
t
SA
t
HZE
0
t
HA
HIGHZ
t
LZE
E
(ASYNCH)
S
Timing Diagram (Input Transparent)
A0-A
14
t
SA
E
S
(SYNCH)
CP
t
HES
t
CO
t
SES
t
HZC
t
PWC
t
HES
t
PWC
t
SES
t
LZC
HIGHZ
O
-O
0
7
t
HZE
E
(ASYNCH)
Note:
S
9. ALE is shown with positive polarity.
Document #: 38-04006 Rev. ** Page 4 of 13
t
HA
HIGHZ
t
LZE
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