Cypress CY7C2576KV18, CY7C2563KV18, CY7C2561KV18, CY7C2565KV18 User Manual

72-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency) with ODT

PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Features

Note

1. The Cypress QDR-II+ devices surpass the QDR consortium specification and can support V

DDQ

= 1.4V to VDD.

Configurations

■ Separate independent read and write data ports ❐ Supports concurrent transactions

■ 550 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write

ports (data transferred at 1100 MHz) at 550 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ On-Die Termination (ODT) feature ❐ Supported for D

■ Single multiplexed address input bus latches address inputs

[x:0]

, BWS

, and K/K inputs

[x:0]

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR™-II+ operates with 2.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to QDR-I device with 1 cycle read latency

when DOFF

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V ❐ Supports both 1.5V and 1.8V IO supply

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Phase Locked Loop (PLL) for accurate data placement

is asserted LOW

= 1.8V± 0.1V; IO V

= 1.4V to V

DDQ

[1]

With Read Cycle Latency of 2.5 cycles:

CY7C2561KV18 – 8M x 8

CY7C2576KV18 – 8M x 9

CY7C2563KV18 – 4M x 18

CY7C2565KV18 – 2M x 36

Functional Description

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR-II architecture, QDR-II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common IO devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C2561KV18), 9-bit words (CY7C2576KV18), 18-bit words (CY7C2563KV18), or 36-bit words (CY7C2565KV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K fying system design by eliminating bus “turn-arounds”.

These devices have an On-Die Termination feature supported for D

[x:0]

external termination resistors, reduce cost, reduce board area, and simplify board routing.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the K or K conducted with on-chip synchronous self-timed write circuitry.

), memory bandwidth is maximized while simpli-

, BWS

, and K/K inputs, which helps eliminate

[x:0]

input clocks. All data outputs pass through output

input clocks. Writes are

Table 1. Selection Guide

Description 550 MHz 500 MHz 450 MHz 400 MHz Unit

Maximum Operating Frequency 550 500 450 400 MHz Maximum Operating Current x8 900 830 760 690 mA

x9 900 830 760 690 x18 920 850 780 710 x36 1310 1210 1100 1000

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-15887 Rev. *E Revised April 24, 2009

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Logic Block Diagram (CY7C2561KV18)

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write

Reg

(20:0)

2M x 8 Array

DOFF

[7:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

[8:0]

2M x 9 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[0]

REF

Write Add. Decode

Write

Reg

(20:0)

2M x 9 Array

DOFF

QVLD

Write

Reg

Write

Reg

Write

Reg

Logic Block Diagram (CY7C2576KV18)

Document Number: 001-15887 Rev. *E Page 2 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Logic Block Diagram (CY7C2563KV18)

1M x 18 Array

CLK

(19:0)

Gen.

Control

Logic

Address Register

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(19:0)

1M x 18 Array

DOFF

[17:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

512K x 36 Array

CLK

(18:0)

Gen.

Control

Logic

Address Register

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

144

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(18:0)

512K x 36 Array

DOFF

[35:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

Logic Block Diagram (CY7C2565KV18)

Document Number: 001-15887 Rev. *E Page 3 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Pin Configuration

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C2561KV18 (8M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAWPSNWS

B NC NC NC A NC/288M K NWS

C NC NC NC V

D NC D4 NC V

E NC NC Q4 V

F NC NC NC V

G NC D5 Q5 V

H DOFF V

REF

DDQ

J NC NC NC V

K NC NC NC V

L NC Q6 D6 V

M NC NC NC V

N NC D7 NC V

DDQ

ANCAVSSNC NC D3

AAAVSSNC NC NC

P NC NC Q7 A A QVLD A A NC NC NC

R TDOTCKAAAODTAAATMSTDI

K NC/144M RPS AACQ

ANCNCQ3

DDQ

[2]

NC NC NC

NC D2 Q2

NC NC NC

DDQ

REF

NC Q1 D1

NC NC NC

NC NC Q0

NC NC D0

CY7C2576KV18 (8M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAWPSNC K NC/144M RPS AACQ

B NC NC NC A NC/288M K BWS

C NC NC NC V

D NC D5 NC V

E NC NC Q5 V

F NC NC NC V

G NC D6 Q6 V

H DOFF V

REF

DDQ

J NC NC NC V

K NC NC NC V

L NC Q7 D7 V

M NC NC NC V

N NC D8 NC V

DDQ

ANCAVSSNC NC D4

AAAVSSNC NC NC

ANCNCQ4

DDQ

NC NC NC

NC D3 Q3

NC NC NC

DDQ

REF

NC Q2 D2

NC NC NC

NC NC Q1

NC NC D1

P NC NC Q8 A A QVLD A A NC D0 Q0

R TDOTCKAAAODTAAATMSTDI

Document Number: 001-15887 Rev. *E Page 4 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Pin Configuration

The pin configuration for CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, and CY7C2565KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C2563KV18 (4M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A WPS BWS

B NC Q9 D9 A NC K BWS

C NC NC D10 V

D NC D11 Q10 V

E NC NC Q11 V

F NC Q12 D12 V

G NC D13 Q13 V

H DOFF V

REF

DDQ

J NC NC D14 V

K NC NC Q14 V

L NC Q15 D15 V

M NC NC D16 V

N NC D17 Q16 V

DDQ

ANCAVSSNC Q7 D8

AAAVSSNC NC D1

P NC NC Q17 A A QVLD A A NC D0 Q0

R TDOTCKAAAODTAAATMSTDI

K NC/288M RPS AACQ

ANCNCQ8

DDQ

[2]

(continued)

NC NC D7

NC D6 Q6

NC NC Q5

NC NC D5

DDQ

REF

NC Q4 D4

NC D3 Q3

NC NC Q2

NC Q1 D2

CY7C2565KV18 (2M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/288M A WPS BWS

B Q27 Q18 D18 A BWS

C D27 Q28 D19 V

D D28 D20 Q19 V

E Q29 D29 Q20 V

F Q30 Q21 D21 V

G D30 D22 Q22 V

H DOFF V

REF

DDQ

J D31 Q31 D23 V

K Q32 D32 Q23 V

L Q33 Q24 D24 V

M D33 Q34 D25 V

N D34 D26 Q25 V

DDQ

ANCAVSSD16 Q7 D8

AAAVSSQ10 D9 D1

K BWS

RPS A NC/144M CQ

KBWS0AD17Q17Q8

DDQ

Q16 D15 D7

Q15 D6 Q6

D14 Q14 Q5

Q13 D13 D5

DDQ

REF

D12 Q4 D4

Q12 D3 Q3

D11 Q11 Q2

D10 Q1 D2

P Q35 D35 Q26 A A QVLD A A Q9 D0 Q0

R TDOTCKAAAODTAAATMSTDI

Document Number: 001-15887 Rev. *E Page 5 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Table 2. Pin Definitions

Note

3. On-Die Termination (ODT) feature is supported for D

[x:0]

, BWS

[x:0]

, and K/K inputs.

Pin Name IO Pin Description

[x:0]

WPS Input-

NWS

Input-

Synchronous

Input-

Synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C2561KV18 − D CY7C2576KV18 − D CY7C2563KV18 − D CY7C2565KV18 − D

[7:0] [8:0] [17:0] [35:0]

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D

Nibble Write Select 0, 1 − Active LOW (CY7C2561KV18 Only). Sampled on the rising edge of the K and K

clocks

when write operations are active during the current portion of the write operations. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

. Used to select which nibble is written into the device

NWS

controls D

ignores the corresponding nibble of data and it is not written into the device

BWS0, BWS

BWS

, ,

Input-

Synchronous

Byte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when write operations are active. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C2576KV18 − BWS CY7C2563KV18 − BWS0 controls D CY7C2565KV18 − BWS0 controls D BWS

controls D

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

[26:18]

controls D

and BWS3 controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[35:27].

ignores the corresponding byte of data and it is not written into the device

A Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C2561KV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C2576KV18, 4M x 18 (4 arrays each of 1M x 18) for CY7C2563KV18 and 2M x 36 (4 arrays each of 512K x 36) for CY7C2565KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C2561KV18 and CY7C2576KV18, 20 address inputs for CY7C2563KV18 and 19 address inputs for CY7C2565KV18. These inputs are ignored when the appropriate port is deselected.

[x:0]

RPS Input-

Outputs-

Synchronous

Data Output Signals. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of the K and K read port, Q CY7C2561KV18 − Q CY7C2576KV18 − Q CY7C2563KV18 − Q CY7C2565KV18 − Q

are automatically tri-stated.

[x:0]

[7:0] [8:0] [17:0] [35:0]

clocks during read operations. On deselecting the

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the K

clock. Each read access consists of a burst of four sequential transfers.

QVLD Valid output

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ

indicator

ODT

[3]

On-Die

Termination

input pin

On-Die Termination Input. This pin is used for On-Die termination of the input signals. ODT range selection is made during power up initialization. A LOW on this pin selects a low range that follows RQ/3.33 for 175Ω < that follows RQ/1.66 for 175Ω <

RQ < 350Ω (where RQ is the resistor tied to ZQ pin). A HIGH on this pin selects a high range

RQ < 250Ω (where RQ is the resistor tied to ZQ pin). When left floating,

a high range termination value is selected by default.

[17:9]

[17:9].

and NWS1 controls D

[3:0]

[7:4]

[x:0]

Document Number: 001-15887 Rev. *E Page 6 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Table 2. Pin Definitions (continued)

Pin Name IO Pin Description

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q

K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q

CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

(K) of the QDR-II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG.

TCK Input TCK Pin for JTAG.

TDI Input TDI Pin for JTAG.

TMS Input TMS Pin for JTAG.

NC N/A Not Connected to the Die. Can be tied to any voltage level.

Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

Input PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings

) of the QDR-II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.

impedance. CQ, CQ between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing.

[x:0]

, and Q

. All accesses are initiated on the rising edge of K.

[x:0]

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.

REF

DDQ

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

Document Number: 001-15887 Rev. *E Page 7 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Functional Overview

The CY7C2561KV18, CY7C2576KV18, CY7C2563KV18, CY7C2565KV18 are synchronous pipelined Burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II+ completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C2561KV18, four 9-bit data transfers in the case of CY7C2576KV18, four 18-bit data transfers in the case of CY7C2563KV18, and four 36-bit data transfers in the case of CY7C2565KV18, in two clock cycles.

These devices operate with a read latency of two and half cycles when DOFF connected to VSS then device behaves in QDR-I mode with a read latency of one clock cycle.

Accesses for both ports are initiated on the positive input clock (K). All synchronous input and output timing are referenced from the rising edge of the input clocks (K and K

All synchronous data inputs (D controlled by the input clocks (K and K outputs (Q by the rising edge of the input clocks (K and K) as well.

All synchronous control (RPS pass through input registers controlled by the rising edge of the input clocks (K and K

CY7C2563KV18 is described in the following sections. The same basic descriptions apply to CY7C2561KV18, CY7C2576KV18 and CY7C2565KV18.

Read Operations

The CY7C2563KV18 is organized internally as four arrays of 1M x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next two K sponding lowest order 18-bit word of data is driven onto the Q

[17:0]

quent rising edge of K, the next 18-bit data word is driven onto the Q have been driven out onto Q

0.45 ns from the rising edge of the input clock (K or K maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K

pin is tied HIGH. When DOFF pin is set LOW or

) pass through input registers

[x:0]

). All synchronous data

) outputs pass through output registers controlled

[x:0]

, WPS, NWS

[x:0]

, BWS

[x:0]

) inputs

clock rise, the corre-

using K as the output timing reference. On the subse-

. This process continues until all four 18-bit data words

[17:0]

. The requested data is valid

[17:0]

). To

clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the input clocks (K and K

When the read port is deselected, the CY7C2563KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the negative input clock (K

). This enables for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D the lower 18-bit write data register, provided BWS

is latched and stored into

[17:0]

[1:0]

are both asserted active. On the subsequent rising edge of the negative input clock (K

) the information presented to D

into the write data register, provided BWS

[1:0]

is also stored

[17:0]

are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When deselected, the write port ignores all inputs after the pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C2563KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS

, which are sampled with each set of 18-bit data words.

BWS

and

Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation.

Concurrent Transactions

The read and write ports on the CY7C2563KV18 operates completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Document Number: 001-15887 Rev. *E Page 8 of 29

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PRELIMINARY

CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18

Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations can not be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations being initiated, with the first access being a read.

Depth Expansion

The CY7C2563KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

to allow the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the QDR-II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K synchronized to the input clock of the QDR-II+. The timing for the echo clocks is shown in the Switching Characteristics on page

24.

. These are free-running clocks and are

Valid Data Indicator (QVLD)

QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

On-Die Termination (ODT)

These devices have an On-Die Termination feature for Data inputs (D and K The ODT range selection is enabled through ball R6 (ODT pin). The ODT termination tracks value of RQ where RQ is the resistor tied to the ZQ pin. ODT range selection is made during power up initialization. A LOW on this pin selects a low range that follows RQ/3.33 for 175Ω < ZQ pin). A HIGH on this pin selects a high range that follows RQ/1.66 for 175Ω < ZQ pin). When left floating, a high range termination value is selected by default. For a detailed description on the ODT implementation, refer to the application note, On-Die Termination for QDRII+/DDRII+ SRAMs.

), Byte Write Selects (BWS

[x:0]

). The termination resistors are integrated within the chip.

RQ < 350Ω (where RQ is the resistor tied to

RQ < 250Ω (where RQ is the resistor tied to

), and Input Clocks (K

[x:0]

PLL

These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 μs after a stable clock is presented. The PLL may be disabled by applying ground to the

pin. When the PLL is turned off, the device behaves in

DOFF QDR-I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+.

is tied HIGH, the PLL is locked after 20 μs

Document Number: 001-15887 Rev. *E Page 9 of 29

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Cypress CY7C2576KV18, CY7C2563KV18, CY7C2561KV18, CY7C2565KV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Configurations

Functional Description

Logic Block Diagram (CY7C2561KV18)

Logic Block Diagram (CY7C2576KV18)

Logic Block Diagram (CY7C2563KV18)

Logic Block Diagram (CY7C2565KV18)

Pin Configuration

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Concurrent Transactions

Depth Expansion

Programmable Impedance

Echo Clocks

Valid Data Indicator (QVLD)

On-Die Termination (ODT)