Cypress CY7C199 User Manual
99
CY7C199
32K x 8 Static RAM
Features
• High speed
—10 ns
•Fast t
DOE
• CMOS for optimum speed/power
• Low active power
—467 mW (max, 12 ns “L” version)
• Low standby power
—0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE
and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
provided by an a ctive LOW Chip En able (CE
Output Enable (OE
) and three-state drivers. This device has
an automatic power-down feature, reducing the power consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE
ing/reading operation o f the memory . Whe n CE
are both LOW, data on the eight data input/output pins (I/O
through I/O7) is written into the memory locati on addressed by
the address present on the address pins (A
Reading th e device is ac complished by selectin g the device
and enabling the outputs, CE
and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pi ns remain in a hig h-impedance sta te unless
the chip is selected, outputs are enabled, and Write Enable
) is HIGH. A die coat is used to improve alpha immunity.
(WE
) and active LOW
) controls the writ-
and WE inputs
through A14).
0
0
The CY7C199 is a high-perfo rmance CMO S static RAM org anized as 32, 768 word s by 8 bits . Easy mem ory expa nsion is
Logic Block Diagram
INPUT BUFFER
A
0
A
1
A
2
A
3
A
CE
WE
OE
4
A
5
A
6
A
A
A
ROW DECODER
7
8
9
1024 x 32 x 8
ARRAY
COLUMN
DECODER
11
10
A
A
DIP / SOJ / SOIC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
I/O
I/O
I/O
I/O
SENSE AMPS
I/O
I/O
POWER
DOWN
I/O
I/O
12
14
A13A
A
C199–1
A
12
0
A
13
A
14
1
I/O
0
I/O
1
2
I/O
2
GND
3
OE
A
1
4
A
2
A
3
5
A
4
WE
V
CC
6
A
5
A
6
7
A
7
A
8
A
9
A
10
A
11
Pin Configurations
Top Vi ew
V
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
22
23
24
25
26
27
28
1
2
3
4
5
6
7
CC
WE
27
A
26
4
A
25
3
24
A
2
23
A
1
22
OE
21
A
0
20
CE
19
I/O
7
18
I/O
6
17
I/O
5
16
I/O
4
15
I/O
3
C199–2
Top View
(not to scale)
A
A
A
A
A
I/O
I/O
TSOP I
A
8
A
9
10
11
12
13
14
0
1
LCC
Top Vi ew
7
A
A6A
321 27
4
5
6
7
8
9
10
11
12
1314151617
2
I/O
GND
5
CC
V
WE
28
26
A
4
25
A
3
24
A
2
23
A
1
22
OE
21
A
0
20
CE
19
I/O
18
I/O
C199–3
5
3
I/O
I/O4I/O
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Selection Guide
7C199-8 7C199-10 7C199-12 7C199-15 7C199-20 7C199-25 7C199-35 7C199-45
Maximum Access Time (ns) 81012 15 20 25 35 45
Maximum Operating
Current (mA)
L 90 90 90 90 80 70
Maximum CMOS
Standby Current (mA)
Shaded area contains advance information.
L 0.05 0.05 0.05 0.05 0.05 0.05
120 110 160 155 150 150 140 140
0.5 0.5 10 10 10 10 10 10
7
6
A
0
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
14
A
13
A
12
C199–4
7
6
5
4
3
2
1
0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05160 Rev. ** Revised September 7, 2001
CY7C199
Maximum Ratings
(Above which the useful life may be impaired. For user g uid elines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)...........................................–0.5V to +7.0V
Operating Range
Range Ambient Temperature
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Military –55°C to +125°C 5V ± 10%
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Shaded area contains advance information.
Notes:
1. V
2. T
3. See the last page of this speci ficati on for Grou p A subgroup testing information.
Output HIGH
V
Voltage
Output LOW
V
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Load
GND < VI < V
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down
Current— TTL
Inputs
Automatic CE
Power-Down
Current— CMOS
Inputs
(min.) = –2.0V for pu lse durat ions of les s than 20 ns.
IL
is the “instant o n” case temperature.
A
GND < VO < VCC,
Output Dis abl e d
VCC = Max.,
I
OUT
f = f
Max. V
CE
V
VIN < VIL, f = f
Max. V
CE > VCC – 0.3V
V
or V
[2]
V
CC
[3]
7C199-8 7C199-10 7C199-12 7C199-15
Min. Max. Min. Max. Min. Max. Min. Max. Unit
= Min., IOH=–4.0 mA 2.4 2.4 2.4 2.4 V
CC
= Min., IOL=8.0 mA 0.4 0.4 0.4 0.4 V
CC
2.2 V
–0.5 0.8 –0.5 0.8 –0.5 0.8 –0.5 0.8 V
CC
–5 +5 –5+5–5+5–5+5µA
–5 +5 –5+5–5+5–5+5µA
Com’l 120 110 160 155 mA
= 0 mA,
= 1/t
MAX
,
CC
> VIH,
> VIH or
IN
,
CC
> VCC – 0.3V
IN
< 0.3V, f = 0
IN
L
RC
Mil
Com’l 553030mA
L
MAX
Com’l
L 0.05 0.05 0.05 0.05 mA
Mil 15 mA
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[1]
................................... –0.5V to VCC + 0.5V
[1]
................................ –0.5V to VCC + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
CC
+0.3V
2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
V
85 85 100 mA
180 mA
555mA
0.5 0.5 10 10 mA
Document #: 38-05160 Rev. ** Page 2 of 16
CY7C199
Electrical Characteristics Over the Operating Range
[3]
(continued)
7C199-20 7C199-25 7C199-35 7C199-45
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
OH
OL
IH
IL
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Load
Current
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
Power-Down
Current—
TTL Inputs
I
SB2
Automatic CE
Power-Down
Current—
CMOS Inputs
]
Capacitance
[4]
V
= Min., IOH=–4.0 mA 2.4 2.4 2.4 2.4 V
CC
V
= Min., IOL=8.0 mA 0.4 0.4 0.4 0.4 V
CC
2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
2.2 V
+0.3V
CC
2.2 V
–0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V
GND < VI < V
CC
GND < VI < VCC,
–5+5–5+5–5+5 –5+5µA
–5+5–5+5–5+5 –5+5µA
Output Disabled
VCC = Max.,
= 0 mA,
I
OUT
= 1/t
f = f
MAX
Max. V
> V
V
IN
or VIN < VIL, f = f
Max. V
> VCC – 0.3V
CE
> VCC – 0.3V or
V
IN
< 0.3V , f=0
V
IN
RC
, CE > VIH,
CC
IH
,
CC
Com’l 150 150 140 140 mA
L90807070mA
Mil 170 150 150 150 mA
Com’l30 30 25 25mA
L5555mA
MAX
Com’l10 10 10 10mA
L 0.05 0.05 0.05 0.05 µA
Mil 15 15 15 15 mA
CC
+0.3V
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
Output Ca pacitance 8 pF
CC
8pF
V
Document #: 38-05160 Rev. ** Page 3 of 16
CY7C199
AC Test Loads and Waveforms
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R1 481
R2
255
Ω
[5]
5V
OUTPUT
INCLUDING
5pF
JIG AND
SCOPE
R1 481
Ω
3.0V
R2
255
C199–5
Ω
GND
(a) (b)
Equivalent to: THÉ VENIN EQUIVALENT
167Ω
OUTPUT 1.73V
Data Retention Characteristics Over the Operating Range (L version only)
Parameter Description Conditions
V
DR
I
CCDR
t
CDR
[5]
t
R
[4]
VCC for Data Retention 2.0 V
Data Retention Current Com’l VCC = VDR = 2.0V,
> VCC – 0.3V,
Com’l L 10 µA
Chip Deselect to Data Retention Time 0 ns
CE
VIN > VCC – 0.3V or
< 0.3V
V
IN
Operation Recovery Time 200 µs
ALL INPUT PULSES
10%
≤t
r
[6]
90%
Min. Max. Unit
90%
10%
≤t
r
C199–6
µA
Data Retention Waveform
V
CC
t
CDR
CE
Note:
< 3 ns for the - 12 and the -1 5 speeds. tR< 5 ns for the -20 and slower speeds
5. t
R
6. No input may exceed V
CC
+ 0.5V.
DATA RETENTION MODE
VDR> 2V
3.0V3.0V
t
R
C199–7
Document #: 38-05160 Rev. ** Page 4 of 16
CY7C199
Switching Characteristics O ver the Operating Range
[3, 7]
7C199-8 7C199-10 7C199-12 7C199-15
Min. Max. Min. Max. Min. Max. Min. Max.
UnitParameter Description
READ CYCLE
, t
Read Cycle Time 8 10 12 15 ns
Address to Data Valid 8 101215ns
Data Hold from Address Change 3 333ns
CE LOW to Data Valid 8 101215ns
OE LOW to Data Valid 4.5 5 5 7 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[8]
[8]
[8, 9]
[8,9]
0 000ns
5557ns
3 333ns
4557ns
CE LOW to Power-Up 0 000ns
CE HIGH to Power-Down 8 101215ns
[10, 11]
Write Cycle T ime 8 10 12 15 ns
CE LOW to Write End 7 7910ns
Address Set-Up to Write End 7 7910ns
Address Hold from Write End 0 000ns
Address Set-Up to Write Start 0 000ns
WE Pulse Width 7 789ns
Data Set-Up to Write End 5 589ns
Data Hold from Write End 0 000ns
WE LOW to High Z
WE HIGH to Low Z
, and t
HZCE
HZWE
are specified with CL = 5 pF as in part (b) of AC T est Loads. T ransit ion is measured ±500 mV from steady-state volt age.
[9]
[8]
3 333ns
and 30-pF load ca pacitanc e.
is less than t
HZCE
controlled, OE L OW) is the su m of t
OL/IOH
, t
LZCE
is less than t
HZOE
LOW and WE LOW. Both signals must be L OW to i nitiat e a wr ite and either signal can termin ate
5677ns
HZWE
LZOE
and tSD.
, and t
HZWE
is less than t
for any given devi ce.
LZWE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Shaded area contains advance information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
8. At any given temperature and voltage condition, t
9. t
HZOE
10. The internal write time of the memory is defined by the overlap of CE
a write by going HIG H. Th e data in put s et-up a nd hold t iming s hould be referen ced t o the rising edge of the signal that termi na tes the write.
11. The minimum write cycle time for write cycle #3 (WE
Document #: 38-05160 Rev. ** Page 5 of 16
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