f
1013
g
ax id:
CY7C185
8K x 8 Static RAM
Features
• High speed
—15 ns
• Fast t
• Low active power
• Low st andby p ow e r
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automat ic power-dow n wh en deselected
DOE
—715 mW
—220 mW
, CE2, and OE f eatures
1
provided by an active LOW chip enable (CE
chip enable (CE
three-state driv ers . This de vi ce has an automati c power -do wn
feature (CE
), and active LOW output enable (OE) and
2
or CE2), reduci ng the po wer c onsumption b y 70%
1
when deselected. Th e CY7C185 i s in a st andard 3 00-mi l-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE
ing/reading operation of the memory. When CE
puts are both LOW and CE
input/output pin s (I/O
location addressed by the address present on the address
pins (A
through A12). Reading the device is acco mplishe d by
0
0
is HIGH, data on the eight data
2
through I/O7) is written into the memory
selecting the device and enabling the outputs, CE
active LOW, CE2 active HIG H, wh ile WE rem ains in active or
HIGH. Under the se condit ions , the co ntents of the locat ion ad -
), an active HIGH
1
) controls the writ-
dressed by t he i nf ormation on a ddress p ins are pr ese nt on t he
Functional Description
The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is
eight data input/output pins.
The input/out put pins rem ain in a high- impedance s tate unle ss
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH. A die coat is used to insure alpha immunity.
Logic Block Diagram Pin Configurations
DIP/SOJ/SOIC
Top View
NC
1
A
4
A
5
A
6
A
A
A
A
I/O
I/O
I/O
GND
7
A
8
A
9
10
11
12
0
1
2
I/O
0
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
256 x 32 x 8
ARRAY
SENSE AMPS
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
and WE in-
1
and OE
1
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
C185–2
I/O
6
CE
1
CE
2
WE
OE
Selection Guide
COLUMN DECODER
[1]
0
9
10
A
A
A
A11A
POWER
DOWN
12
I/O
C185–1
7
7C185–15 7C185–20 7C185–25 7C185–35
Maximum Access Time (ns) 15 20 25 35
Maximum Operati ng Current (mA) 130 110 100 100
Maximum Standby Current (mA) 40/15 20/15 20/15 20/15
Note:
1. For military specifications, see the CY7C185A datasheet.
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Au
ust 12, 1998
CY7C185
Maximum Ratings
(Abov e which the use ful lif e ma y be impai red. F or use r guidelines, not tested.)
Storage Temperature .............................. .. .–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage t o Ground Potential. ..............–0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State
DC Input Voltage
Electrical Characteristics
[2]
............................................–0.5V to +7.0V
[2]
......................................... –0.5V to +7.0V
Over the Operating Range
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... .......... .. .......... .. ........ >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current............ .......... ........ .. .. ........ .. ........ >200 mA
Operating Range
Ambient
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Temperature
V
7C185–15 7C185–20
Parameter Description Te st Conditions Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Notes:
2. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 VCC +
0.3V
Input LOW Voltage
Input Load Current GND ≤ VI ≤ V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic
Power-Down Current
Automatic
Power-Down Current
[2]
CC
GND ≤ V
Output Disabled
[3]
VCC = Max.,
V
OUT
V
CC
I
OUT
Max. VCC, CE1 ≥ VIH or CE
Min. Duty Cycle=100%
≤ V
I
= GND
= Max.,
= 0 mA
CC
,
2 ≤ VIL
Max. VCC, CE1 ≥ VCC – 0.3V,
≤ 0.3V
or CE
2
V
≥ VCC – 0.3V or VIN ≤ 0.3V
IN
–0.5 0.8 –0.5 0.8 V
–5 +5 –5 +5
–5 +5 –5 +5
–300 –300 mA
130 110 mA
40 20
15 15
2.2 VCC +
0.3V
CC
V
µA
µA
mA
mA
2
CY7C185
Electrical Characteristics
Over the Operati ng Range (continue d)
7C185–25 7C185-35
Parameter Description Test Conditions Min. Max. Min. Max. Unit
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 VCC +
0.3V
[3]
[2]
CC
GND ≤ V
Output Disabled
I
≤ V
CC
VCC = Max.,
V
= GND
OUT
V
= Max.,
CC
I
= 0 mA
OUT
Max. VCC, CE1 ≥ VIH or CE
Min. Duty Cycle =100%
Max. VCC, CE1 ≥ VCC – 0.3V
≤ 0.3V
or CE
2
V
≥ VCC – 0.3V or VIN ≤ 0.3V
IN
–0.5 0.8 –0.5 0.8 V
–5 +5 –5 +5
,
–5 +5 –5 +5
–300 –300 mA
100 100 mA
2 ≤ VIL
20 20 mA
15 15 mA
Input LOW Voltage
Input Load Current GND ≤ VI ≤ V
Output Leakage
Current
Output Short
Circuit Current
VCC Operating
Supply Current
Automatic
Po wer-Down Current
Automatic
Po wer-Down Current
[4]
2.2 VCC +
0.3V
Parameter Desc ription Test Conditions Max. Unit
C
IN
C
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
Output Capacitance 7 pF
CC
7 pF
V
µA
µA
AC Test Loads and Waveforms
R1 481
5V
OUTPUT
30pF
INCLUDING
JIG AND
SCOPE
Equivalent to: THÉVENIN EQUIVALENT
(a) (b)
OUTPUT 1.73V
Ω
R2
255
Ω
167
OUTPUT
Ω
5V
5
pF
INCLUDING
JIGAND
SCOPE
R1 481
Ω
R2
255
C185–4
3.0V
≤
10%
5ns
Ω
GND
ALL INPUT PULSES
90%
90%
10%
≤
ns
5
C185–5
3
CY7C185
Switching Characteristics
Over the Operating Range
[5]
7C185–15 7C185–20 7C185–25 7C185–35
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
t
LZCE2
t
HZCE
t
PU
t
PD
WRIT E CYCLE
t
WC
t
SCE1
t
SCE2
t
AW
Read Cycle Time 15 20 25 35 ns
Address to Data Valid 15 20 25 35 ns
Data Hold from
3 5 5 5 ns
Address Change
CE1 LOW to Data Valid 15 20 25 35 ns
CE2 HIGH to Data Valid 15 20 25 35 ns
OE LOW to Data Valid 8 9 12 15 ns
OE LOW to Low Z 3 3 3 3 ns
[7]
[6]
7 8 10 10 ns
3 5 5 5 ns
OE HIGH to High Z
CE1 LOW to Low Z
CE2 HIGH to Low Z 3 3 3 3 ns
CE1 HIGH to High Z
[6, 7]
7 8 10 10 ns
CE2 LOW to High Z
CE1 LOW to Power-Up
CE
to HIGH to Power-Up
2
CE1 HIGH to Power-Down
CE
LOW to Power-Down
2
[8]
0 0 0 0 ns
15 20 20 20 ns
Write Cycle Time 15 20 25 35 ns
CE1 LOW to Write End 12 15 20 20 ns
CE2 HIGH to W r ite E nd 12 15 20 20 ns
Address Set-Up to
12 15 20 25 ns
Write End
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Notes:
5. Tes t conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
6. t
HZOE, tHZCE
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Address Hold from
0 0 0 0 ns
Write End
Address Set-Up to
0 0 0 0 ns
Write Start
WE Pulse Width 12 15 15 20 ns
Data Set-Up to Write End 8 10 10 12 ns
Data Hold from Write End 0 0 0 0 ns
WE LOW to High Z
[6]
7 7 7 8 ns
WE HIGH to Low Z 3 5 5 5 ns
and 30-pF load capacitance.
, and t
are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
HZWE
is less than t
HZCE
LZCE1
and t
for any given device.
LZCE2
4
Switching Waveforms
CY7C185
Read Cycle No.1
[9,10]
ADDRESS
DATA OUT PREVIOUS DATA VALID
Read Cycle No.2
CE
CE
OE
OE
DATA OUT
V
CC
SUPPLY
[11,12]
1
2
t
ACE
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
CURRENT
t
OHA
t
50%
DOE
t
RC
t
AA
DATA VALID
C185–6
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
ICC
50%
ISB
C185–7
Write Cycle No. 1 (WE Controlled)
[10,12]
t
WC
ADDRESS
t
AW
t
SCEI
t
SCE2
t
PWE
t
HA
CE
CE
CE
WE
1
2
t
SA
OE
t
SD
DATA I/O
9. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = VIH, CE1 = VIH, WE = VIL, or CE2=VIL.
12. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW . CE1 and WE must be LOW and CE2 must be HIGH
to initiate write. A write can be terminated by CE1 or WE going HIGH or CE2 going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
13. During this period, the I/Os are in the output state and input signals should not be applied.
NOTE 13
t
HZOE
DATAINVALID
t
HD
C185–8
5
CY7C185
Switching Waveforms
rite Cycle No. 2 (CE Controlled)
(continued )
[12,13,14]
ADDRESS
CE
1
t
SA
CE
2
WE
DATA I/O
Write Cycle No. 3 (WE Controlled, OE LOW)
ADDRESS
CE
1
[12,13,14,15]
t
t
AW
SCE1
t
WC
t
WC
t
SCE1
t
SCE2
t
SD
DATAINVALID
t
HA
t
HD
C185–9
t
t
AW
SCE2
t
SD
DATAINVALID
and tSD.
HZWE
CE
2
t
WE
DATA I/O
Notes:
14. The minimum write cycle time for write cycle #3 (WE
15. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
SA
NOTE 13
t
HZWE
controlled, OE LOW) is the sum of t
t
HA
t
LZWE
t
HD
C185–10
6
T y pical DC and AC Characteris ti cs
CY7C185
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
I
1.0
CC SB
CC
0.8
0.6
0.4
NORMALIZED I , I
0.2
0.0
4.0 4.5 5.0 5.5 6.0
I
SB
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY
VOLTAGE
1.4
1.3
AA
1.2
1.1
1.0
NORMALIZED t
TA=25°C
0.9
0.8
4.0 4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.2
SB
1.0
CC
0.8
0.6
0.4
NORMALIZED I , I
0.2
I
SB
0.0
–55 25 125
VCC=5.0V
V
=5.0V
IN
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.6
1.4
AA
1.2
1.0
NORMALIZED t
VCC=5.0V
0.8
0.6
–55 25 125
AMBIENT TEMPERATURE (°C)
OUTPUT SOURCE CURRENT
vs. OUTPUT
VOLTAGE
120
I
CC
100
80
V
=5.0V
60
T
CC
A
=25°C
40
20
0
OUTPUT SOURCE CURRENT (mA)
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
V
T
A
CC
=25°C
=5.0V
60
40
20
OUTPUT SINK CURRENT (mA)
0
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY
VOLTAGE
3.0
2.5
PO
2.0
1.5
1.0
NORMALIZED I
0.5
0.0
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V)
5.0
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT
LOADING
30.0
25.0
20.0
AA
15.0
DELTA t (ns)
10.0
5.0
0.0
0 200 400 600 800
V
T
CC
=25°C
A
=4.5V
CAPACITANCE (pF)
7
1000
1.25
CC
NORMALIZED I
V
=5.0V
CC
T
=25°C
A
V
=0.5V
CC
vs. CYCLE TIME
CC
1.00
0.75
NORMALIZED I
0.50
10 20 30 40
CYCLE FREQUENCY (MHz)
Truth Table
CE1CE2WE OE Input/Output Mode
H X X X High Z Deselect/Power-Down
X L X X High Z Deselect/Power-Down
L H H L Data Out Read
L H L X Data In Write
L H H H High Z Deselect
Address Designators
Address
Name
A4 X3 2
A5 X4 3
A6 X5 4
A7 X6 5
A8 X7 6
A9 Y1 7
A10 Y4 8
A11 Y3 9
A12 Y0 10
A0 Y2 21
A1 X0 23
A2 X1 24
A3 X2 25
Address
Function
Pin
Number
CY7C185
Ordering Information
Speed
(ns)
15 CY7C185–15PC P21 28-Lead (300-Mil) Mold ed DIP Commercial
20 CY7C185–20PC P21 28-Lead (300-Mi l) Molded DIP Commercial
25 CY7C185–25PC P21 28-Lead (300-Mi l) Molded DIP Commercial
35 CY7C185–35PC P21 28-Lead (300-Mi l) Molded DIP Commercial
Document #: 38–00037–K
Ordering Code
CY7C185–15SC S21 28-Lead M olded SOIC
CY7C185–15VC V21 28-Lead M olded SOJ
CY7C185–15VI V21 28-Lead M olded SOJ Industria l
CY7C185–20SC S21 28-Lead M olded SOIC
CY7C185–20VC V21 28-Lead M olded SOJ
CY7C185–20VI V21 28-Lead M olded SOJ Industria l
CY7C185–25SC S21 28-Lead M olded SOIC
CY7C185–25VC V21 28-Lead M olded SOJ
CY7C185–25VI V21 28-Lead M olded SOJ Industria l
CY7C185–35SC S21 28-Lead M olded SOIC
CY7C185–35VC V21 28-Lead M olded SOJ
CY7C185–35VI V21 28-Lead M olded SOJ Industria l
Package
Name
Pack age Type
Operating
Range
8
Package Diagrams
CY7C185
28-Lead(300-Mil) MoldedDIP P21
51-85014-B
28-Lead(300-Mil)Molded SOICS21
51-85026-A
9
CY7C185
Package Diagrams
(continued)
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any lice nse under patent or other rights. Cypress Semi conductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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