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CY7C182
8Kx9 Static RAM
Features
• High speed
= 25 ns
—t
AA
• x9 organizat ion is i deal f o r cache m emory appli cation s
• CMOS for optimum speed/power
• Low active power
—770 mW
• Low st andby p ow er
—195 mW
• TTL-compatible inputs and outputs
• Automat ic power-down when desel ected
• Easy memory expansion with CE
, CE2, OE options
1
Functional Description
The CY7C182 is a high-speed CMOS static RAM organized
as 8,192 by 9 bit s and it is man ufact ured using Cypr ess’ s highperformance CMO S technolog y . Access times as f ast as 25 ns
are available with maximum power consumption of only 770
mW.
Logic Block Diagram
The CY7C182, which is oriented toward cache mem ory appl ications, features fully static operation requiring no external
clocks or timing strobes. The automatic power-down feature
reduces the power consumption by more than 70% when the
circuit is deselected. Easy memory expansion is provided by
an active-LOW Chip Enable (CE
able (CE
state drivers.
), an active-LOW Output Enable (OE), and three-
2
An active-LOW Write Enable signal (WE
ing/reading operation of the memory. When CE
), an active HIGH Chip En-
1
) controls the writ-
and WE in-
1
puts are both LOW, data on the nine data input/output pins
(I/O
through I/O8) is written into the memory location ad-
0
dressed by the address present on the address pins (A
through A12). Reading the d evice is a ccompli shed by sel ecting
the devic e an d enab ling the output s , (CE
and CE
active HIGH), while (WE) remains inactive or HIGH.
2
and OE active L OW
1
Under these co nditions , the contents of the location addressed
by the inf ormation on addre ss pins is present on th e nine data
input/output pins.
The input/out put pins rem ain in a high- impedance s tate unless
the chip is selected, outputs are enabled, and write enable
(WE
) is HIGH.
A die coat is used to insure alpha immunity.
PinConfiguration
DIP/SOJ
Top View
0
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
A
3
A
2
A
1
OE
A
0
CE
I/O
I/O
I/O
I/O
I/O
C182–2
2
1
8
7
6
5
4
CE
CE
WE
OE
A
1
4
A
2
A
A
A
I/O
I/O
I/O
I/O
GND
5
A
3
6
A
4
7
A
5
8
A
6
9
7
10
8
11
9
12
10
0
11
1
12
2
13
3
14
I/O
0
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
1
2
ROW DECODER
256 x 32 x 9
ARRAY
COLUMN
DECODER
0
9
10
A
A
A
A11A
SENSE AMPS
POWER
DOWN
12
C182–1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
Selectio n Gu ide
7C182-25 7C182-35 7C182-45
Maximum Access Time (ns) 25 35 45
Maximum Operating Curr ent (mA) 140 140 140
Maximum Standby Current (mA) 35 35 35
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 4, 1999
CY7C182
Maximum Ratings
(Abov e which the useful life m ay be impaired. For user guidelines, not tested.)
Storage Temperature .....................................−65
Ambient Temperature with
Po wer Applied..................................................−55
[1]
Supply Voltage to Ground Potential
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[1]
.................................................−0.5V to +7.0V
[1]
..............................................−0.5V to +7.0V
Electrical Characteristics
..............−0.5V to +7.0V
Over the Operati ng Range
°
C to +150°C
°
C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......... ......................... ....... >2001V
(per MIL-STD-883, Method 3015.2)
Latch-Up Current............. ........................ .. ............. >200 mA
Operating Range
Range
Commercial 0°C to + 70°C 5V ± 10%
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
OH
OL
IH
IL
IX
OZ
OS
CC
Output H IGH Voltage VCC Min., IOH = −4.0 mA. 2.4 V
Output LOW Voltage VCC Min., IOL = 8.0 mA 0.4 V
Input HIG H Voltage 2.2 V
Input LOW Voltage
[1]
Input Load Current GND < VIN < VCC,
Output Leakage Current V
Output Short Circuit
[2]
Current
VCC Operating Circuit
Current
Auto matic Power-Down
Current — TTL Inputs
Auto matic Power-Down
Current — CMOS Inputs
GND < V
Output Disabled
= Max., V
CC
V
= Max., V
CC
VCC Max., Output Current = 0 mA,
f = Max., V
Max VCC, CE1 > VIH, CE2 < VIL,
V
> VIH or VIN < VIL, f = f
IN
Max VCC, CE1 > VCC − 0.3V, CE2 < 0.3V,
V
> VCC − 0.3V or VIN < 0.3V, f = 0
IN
< VCC,
OUT
= GND
OUT
= GND
OUT
= VCC or GND
IN
MAX
Ambient
Temperature
7C182-25, 35, 45
Min. Max. Unit
−0.5
−10
−10
V
CC
CC
0.8 V
+10
+10
−300
mA
140 mA
35 mA
20 mA
V
µA
µA
Capacitance
[3]
Parameter Description Test Conditions Max. Unit
C
OUT
C
IN
Note:
1. V
(min.) = −3.0V for pulse durations of less than 20 ns.
IL
2. Duration of the short circuit should not exceed 30 seconds. Not more than one output should be shorted at one time.
3. Tested initially and after any design or process changes that may affect these parameters.
Output Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
Input Capacitance 10 pF
CC
AC Test Loads and Waveforms
R1 481
5V
OUTPUT
INCLUDING
30pF
JIG AND
SCOPE
Ω
R2
255
OUTPUT
Ω
5V
INCLUDING
JIG AND
(a) (b)
Equivalent to: THÉ VENIN EQUIVALENT
167
OUTPUT 1.73V
Ω
SCOPE
5pF
R1 481
Ω
R2
255
C182–3
3.0V
Ω
GND
10%
<5ns
2
10 pF
ALL INPUT PULSES
90%
90%
10%
<5ns
C182–4
CY7C182
Switching Characteristics
Over the Operating Range
7C182-25 7C182-35 7C182-45
Parameter Description
and t
[4]
Read Cycle Time 25 35 45 ns
Address to Data Valid 25 35 45 ns
Data Hold from Address Change 3 3 3 ns
CE1 Access Time 25 35 45 ns
CE2 Access Time 25 35 45 ns
CE1 LOW to Low Z 5 5 5 ns
CE2 HIGH to Lo w Z 5 5 5 ns
[5]
[5]
18 20 25 ns
18 20 25
CE1 HIGH to H ig h Z
CE2 LOW to High Z
CE1 LOW to Po wer-Up 0 0 0 ns
CE1 HIGH to Power-Down 20 20 25 ns
OE Access Time 18 20 20 ns
OE LOW to Low Z 3 3 3 ns
OE HIGH to High Z
[6]
[5]
18 20 25 ns
Write Cycle Time 25 35 45 ns
Address Set-Up Time 0 0 0 ns
Address Valid to End of Write 20 30 40 ns
Data Set-Up Time 15 20 25 ns
CE1 LOW to Write End 20 30 40 ns
CE2 HIGH to Wr ite End 20 30 40 ns
WE Pulse Width 20 25 30 ns
Address Hold from End of Write 0 0 0 ns
Data Hold Time 0 0 0 ns
Write HIGH to Low Z
Write LOW to High Z
are specified with CL = 5 pF. Transition is measured ± 500 mV from steady-state voltage.
HZWE
[7]
[5, 7, 8]
LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write
1
is less than t
LZWE
transition LOW and CE2 transition HIGH.
HZWE
3 3 3 ns
for any given device. These parameters are sampled and not 100% tested.
13 15 20 ns
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE1
t
ACE2
t
LZCE1
t
LZCE2
t
HZCE1
t
HZCE2
t
PU
t
PD
t
DOE
t
LZOE
t
HZOE
WRIT E CYCL E
t
WC
t
SA
t
AW
t
SD
t
SCE1
t
SCE2
t
PWE
t
HA
t
HD
t
LZWE
t
HZWE
Notes:
4. WE
is HIGH for read cycle.
5. t
HZCE
6. The internal write time of the memory is defined by the overlap of CE
and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
7. At any given temperature and voltage condition, t
8. Address valid prior to or coincident with CE
UnitMin. Max. Min. Max. Min. Max.
3
Switching Wave forms
CY7C182
Read Cycle No. 1
[4, 9]
t
RC
ADDRESS
t
t
OHA
AA
DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No.2
CE
1
CE
2
OE
OE
DATA OUT
V
CC
SUPPLY
CURRENT
Write Cycle No.1 (WEControlled)
[4, 10]
HIGH IMPEDANCE
t
t
PU
LZCE
t
ACE1
t
ACE2
t
LZOE
t
RC
t
t
DOE
HZOE
DATA VALID
50%
[6]
t
WC
t
HZCE
C182–5
HIGH
IMPEDANCE
t
PD
ICC
50%
ISB
C182–6
ADDRESS
t
SCE1
t
CS
1
CS
2
t
WE
SA
DATA IN
DATA I/O
Notes:
9. Device is continuously selected. OE
10. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
DATA UNDEFINED
, CE1 = VIL. CE2 = V
SCE2
t
AW
t
PWE
t
SD
DATA VALID
t
HZWE
HIGH IMPEDANCE
IH.
t
HA
t
LZWE
t
HD
C182–7
4
CY7C182
Switching Wave forms
(continued)
Write Cycle No.2 (CE Controlled)
ADDRESS
CE
1
CE
2
WE
DATA IN
DATA I/O
Truth Table
[6, 10 ]
t
SA
DATA UNDEFINED
t
t
HZWE
AW
t
WC
t
SCE1
t
SCE2
t
PWE
t
SD
DATA VALID
t
HA
t
HD
HIGH IMPEDANCE
C182–8
CE
1
CE
2
OE WE Data In Data Out Mode
H X X X Z Z Deselect/Power-Down
L H L H Z Valid Read
L H X L Valid Z Write
L H H H Z Z Output Disable
X L X X Z Z Deselect
Ordering Information
Speed
(ns)
Ordering Code
25 CY7C182−25PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C182−25VC V21 28-Lead Molded SOJ
35 CY7C182−35PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C182−35VC V21 28-Lead Molded SOJ
45 CY7C182−45PC P21 28-Lead (300-Mil) Molded DIP Commercial
CY7C182−45VC V21 28-Lead Molded SOJ
Document #: 38-00110-F
Package
Name
Packag e Type
Operating
Range
5
Package Diagrams
CY7C182
28-Lead(300-Mil) MoldedDIP P21
51-85014-B
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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