Cypress CY7C1566V18, CY7C1570V18, CY7C1577V18, CY7C1568V18 User Manual
72-Mbit DDR-II+ SRAM 2-Word Burst
Architecture (2.5 Cycle Read Latency)
CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Features
Note
1. The QDR consortium specification for V
DDQ
is 1.5V + 0.1V . The Cyp ress QDR devices exceed th e QDR consort ium sp ecificatio n and ar e cap able o f support ing V
DDQ
= 1.4V to V
DD
.
Functional Description
■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)
■ 400 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces
(data transferred at 800 MHz) at 400 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Core V
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
= 1.8V ± 0.1V; IO V
DD
= 1.4V to V
DDQ
DD
[1]
Configurations
The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K
of K and K
. Each address location is associated with two 8-bit
. Read data is driven on the rising edges
words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit
words (CY7C1568V18), or 36-bit words (CY7C1570V18) that
burst sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ
, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the K or K
input clocks. All data outputs pass through output
input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
With Read Cycle Latency of 2.5 cycles:
CY7C1566V18 – 8M x 8
CY7C1577V18 – 8M x 9
CY7C1568V18 – 4M x 18
CY7C1570V18 – 2M x 36
Selection Guide
Maximum Operating Frequency 400 375 333 300 MHz
Maximum Operating Current x8 1400 1300 1200 1100 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06551 Rev. *E Revised March 11, 2008
Description 400 MHz 375 MHz 333 MHz 300 MHz Unit
x9 1400 1300 1200 1100
x18 1400 1300 1200 1100
x36 1400 1300 1200 1100
[+] Feedback [+] Feedback
CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Logic Block Diagram (CY7C1566V18)
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[7:0]
Output
Logic
Reg.
Reg.
Reg.
8
8
16
8
NWS
[1:0]
V
REF
Write Add. Decode
8
8
LD
Control
22
4M x 8 Array
4M x 8 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
8
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[8:0]
Output
Logic
Reg.
Reg.
Reg.
9
9
18
9
BWS
[0]
V
REF
Write Add. Decode
9
9
LD
Control
22
4M x 9 Array
4M x 9 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
9
Logic Block Diagram (CY7C1577V18)
Document Number: 001-06551 Rev. *E Page 2 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Logic Block Diagram (CY7C1568V18)
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[17:0]
Output
Logic
Reg.
Reg.
Reg.
18
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
18
LD
Control
21
2M x 18 Array
2M x 18 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
18
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
DQ
[35:0]
Output
Logic
Reg.
Reg.
Reg.
36
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
36
LD
Control
20
1M x 36 Array
1M x 36 Array
Write
Reg
Write
Reg
CQ
CQ
R/W
DOFF
QVLD
36
Logic Block Diagram (CY7C1570V18)
Document Number: 001-06551 Rev. *E Page 3 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Pin Configuration
Note
2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
The pin configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follow.
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1566V18 (8M x 8)
1 2 3 4 5 6 7 8 9 10 11
A CQ AAR/WNWS
1
B NC NC NC A NC/288M K NWS
C NC NC NC V
D NC NC NC V
E NC NC DQ4 V
F NC NC NC V
G NC NC DQ5 V
H DOFF V
REF
V
DDQ
V
J NC NC NC V
K NC NC NC V
L NC DQ6 NC V
M NC NC NC V
N NC NC NC V
SS
SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
SS
SS
AAAVSSNC NC NC
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
AAAVSSNC NC NC
P NC NC DQ7 A A QVLD A A NC NC NC
R TDOTCKAAANCAAATMSTDI
K NC/144M LD AACQ
0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
ANCNCDQ3
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
[2]
NC NC NC
NC NC DQ2
NC NC NC
NC NC NC
V
DDQ
V
REF
NC DQ1 NC
NC NC NC
NC NC DQ0
NC NC NC
ZQ
CY7C1577V18 (8M x 9)
1 2 3 4 5 6 7 8 9 10 11
A CQ AAR/WNC K NC/144M LD AACQ
B NC NC NC A NC/288M K BWS
C NC NC NC V
D NC NC NC V
E NC NC DQ4 V
F NC NC NC V
G NC NC DQ5 V
H DOFF V
REF
V
DDQ
V
J NC NC NC V
K NC NC NC V
L NC DQ6 NC V
M NC NC NC V
N NC NC NC V
SS
SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
SS
SS
AAAVSSNC NC NC
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
AAAVSSNC NC NC
0
ANCNCDQ3
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
SS
NC NC NC
NC NC DQ2
NC NC NC
NC NC NC
V
DDQ
V
REF
NC DQ1 NC
NC NC NC
NC NC DQ0
NC NC NC
ZQ
P NC NC DQ7 A A QVLD A A NC NC DQ8
R TDOTCKAAANCAAATMSTDI
Document Number: 001-06551 Rev. *E Page 4 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Pin Configuration (continued)
The pin configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follow.
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1568V18 (4M x 18)
1 2 3 4 5 6 7 8 9 10 11
A CQ AAR/WBWS
1
B NC DQ9 NC A NC/288M K BWS
C NC NC NC V
D NC NC DQ10 V
E NC NC DQ11 V
F NC DQ12 NC V
G NC NC DQ13 V
H DOFF V
REF
V
DDQ
V
J NC NC NC V
K NC NC DQ14 V
L NC DQ15 NC V
M NC NC NC V
N NC NC DQ16 V
SS
SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
SS
SS
ANCAVSSNC DQ7 NC
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
AAAVSSNC NC NC
P NC NC DQ17 A A QVLD A A NC NC DQ0
R TDOTCKAAANCAAATMSTDI
K NC/144M LD AACQ
0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
ANCNCDQ8
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
[2]
NC NC NC
NC NC DQ6
NC NC DQ5
NC NC NC
V
DDQ
V
REF
NC DQ4 NC
NC NC DQ3
NC NC DQ2
NC DQ1 NC
ZQ
CY7C1570V18 (2M x 36)
1 2 3 4 5 6 7 8 9 10 11
A CQ NC/144M A R/W BWS
B NC DQ27 DQ18 A BWS
C NC NC DQ28 V
D NC DQ29 DQ19 V
E NC NC DQ20 V
F NC DQ30 DQ21 V
G NC DQ31 DQ22 V
H DOFF V
REF
V
DDQ
V
J NC NC DQ32 V
K NC NC DQ23 V
L NC DQ33 DQ24 V
M NC NC DQ34 V
N NC DQ35 DQ25 V
SS
SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
SS
SS
ANCAVSSNC DQ17 DQ7
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
AAAVSSNC NC DQ10
2
3
K BWS
LD AACQ
1
KBWS0ANCNCDQ8
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
SS
SS
NC NC DQ16
NC DQ15 DQ6
NC NC DQ5
NC NC DQ14
V
DDQ
V
REF
ZQ
NC DQ13 DQ4
NC DQ12 DQ3
NC NC DQ2
NC DQ11 DQ1
P NC NC DQ26 A A QVLD A A NC DQ9 DQ0
R TDOTCKAAANCAAATMSTDI
Document Number: 001-06551 Rev. *E Page 5 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Pin Definitions
Pin Name IO Pin Description
DQ
[x:0]
Input and
Output
Synchronous
LD Input
Synchronous
NWS
,
Input
0
NWS
BWS
BWS
BWS
BWS
1
,
0
,
1
,
2
3
Synchronous
Input
Synchronous
Data Input and Output Signals. Inputs are sampled on the rising edge of K and K
clocks during valid
write operations. These pins drive out the requested data during a read operation. Valid data is driven out
on the rising edge of both the K and K
are automatically tri-stated.
Q
[x:0]
CY7C1566V18 − DQ
CY7C1577V18 − DQ
CY7C1568V18 − DQ
CY7C1570V18 − DQ
[7:0]
[8:0]
[17:0]
[35:0]
clocks during read operations. When read access is deselected,
Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read or write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
Nibble Write Select 0, 1 − Active LOW (CY7C1566V18 only). Sampled on the rising edge of the K and
clocks during write operations. Used to select the nibble that is written into the device during the current
K
portion of the write operations. Nibbles not written remain unaltered.
NWS
controls D
0
and NWS1 controls D
[3:0]
[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and does not write into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1577V18 − BWS
CY7C1568V18 − BWS0 controls D
CY7C1570V18 − BWS0 controls D
BWS
controls D
2
controls D
0
and BWS3 controls D
[26:18]
[8:0]
and BWS1 controls D
[8:0]
, BWS1 controls D
[8:0]
[35:27]
.
[17:9]
[17:9].
,
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and does not write into the device.
A Input
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (2 arrays each of 4M x 8) for CY7C1566V18, 8M x 9 (2 arrays each of 4M x 9) for CY7C1577V18,
4M x 18 (2 arrays each of 2M x 18) for CY7C1568V18, and 2M x 36 (2 arrays each of 1M x 36) for
CY7C1570V18.
R/W
Input
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when
R/W
is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD Valid Output
Valid Outp ut Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
Indicator
K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous data presented to the device and to drive
out data through Q
when in single clock mode.
[x:0]
when in single clock mode. All accesses are initiated on the rising
[x:0]
CQ Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.
CQ
Clock Output
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.
Document Number: 001-06551 Rev. *E Page 6 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Pin Definitions (continued)
Pin Name IO Pin Description
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ
between ZQ and ground. Alternatively, this pin is connected directly to V
impedance mode. This pin is not connected directly to GND or is left unconnected.
DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation is different from that listed in this datasheet. For normal operation, this pin
is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode
when the DLL is turned off. In this mode, the device is operated at a frequency of up to 167 MHz with
DDR-I timing.
TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Is tied to any voltage level.
NC/144M N/A Not Connected to the Die. Is tied to any voltage level.
NC/288M N/A Not Connected to the Die. Is tied to any voltage level.
, and Q
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
[x:0]
that enables the minimum
DDQ
V
V
V
V
REF
DD
SS
DDQ
Input
Reference
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Reference Volt age Input. Static input is used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Document Number: 001-06551 Rev. *E Page 7 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Functional Overview
The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.
Accesses are initiated on the positive input clock (K). All
synchronous input and output timing is referenced from the rising
edge of the input clocks (K and K).
All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K
synchronous data outputs (Q
controlled by the rising edge of the input clocks (K and K
All synchronous control (R/W, LD, NWS
pass through input registers controlled by the rising edge of the
input clock (K).
CY7C1568V18 is described in the following sections. The same
basic descriptions apply to CY7C1566V18, CY7C1577V18, and
CY7C1570V18.
Read Operations
The CY7C1568V18 is organized internally as two arrays of 2M x
18. Accesses are completed in a burst of 2 sequential 18-bit data
words. Read operations are initiated by asserting R/W HIGH and
LD
LOW at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven
onto the Q
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q
rising edge of the input clock (K and K
using K as the output timing reference. On the
[17:0]
. The requested data is valid 0.45 ns from the
[17:0]
logic, each read access must be allowed to complete. Read
accesses are initiated on every rising edge of the positi ve input
clock (K).
When read access is deselected, the CY7C1568V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the negative input clock (K
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D
data register, provided BWS
subsequent rising edge of the negative input clock (K
mation presented to D
register, provided BWS
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
is latched and stored into the 18-bit write
[17:0]
[17:0]
[1:0]
) pass through input registers
[x:0]
) pass through output registers
[x:0]
BWS
[x:0],
[x:0]
). All
).
) inputs
). To maintain the internal
). This enables a
are both asserted active. On the
[1:0]
), the infor-
is also stored into the write data
are both asserted active. The 36 bits
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data is transferred into the device on every rising
edge of the input clocks (K and K
).
When the write access is deselected, the device ignores all
inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1568V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS
, which are sampled with each set of 18-bit data words.
BWS
1
Asserting the appropriate Byte Write Select input during the data
and
0
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, and or write operations to a byte write
operation.
Double Date Rate Operation
The CY7C1568V18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1568V18 requires a
minimum of two No Operation (NOP) cycles during transition
from a read to a write cycle. At higher frequencies, some applications require a third NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15%, is between 175Ω and 350Ω,
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
to allow the SRAM to adjust its output
SS
with V
=1.5V. The
DDQ
Document Number: 001-06551 Rev. *E Page 8 of 28
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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18
Echo Clocks
Echo clocks are provided on the DDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is referenced with respect to K
. These are free-running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in Switching Characteristics on page 23.
Valid Data Indicator (QVLD)
QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
Application Example
Figure 1 shows two DDR-II+ used in an application.
Figure 1. Application Example
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF
pin. When the DLL is turned off, the device behaves in
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K
minimum of 30ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. During Power-up, when the
DOFF
is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.
for a
BUS
MASTER
(CPU or ASIC)
Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2
Addresses
Cycle Start
R/W
Source CLK
Source CLK
DQ
DQ
A
SRAM#1
LD R/W
ZQ
CQ/CQ
K
K
R = 250ohms
DQ
A
SRAM#2
LD R/W
ZQ
CQ/CQ
K
K
R = 250ohms
Document Number: 001-06551 Rev. *E Page 9 of 28
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