Cypress CY7C1566V18, CY7C1570V18, CY7C1577V18, CY7C1568V18 User Manual

72-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.5 Cycle Read Latency)

CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18

Features

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V . The Cyp ress QDR devices exceed th e QDR consort ium sp ecificatio n and ar e cap able o f support ing V

DDQ

= 1.4V to V

DD

.

Functional Description

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 400 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Available in 2.5 clock cycle latency

■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

= 1.8V ± 0.1V; IO V

DD

= 1.4V to V

DDQ

DD

[1]

Configurations

The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II+ architecture. The DDR-II+ consists of an
SRAM core with advanced synchronous peripheral circuitry.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K
of K and K

. Each address location is associated with two 8-bit

. Read data is driven on the rising edges

words (CY7C1566V18), 9-bit words (CY7C1577V18), 18-bit
words (CY7C1568V18), or 36-bit words (CY7C1570V18) that
burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ

, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.

All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the K or K

input clocks. All data outputs pass through output

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

With Read Cycle Latency of 2.5 cycles:

CY7C1566V18 – 8M x 8
CY7C1577V18 – 8M x 9
CY7C1568V18 – 4M x 18
CY7C1570V18 – 2M x 36

Selection Guide

Maximum Operating Frequency 400 375 333 300 MHz
Maximum Operating Current x8 1400 1300 1200 1100 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-06551 Rev. *E Revised March 11, 2008

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

x9 1400 1300 1200 1100
x18 1400 1300 1200 1100
x36 1400 1300 1200 1100

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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18

Logic Block Diagram (CY7C1566V18)

CLK

A

(21:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[7:0]

Output

Logic

Reg.

Reg.

Reg.

8

8

16

8

NWS

[1:0]

V

REF

Write Add. Decode

8

8

LD

Control

22

4M x 8 Array

4M x 8 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

8

CLK

A

(21:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[8:0]

Output

Logic

Reg.

Reg.

Reg.

9

9

18

9

BWS

[0]

V

REF

Write Add. Decode

9

9

LD

Control

22

4M x 9 Array

4M x 9 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

9

Logic Block Diagram (CY7C1577V18)

Document Number: 001-06551 Rev. *E Page 2 of 28

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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18

Logic Block Diagram (CY7C1568V18)

CLK

A

(20:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[17:0]

Output

Logic

Reg.

Reg.

Reg.

18

18

36

18

BWS

[1:0]

V

REF

Write Add. Decode

18

18

LD

Control

21

2M x 18 Array

2M x 18 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

18

CLK

A

(19:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

DQ

[35:0]

Output

Logic

Reg.

Reg.

Reg.

36

36

72

36

BWS

[3:0]

V

REF

Write Add. Decode

36

36

LD

Control

20

1M x 36 Array

1M x 36 Array

Write
Reg

Write
Reg

CQ
CQ

R/W

DOFF

QVLD

36

Logic Block Diagram (CY7C1570V18)

Document Number: 001-06551 Rev. *E Page 3 of 28

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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18

Pin Configuration

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1566V18 (8M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAR/WNWS

1

B NC NC NC A NC/288M K NWS
C NC NC NC V
D NC NC NC V
E NC NC DQ4 V
F NC NC NC V
G NC NC DQ5 V
H DOFF V

REF

V

DDQ

V

J NC NC NC V
K NC NC NC V
L NC DQ6 NC V
M NC NC NC V
N NC NC NC V

SS

SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

SS

SS

AAAVSSNC NC NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

P NC NC DQ7 A A QVLD A A NC NC NC
R TDOTCKAAANCAAATMSTDI

K NC/144M LD AACQ

0

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

ANCNCDQ3

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

[2]

NC NC NC
NC NC DQ2
NC NC NC
NC NC NC

V

DDQ

V

REF

NC DQ1 NC
NC NC NC
NC NC DQ0
NC NC NC

ZQ

CY7C1577V18 (8M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAR/WNC K NC/144M LD AACQ
B NC NC NC A NC/288M K BWS
C NC NC NC V
D NC NC NC V
E NC NC DQ4 V
F NC NC NC V
G NC NC DQ5 V
H DOFF V

REF

V

DDQ

V

J NC NC NC V
K NC NC NC V
L NC DQ6 NC V
M NC NC NC V
N NC NC NC V

SS

SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

SS

SS

AAAVSSNC NC NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

0

ANCNCDQ3

V
V
V
V
V
V
V

V

DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

V

SS

SS

NC NC NC
NC NC DQ2
NC NC NC
NC NC NC

V

DDQ

V

REF

NC DQ1 NC
NC NC NC
NC NC DQ0
NC NC NC

ZQ

P NC NC DQ7 A A QVLD A A NC NC DQ8
R TDOTCKAAANCAAATMSTDI

Document Number: 001-06551 Rev. *E Page 4 of 28

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CY7C1566V18, CY7C1577V18
CY7C1568V18, CY7C1570V18

Pin Configuration (continued)

The pin configuration for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1568V18 (4M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAR/WBWS

1

B NC DQ9 NC A NC/288M K BWS
C NC NC NC V
D NC NC DQ10 V
E NC NC DQ11 V
F NC DQ12 NC V
G NC NC DQ13 V
H DOFF V

REF

V

DDQ

V

J NC NC NC V
K NC NC DQ14 V
L NC DQ15 NC V
M NC NC NC V
N NC NC DQ16 V

SS

SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

SS

SS

ANCAVSSNC DQ7 NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

P NC NC DQ17 A A QVLD A A NC NC DQ0
R TDOTCKAAANCAAATMSTDI

K NC/144M LD AACQ

0

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

ANCNCDQ8

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

[2]

NC NC NC
NC NC DQ6
NC NC DQ5
NC NC NC

V

DDQ

V

REF

NC DQ4 NC
NC NC DQ3
NC NC DQ2
NC DQ1 NC

ZQ

CY7C1570V18 (2M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A R/W BWS
B NC DQ27 DQ18 A BWS
C NC NC DQ28 V
D NC DQ29 DQ19 V
E NC NC DQ20 V
F NC DQ30 DQ21 V
G NC DQ31 DQ22 V
H DOFF V

REF

V

DDQ

V

J NC NC DQ32 V
K NC NC DQ23 V
L NC DQ33 DQ24 V
M NC NC DQ34 V
N NC DQ35 DQ25 V

SS

SS
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

SS

SS

ANCAVSSNC DQ17 DQ7

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC DQ10

2
3

K BWS

LD AACQ

1

KBWS0ANCNCDQ8

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V
V
V
V
V
V
V

V

DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ

V

SS

SS

NC NC DQ16
NC DQ15 DQ6
NC NC DQ5
NC NC DQ14

V

DDQ

V

REF

ZQ
NC DQ13 DQ4
NC DQ12 DQ3
NC NC DQ2
NC DQ11 DQ1

P NC NC DQ26 A A QVLD A A NC DQ9 DQ0
R TDOTCKAAANCAAATMSTDI

Document Number: 001-06551 Rev. *E Page 5 of 28

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CY7C1568V18, CY7C1570V18

Pin Definitions

Pin Name IO Pin Description

DQ

[x:0]

Input and

Output

Synchronous

LD Input

Synchronous

NWS

,

Input

0

NWS

BWS
BWS
BWS
BWS

1

,

0

,

1

,

2
3

Synchronous

Input

Synchronous

Data Input and Output Signals. Inputs are sampled on the rising edge of K and K

clocks during valid
write operations. These pins drive out the requested data during a read operation. Valid data is driven out
on the rising edge of both the K and K

are automatically tri-stated.

Q

[x:0]

CY7C1566V18 − DQ
CY7C1577V18 − DQ
CY7C1568V18 − DQ
CY7C1570V18 − DQ

[7:0]
[8:0]
[17:0]
[35:0]

clocks during read operations. When read access is deselected,

Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read or write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.

Nibble Write Select 0, 1 − Active LOW (CY7C1566V18 only). Sampled on the rising edge of the K and

clocks during write operations. Used to select the nibble that is written into the device during the current

K
portion of the write operations. Nibbles not written remain unaltered.
NWS

controls D

0

and NWS1 controls D

[3:0]

[7:4]

.

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and does not write into the device.

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1577V18 − BWS
CY7C1568V18 − BWS0 controls D
CY7C1570V18 − BWS0 controls D
BWS

controls D

2

controls D

0

and BWS3 controls D

[26:18]

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[35:27]

.

[17:9]

[17:9].

,

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and does not write into the device.

A Input

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
8M x 8 (2 arrays each of 4M x 8) for CY7C1566V18, 8M x 9 (2 arrays each of 4M x 9) for CY7C1577V18,
4M x 18 (2 arrays each of 2M x 18) for CY7C1568V18, and 2M x 36 (2 arrays each of 1M x 36) for
CY7C1570V18.

R/W

Input

Synchronous

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when
R/W

is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

QVLD Valid Output

Valid Outp ut Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.

Indicator

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q
edge of K.

K

Input Clock Negative Input Clock Input. K is used to capture synchronous data presented to the device and to drive

out data through Q

when in single clock mode.

[x:0]

when in single clock mode. All accesses are initiated on the rising

[x:0]

CQ Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock

(K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.

CQ

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.

Document Number: 001-06551 Rev. *E Page 6 of 28

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CY7C1568V18, CY7C1570V18

Pin Definitions (continued)

Pin Name IO Pin Description

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. CQ, CQ
between ZQ and ground. Alternatively, this pin is connected directly to V
impedance mode. This pin is not connected directly to GND or is left unconnected.

DOFF Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing

in the DLL turned off operation is different from that listed in this datasheet. For normal operation, this pin
is connected to a pull up through a 10 Kohm or less pull up resistor. The device behaves in DDR-I mode
when the DLL is turned off. In this mode, the device is operated at a frequency of up to 167 MHz with
DDR-I timing.

TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
TMS Input TMS Pin for JTAG.
NC N/A Not Connected to the Die. Is tied to any voltage level.
NC/144M N/A Not Connected to the Die. Is tied to any voltage level.
NC/288M N/A Not Connected to the Die. Is tied to any voltage level.

, and Q

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

that enables the minimum

DDQ

V

V
V
V

REF

DD

SS

DDQ

Input

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

Reference Volt age Input. Static input is used to set the reference level for HSTL inputs, outputs, and AC
measurement points.

Document Number: 001-06551 Rev. *E Page 7 of 28

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CY7C1568V18, CY7C1570V18

Functional Overview

The CY7C1566V18, CY7C1577V18, CY7C1568V18, and
CY7C1570V18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface.

Accesses are initiated on the positive input clock (K). All
synchronous input and output timing is referenced from the rising
edge of the input clocks (K and K).

All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K
synchronous data outputs (Q
controlled by the rising edge of the input clocks (K and K

All synchronous control (R/W, LD, NWS
pass through input registers controlled by the rising edge of the
input clock (K).

CY7C1568V18 is described in the following sections. The same
basic descriptions apply to CY7C1566V18, CY7C1577V18, and
CY7C1570V18.

Read Operations

The CY7C1568V18 is organized internally as two arrays of 2M x

18. Accesses are completed in a burst of 2 sequential 18-bit data
words. Read operations are initiated by asserting R/W HIGH and
LD

LOW at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the corre­sponding 18-bit word of data from this address location is driven
onto the Q
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q
rising edge of the input clock (K and K

using K as the output timing reference. On the

[17:0]

. The requested data is valid 0.45 ns from the

[17:0]

logic, each read access must be allowed to complete. Read
accesses are initiated on every rising edge of the positi ve input
clock (K).

When read access is deselected, the CY7C1568V18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the output following the next
rising edge of the negative input clock (K
seamless transition between devices without the insertion of wait
states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register. On the following K clock rise, the data
presented to D
data register, provided BWS
subsequent rising edge of the negative input clock (K
mation presented to D
register, provided BWS
of data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of

is latched and stored into the 18-bit write

[17:0]

[17:0]

[1:0]

) pass through input registers

[x:0]

) pass through output registers

[x:0]

BWS

[x:0],

[x:0]

). All

).

) inputs

). To maintain the internal

). This enables a

are both asserted active. On the

[1:0]

), the infor-

is also stored into the write data

are both asserted active. The 36 bits

the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data is transferred into the device on every rising
edge of the input clocks (K and K

).

When the write access is deselected, the device ignores all
inputs after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C1568V18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS

, which are sampled with each set of 18-bit data words.

BWS

1

Asserting the appropriate Byte Write Select input during the data

and

0

portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, and or write operations to a byte write
operation.

Double Date Rate Operation

The CY7C1568V18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1568V18 requires a
minimum of two No Operation (NOP) cycles during transition
from a read to a write cycle. At higher frequencies, some appli­cations require a third NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information is stored because
the SRAM cannot perform the last word write to the array without
conflicting with the read. The data stays in this register until the
next write cycle occurs. On the first write cycle after the read(s),
the stored data from the earlier write is written into the SRAM
array. This is called a Posted write.

If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15%, is between 175Ω and 350Ω,
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.

to allow the SRAM to adjust its output

SS

with V

=1.5V. The

DDQ

Document Number: 001-06551 Rev. *E Page 8 of 28

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CY7C1568V18, CY7C1570V18

Echo Clocks

Echo clocks are provided on the DDR-II+ to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II+. CQ is referenced with respect to K and CQ is refer­enced with respect to K

. These are free-running clocks and are
synchronized to the input clock of the DDR-II+. The timing for the
echo clocks is shown in Switching Characteristics on page 23.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR-II+ to simplify data capture on high
speed systems. The QVLD is generated by the DDR-II+ device
along with data output. This signal is also edge aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

DLL

These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF

pin. When the DLL is turned off, the device behaves in
DDR-I mode (with 1.0 cycle latency and a longer access time).
For more information, refer to the application note, “DLL Consid­erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be
reset by slowing or stopping the input clocks K and K
minimum of 30ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. During Power-up, when the
DOFF

is tied HIGH, the DLL gets locked after 2048 cycles of
stable clock.

for a

BUS

MASTER

(CPU or ASIC)

Echo Clock1/Echo Clock1
Echo Clock2/Echo Clock2

Addresses

Cycle Start

R/W
Source CLK
Source CLK

DQ

DQ
A

SRAM#1

LD R/W

ZQ

CQ/CQ

K

K

R = 250ohms

DQ
A

SRAM#2

LD R/W

ZQ

CQ/CQ

K

K

R = 250ohms

Document Number: 001-06551 Rev. *E Page 9 of 28

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Truth Table

Notes

3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

4. Device powers up deselected with the outputs in a tri-state condition.

5. “A” represents address location latched by the devices when transaction was init iated. A + 1 represents the address sequence in the burst.

6. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

7. Data inputs are registered at K and K

rising edges. Data outputs are delivered on K and K rising edges.

8. Cypress recommends that K = K

= HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging

symmetrically.

9. Is based on a write cycle is initiated per the Write Cycle Descriptions table. NWS

0

, NWS1, BWS0, BWS1, BWS2, and BWS3 are altered on different portions of a write

cycle, as long as the setup and hold requirements are met.

The truth table for CY7C1566V18, CY7C1577V18, CY7C1568V18, and CY7C1570V18 follows.

Operation K LD R/W DQ DQ

Write Cycle:

L-H L L D(A) at K(t + 1) ↑ D(A+1) at K
Load address; wait one cycle;
input write data on consecutive K and K

Read Cycle: (2.5 cycle Latency)

rising edges.

L-H L H Q(A) at K(t + 2) ↑ Q(A+1) at K(t + 3) ↑
Load address; wait two and half cycle;
read data on consecutive K and K

rising edges.
NOP: No Operation L-H H X High Z High Z
Standby: Clock Stopped Stopped X X Previous State Previous State

[3, 4, 5, 6, 7, 8]

Write Cycle Descriptions

The write cycle description table for CY7C1566V18 and CY7C1568V18 follows.

[3, 9]

(t + 1) ↑

BWS0/

NWS

0

BWS1/

NWS

K

1

K

Comments

L L L–H – During the data portion of a write sequence:

CY7C1566V18 − both nibbles (D
CY7C1568V18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence:

CY7C1566V18 − both nibbles (D
CY7C1568V18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence:

CY7C1566V18 − only the lower nibble (D
CY7C1568V18 − only the lower byte (D

) is written into the device, D

[3:0]

) is written into the device, D

[8:0]

L H – L–H During the data portion of a write sequence:

CY7C1566V18 − only the lower nibble (D
CY7C1568V18 − only the lower byte (D

) is written into the device, D

[3:0]

) is written into the device, D

[8:0]

H L L–H – During the data portion of a write sequence:

CY7C1566V18 − only the upper nibble (D
CY7C1568V18 − only the upper byte (D

) is written into the device, D

[7:4]

) is written into the device, D

[17:9]

H L – L–H During the data portion of a write sequence:

CY7C1566V18 − only the upper nibble (D
CY7C1568V18 − only the upper byte (D

) is written into the device, D

[7:4]

) is written into the device, D

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

Document Number: 001-06551 Rev. *E Page 10 of 28

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Write Cycle Descriptions

The write cycle description table for CY7C1577V18 follows.

[3, 9]

BWS

L L–H – During the data portion of a write sequence, the single byte (D
L – L–H During the data portion of a write sequence, the single byte (D

K K Comments

0

) is written into the device.

[8:0]

) is written into the device.

[8:0]

H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1570V18 follows.

BWS0BWS1BWS2BWS3K K Comments

LLLLL–H–During the data portion of a write sequence, all four bytes (D

the device.

LLLL–L–HDuring the data portion of a write sequence, all four bytes (D

the device.

L H H H L–H – During the data portion of a write sequence, only the lower byte (D

into the device. D

L H H H – L–H During the data portion of a write sequence, only the lower byte (D

into the device. D

H L H H L–H – During the data portion of a write sequence, only the byte (D

the device. D

H L H H – L–H During the data portion of a write sequence, only the byte (D

the device. D

H H L H L–H – During the data portion of a write sequence, only the byte (D

the device. D

H H L H – L–H During the data portion of a write sequence, only the byte (D

the device. D

H H H L L–H – During the data portion of a write sequence, only the byte (D

the device. D

H H H L – L–H During the data portion of a write sequence, only the byte (D

the device. D
HHHHL–H–No data is written into the device during this portion of a write operation.
HHHH–L–HNo data is written into the device during this portion of a write operation.

[3, 9]

remains unaltered.

[35:9]

remains unaltered.

[35:9]

and D

[8:0]

[8:0]

[17:0]

[17:0]

[26:0]

[26:0]

[35:18]

and D

[35:18]

and D

[35:27]

and D

[35:27]

remains unaltered.

remains unaltered.

remain unaltered.

remain unaltered.

remain unaltered.

remain unaltered.

[35:0]

[35:0]

[17:9]

[17:9]

[26:18]

[26:18]

[35:27]

[35:27]

) are written into

) are written into

) is written

[8:0]

) is written

[8:0]

) is written into

) is written into

) is written into

) is written into

) is written into

) is written into

Document Number: 001-06551 Rev. *E Page 11 of 28

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA p ackage. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter­nally pulled up and may be unconnected. They may alternatively
be connected to V
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up inter­nally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State

Diagram on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from th e
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of th e
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.

through a pull up resistor. TDO must be left

DD

Instruction Register

Three-bit instructions can be serially loaded into the instructi on
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register i s loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.

When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.

Bypass Register

To save time when seri ally shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (V
the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of th e input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.

The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.

The Boundary Scan Order on page 18 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.

SS

) when

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction

Codes on page 17. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions
are described in this section in detail.

Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller must be
moved into the Update-IR state.

Document Number: 001-06551 Rev. *E Page 12 of 28

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IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK

Once the data is captured, it is possible to shift out the data by
putting the T AP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.

PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.

and tCH). The SRAM clock input might not be captured

CS

captured in the boundary scan register.

The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRI-ST ATE

IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set HIGH to enable
the output when the device is powered up, and also when the
T AP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document Number: 001-06551 Rev. *E Page 13 of 28

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TAP Controller State Diagram

TEST-LOGIC
RESET

TEST-LOGIC/
IDLE

SELECT
DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDA TE-DR

1

0

1

1

0

1

0

1

0

0

0

1

1

1

0

1

0

1

0

0

0

1

0

1

1

0

1

0

0

1

1

0

SELECT
IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDA TE-IR

Note

10.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

The state diagram for the TAP controller follows.

[10]

Document Number: 001-06551 Rev. *E Page 14 of 28

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TAP Controller Block Diagram

0

012..29

3031

Boundary Scan Register

Identification Register

012..

.

.108

012

Instruction Register

Bypass Register

Selection
Circuitry

Selection
Circuitry

TA P Controller

TDI

TDO

TCK
TMS

Notes

11.These characteristics apply to the TAP inputs (TMS, TCK, TDI, and TDO). Parallel load levels are specified in Electrical Characteristics on page 20.

12.Test conditions are specified using the load in TAP AC Test Conditions. t

R/tF

= 1 ns.

13.All voltage refers to ground.

TAP Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

Output HIGH Voltage I
Output HIGH Voltage I
Output LOW Voltage IOL = 2.0 mA 0.4 V
Output LOW Voltage IOL = 100 μA0.2V
Input HIGH Voltage 0.65VDDV
Input LOW Voltage –0.3 0.35V
Input and Output Load Current GND ≤ VI ≤ V

[11, 12, 13]

= −2.0 mA 1.4 V

OH

= −100 μA1.6 V

OH

+ 0.3 V

DD

–5 5 μA

DD

DD

V

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TAP AC Switching Characteristics

t

TL

t

TH

(a)

TDO

C

L

= 20 pF

Z

0

= 50

Ω

GND

0.9V

50

Ω

1.8V

0V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In
TDI

Test Data Out

t

TCYC

t

TMSH

t

TMSS

t

TDIS

t

TDIH

t

TDOV

t

TDOX

TDO

Note

14.t

CS

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

Over the Operating Range

[12, 14]

Parameter Description Min Max Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH 20 ns
TCK Clock LOW 20 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns
TDI Setup to TCK Clock Rise 5 ns
Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns

TAP Timing and Test Conditions

Figure 2. TAP Timing and Test Conditions

[12]

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Identification Register Definitions

Instruction Field

Revision Number
(31:29)

Cypress Device ID
(28:12)

Cypress JEDEC ID
(11:1)

ID Register
Presence (0)

CY7C1566V18 CY7C1577V18 CY7C1568V18 CY7C1570V18

000 000 000 000 Version number.

11010111000000100 11010111000001100 11010111000010100 11010111000100100 Defines the type of

00000110100 00000110100 00000110100 00000110100 Allows unique

1111Indicates the

Value

Description

SRAM.

identification of
SRAM vendor.

presence of an ID
register.

Scan Register Sizes

Register Name Bit Size

Instruction 3
Bypass 1
ID 32
Boundary Scan 109

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI

RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

and TDO. Does not affect the SRAM operation.

operation.

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Boundary Scan Order

Bit Number Bump ID Bit Number Bump ID Bit Number Bump ID Bit Number Bump ID

0 6R 28 10G 56 6A 84 1J
16P299G575B852J
2 6N 30 11F 58 5A 86 3K
3 7P 31 11G 59 4A 87 3J
47N329F605C882K
5 7R 33 10F 61 4B 89 1K
6 8R 34 11E 62 3A 90 2L
7 8P 35 10E 63 2A 91 3L
8 9R 36 10D 64 1A 92 1M

9 11P 37 9E 65 2B 93 1L
10 10P 38 10C 66 3B 94 3N
11 10N 39 11D 67 1C 95 3M
12 9P 40 9C 68 1B 96 1N
13 10M 41 9D 69 3D 97 2M
14 11N 42 11B 70 3C 98 3P
15 9M 43 11C 71 1D 99 2N
16 9N 44 9B 72 2C 100 2P
17 11L 45 10B 73 3E 101 1P
18 11M 46 11A 74 2D 102 3R
19 9L 47 10A 75 2E 103 4R
20 10L 48 9A 76 1E 104 4P
21 11K 49 8B 77 2F 105 5P
22 10K 50 7C 78 3F 106 5N
23 9J 51 6C 79 1G 107 5R
24 9K 52 8A 80 1F 108 Internal
25 10J 53 7A 81 3G
26 11J 54 7B 82 2G
27 11H 55 6B 83 1H

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Power Up Sequence in DDR-II+ SRAM

~

~

DDR-II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
power up, when the DOFF is tied HIGH, the DLL is locked after
2048 cycles of stable clock.

Power Up Sequence

■ Apply power with DOFF tied HIGH (All other inputs can be

HIGH or LOW)

❐ Apply V
❐ Apply V

■ Provide stable power and clock (K, K) for 2048 cycles to lock

the DLL.

before V

DD
DDQ

before V

DDQ

or at the same time as V

REF

REF

Power Up Waveforms

Figure 3. Power Up Waveforms

K

K

Unstable Clock > 2048 Stable Clock

Clock Start (Clock Starts after VDD/V

DLL Constraints

■ DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

■ The DLL functions at frequencies down to 120 MHz.

■ If the input clock is unstable and the DLL is enabled, then the

DLL may lock on to an incorrect frequency, causing unstable
SRAM behavior. T o avoid this, provide 2048 cycles stable clock
to relock to the desired clock frequency.

KC Var

.

~

~

Start Normal
Operation

is Stable)

DDQ

VDD/V

DDQ

DOFF

VDD/V

DDQ

Fix HIGH (tie to V

Stable (< + 0.1V DC per 50 ns)

)

DDQ

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Maximum Ratings

Notes

15.Overshoot: V

IH

(AC) < V

DDQ

+ 0.3V (pulse width less than t

CYC

/2). Undershoot: VIL(AC) > − 0.3V (pulse width less than t

CYC

/2).

16.Power up: assumes a linear ramp from 0V to V

DD

(min) within 200 ms. During this time V

IH

< V

DD

and V

DDQ

< VDD.

17.Outputs are impedance controlled. I

OH

= –(V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18.Outputs are impedance controlled. I

OL

= (V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

19.V

REF

(min) = 0.68V or 0.46V

DDQ

, whichever is larger. V

REF

(max) = 0.95V or 0.54V

DDQ

, whichever is smaller.

20.The operation current is calculated with 50% read cycle and 50% write cycle.

Exceeding maximum ratings may impair the useful life of th e
device. These user guidelines are not tested.

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with Power Applied..–55°C to +125°C

Supply Voltage on VDD Relative to GND........–0.5V to +2.9V

Supply Voltage on V

DC Applied to Outputs in High-Z ........ –0.5V to V

DC Input Voltage

Relative to GND.......–0.5V to +V

DDQ

[15]

..............................–0.5V to VDD + 0.3V

DDQ

DD

+ 0.3V

Current into Outputs (LOW) ........................................20 mA

Static Discharge Voltage (MIL-STD-88 3, M. 3015)... >2001V

Latch up Current............................................... ...... >200 mA

Operating Range

Range

Ambient

Temperature (TA)

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to
Industrial –40°C to +85°C

[16]

V

DD

V

DDQ

V

DD

[16]

Electrical Characteristics

Over the Operating Range

[13]

DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

I

X

I

OZ

V

REF

[20]

I

DD

Power Supply Voltage 1.7 1.8 1.9 V
IO Supply Voltage 1.4 1.5 V
Output HIGH Voltage Note 17 V
Output LOW Voltage Note 18 V
Output HIGH Voltage IOH = –0.1 mA, Nominal Impedance V
Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V
Input HIGH Voltage V

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

SS

+ 0.1 V

REF

Input LOW Voltage –0.15 V
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V
Input Reference Voltage
VDD Operating Supply V

[19]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max,

DD

I

= 0 mA,

OUT

MAX

= 1/t

f = f

DDQ

Output Disabled –2 2 μA

DDQ,

400MHz (x8) 1400 mA

(x9) 1400

CYC

(x18) 1400

–2 2 μA

DD

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V
+ 0.15 V

DDQ

– 0.1 V

REF

(x36) 1400

375MHz (x8) 1300 mA

(x9) 1300
(x18) 1300
(x36) 1300

333MHz (x8) 1200 mA

(x9) 1200
(x18) 1200
(x36) 1200

300MHz (x8) 1100 mA

(x9) 1100
(x18) 1100
(x36) 1100

V

V

Document Number: 001-06551 Rev. *E Page 20 of 28

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Electrical Characteristics

Over the Operating Range

[13]

DC Electrical Characteristics

Parameter Description Test Conditions Min Typ Max Unit

I

SB1

Automatic Power down
Current

Max VDD,
Both Ports Deselected,
V

≥ VIH or VIN ≤ VIL

IN

MAX

= 1/t

CYC,

f = f
Inputs Static

400MHz (x8) 550 mA

(x9) 550
(x18) 550
(x36) 550

375MHz (x8) 525 mA

(x9) 525
(x18) 525
(x36) 525

333MHz (x8) 500 mA

(x9) 500
(x18) 500
(x36) 500

300MHz (x8) 450 mA

(x9) 450
(x18) 450
(x36) 450

AC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

V

IH

V

IL

Input HIGH Voltage V
Input LOW Voltage –0.24 – V

[15]

+ 0.2 – V

REF

+ 0.24 V

DDQ

– 0.2 V

REF

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions Max Unit

C

Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, V

IN

C

CLK

C

O

Clock Input Capacitance 8.5 pF
Output Capacitance 8pF

= 1.5V 5.5 pF

DDQ

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Θ

Θ

Thermal Resistance

JA

(Junction to Ambient)
Thermal Resistance

JC

(Junction to Case)

Test conditions fo llow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.

165 FBGA

Package

11.82 °C/W

2.33 °C/W

Unit

Document Number: 001-06551 Rev. *E Page 21 of 28

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AC Test Loads and Waveforms

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

R

L

= 50Ω

Z

0

= 50Ω

V

REF

= 0.75V

V

REF

= 0.75V

[21]

0.75V

Under
Test

0.75V

Device
Under
Test

OUTPUT

0.75V

V

REF

V

REF

OUTPUT

ZQ

ZQ

(a)

Slew Rate = 2 V/ns

RQ =
250

Ω

(b)

RQ =
250

Ω

Note

21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V

REF

= 0.75V, RQ = 250Ω, V

DDQ

= 1.5V, input pulse

levels of 0.25V to 1.25V, output loading of the specified I

OL/IOH

, and load capacitance shown in (a) of AC Test Loads and Waveforms.

Figure 4. AC Test Loads and Waveforms

Document Number: 001-06551 Rev. *E Page 22 of 28

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Switching Characteristics

Notes

22.When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timin gs of the frequency range in which it is operated
and outputs data with the output timings of that fre quency range.

23.This part has a voltage regulator internally; t

POWER

is the time that the power is supplied above V

DD

minimum initially before a read or write operation is initiated.

24.These parameters are extrapolated from the input timing parameters (t

KHKH

- 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (t

KC Var

) is already

included in the t

KHKH

). These parameters are only guaranteed by design and are not tested in production

25.t

CHZ

, t

CLZ

, are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms” on page22. Transition is measured ±100 mV from steady state

voltage.

26.At any given voltage and temperature, t

CHZ

is less than t

CLZ

and t

CHZ

less than tCO.

27.t

QVLD

specification is applicable for both rising and falling edges of QVLD signal.

28.Hold to >V

IH

or <VIL.

Over the Operating Range

Cypress

Parameter

t

POWER

t

CYC

t

KH

t

KL

t

KHKH

Consortium

Parameter

t

KHKH

t

KHKL

t

KLKH

t

KHKH

Setup Times

t

SA

t

SC

t

SCDDRtIVKH

t

SD

t

AVKH

t

IVKH

t

DVKH

Hold Times

t

HA

t

HC

t

HCDDRtKHIX

t

HD

t

KHAX

t

KHIX

t

KHDX

Output Times

t

CO

t

DOH

t

CCQO

t

CQOH

t

CQD

t

CQDOHtCQHQX

t

CQH

t

CQHCQHtCQHCQH

t

CHZ

t

CLZ

t

QVLD

t

CHQV

t

CHQX

t

CHCQV

t

CHCQX

t

CQHQV

t

CQHCQL

t

CHQZ

t

CHQX1

t

QVLD

DLL Timing

t

KC Var

t

KC lock

t

KC ResettKC Reset

t

KC Var

t

KC lock

[21, 22]

VDD(Typical) to the First Access
K Clock Cycle Time 2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns
Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 – 0.4 – t
Input Clock (K/K) LOW 0.4 – 0.4 – 0.4 – 0.4 – t
K Clock Rise to K Clock Rise

(rising edge to rising edge)

Address Setup to K Clock Rise 0.4 – 0.4 – 0 .4 – 0.4 – ns
Control Setup to K Clock Rise (LD, R/W) 0.4 – 0.4 – 0.4 – 0.4 – ns
Double Data Rate Control Setup to Clock (K/K)

Rise (BWS
D

Setup to Clock (K/K) Rise 0.28–0.28–0.28–0.28– ns

[X:0]

Address Hold after K Clock Rise
Control Hold after K Clock Rise (LD, R/W)
Double Data Rate Control Hold after Clock (K/K)

Rise (BWS
D

Hold after Clock (K/K) Rise 0.28 – 0.28 – 0.28 – 0.28 – ns

[X:0]

K/K Clock Rise to Data Valid –0.45–0.45–0.45–0.45ns
Data Output Hold after K/K Clock Rise

(Active to Active)
K/K Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 ns
Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – ns
Echo Clock High to Data Valid – 0.2 – 0.2 – 0.2 – 0.2 ns
Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – –0.2 – ns
Output Clock (CQ/CQ) HIGH
CQ Clock Rise to CQ Clock Rise

(rising edge to rising edge)
Clock (K/K) Rise to High-Z (Active to High Z)
Clock (K/K) Rise to Low-Z
Echo Clock High to QVLD Valid

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns
DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – Cycles
K Static to DLL Reset

Description

, BWS1, BWS2, BWS3)

0

, BWS1, BWS2, BWS3)

0

[24]

[25, 26]

[28]

[23]

[27]

[24]

400 MHz 375 MHz 333 MHz 300 MHz

Min Max Min Max Min Max Min Max

1–1–1–1–ms

1.06 – 1.13 – 1.28 – 1.40 – ns

0.28 – 0.28 – 0.28 – 0.28 – ns

0.4 – 0.4 – 0.4 – 0.4 – ns

0.4 – 0.4 – 0.4 – 0.4 – ns

0.28 – 0.28 – 0.28 – 0.28 – ns

–0.45 – –0.45 – –0.45 – –0.45 – ns

0.81 – 0.88 – 1.03 – 1.15 – ns

0.81 – 0.88 – 1.03 – 1.15 – ns

[25, 26]

– 0.45 – 0.45 – 0.45 – 0.45 ns
–0.45 – –0.45 – –0.45 – –0.45 – ns
–0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns

30–30–30–30– ns

Unit

CYC
CYC

Document Number: 001-06551 Rev. *E Page 23 of 28

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Switching Waveforms

1

2

3

4

5

6

7

89

10

READ

READ

NOP WRITEWRITE

t

NOP

11

LD

R/W

A

t

KH

t

KL

t

CYC

t

HC

t

SA

t

HA

DON’T CARE

UNDEFINED

SC

A0

A1

A2

A3

A4

CQ

CQ

K

QVLD

t

NOP

NOP

DQ

K

t

CCQO

t

CQOH

t

CCQO

t

CQOH

QVLD

t

QVLD

t

QVLD

t

KHKH

12

READ

(Read Latency = 2.5 Cycles)

NOP

NOP

t

CLZ

t

CHZ

CQDOH

Q00

Q11

Q01

Q10

t

DOH

t

CO

Q40

t

SD

HD

t

SD

t

HD

D20

D21

D30 D31

t

t

CQD

t

t

CQH

t

CQHCQH

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

30.Outputs are disabled (High Z) one clock cycle after a NOP.

31.In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded imme diately as read resu lts. This note applies to t he whole diagram.

Read/Write/Deselect Sequence

[29, 30, 31]

Figure 5. Waveform for 2.5 Cycle Read Latency

Document Number: 001-06551 Rev. *E Page 24 of 28

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Ordering Information

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
visit www.cypress.com for actual products offered.

Speed

(MHz)

400 CY7C1566V18-400BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1577V18-400BZC
CY7C1568V18-400BZC
CY7C1570V18-400BZC
CY7C1566V18-400BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-400BZXC
CY7C1568V18-400BZXC
CY7C1570V18-400BZXC
CY7C1566V18-400BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1577V18-400BZI
CY7C1568V18-400BZI
CY7C1570V18-400BZI
CY7C1566V18-400BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-400BZXI
CY7C1568V18-400BZXI
CY7C1570V18-400BZXI

375 CY7C1566V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1577V18-375BZC
CY7C1568V18-375BZC
CY7C1570V18-375BZC
CY7C1566V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-375BZXC
CY7C1568V18-375BZXC
CY7C1570V18-375BZXC
CY7C1566V18-375BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1577V18-375BZI
CY7C1568V18-375BZI
CY7C1570V18-375BZI
CY7C1566V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-375BZXI
CY7C1568V18-375BZXI
CY7C1570V18-375BZXI

Ordering Code

Package
Diagram

Package Type

Operating

Range

Document Number: 001-06551 Rev. *E Page 25 of 28

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Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or
visit www.cypress.com for actual products offered.

Speed

(MHz)

333 CY7C1566V18-333BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1577V18-333BZC
CY7C1568V18-333BZC
CY7C1570V18-333BZC
CY7C1566V18-333BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-333BZXC
CY7C1568V18-333BZXC
CY7C1570V18-333BZXC
CY7C1566V18-333BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1577V18-333BZI
CY7C1568V18-333BZI
CY7C1570V18-333BZI
CY7C1566V18-333BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-333BZXI
CY7C1568V18-333BZXI
CY7C1570V18-333BZXI

300 CY7C1566V18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1577V18-300BZC
CY7C1568V18-300BZC
CY7C1570V18-300BZC
CY7C1566V18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-300BZXC
CY7C1568V18-300BZXC
CY7C1570V18-300BZXC
CY7C1566V18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial
CY7C1577V18-300BZI
CY7C1568V18-300BZI
CY7C1570V18-300BZI
CY7C1566V18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1577V18-300BZXI
CY7C1568V18-300BZXI
CY7C1570V18-300BZXI

Ordering Code

Package
Diagram

Package Type

Operating

Range

Document Number: 001-06551 Rev. *E Page 26 of 28

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Package Diagram

!

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#

$

%

&

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(

*

+

,

-

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51-85195-*A

Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm)

Document Number: 001-06551 Rev. *E Page 27 of 28

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Document History Page

Document Title: CY7C1566V18/CY7C1577V18/CY7C1568V18/CY7C1570V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec­ture (2.5 Cycle Read Latency)
Document Number: 001-06551

REV. ECN No.

Issue

Date

** 432718 See ECN NXR New datasheet
*A 437000 See ECN IGS ECN to show on web
*B 461934 See ECN NXR Changed t

*C 497567 See ECN NXR Changed the V

*D 1351504 See ECN VKN/AESA Converted from preliminary to final

*E 2193266 See ECN VKN/AESA Added footnote# 20 related to I

Orig. of

Change

Description of Change

and t

from 10 ns to 5 ns, and changed t

TH

from 40 ns to 20 ns, changed t

TL

Characteristics table

from 20 ns to 10 ns in TAP AC Switching

TDOV

TMSS

, t

TDIS

, tCS, t

TMSH

, t

TDIH

Modified power up waveform

operating voltage to 1.4V to VDD in the Features section, Operating

Range table, and the DC Electrical Characteristics table

DDQ

Added foot note in page 1
Changed the Maximum rating of ambient temperature with power applied from –10°C
to +85°C to –55°C to +125°C
Changed V
istics table and in the note below the table

(Max) specification from 0.85V to 0.95V in the DC Electrical Character-

REF

Updated footnote 18 to specify overshoot and undershoot specification
Updated I
Updated Θ
Removed x9 part and its related information

and ISB values

DD

and Θ

JA

JC

values

Updated footnote 25

Added x8 and x9 parts
Updated logic block diagram for x18 and x36 parts
Changed t
Updated footnote# 21

max spec to 8.4 ns for all speed bins

CYC

Updated Ordering Information table

DD

, t

CH

© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life sa vin g, critical control or safety applications, unless pursuant to an express written agreem ent with Cypress. Furthermore, Cypress does not a uthor i ze i ts products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States co pyright la ws and inte rnatio na l tre aty prov isi ons. Cyp ress he reby g rant s to lice nsee a p erson al, no n-ex clusi ve, non-tra nsferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpo se of creating custom sof tware and or firm ware in support of licen see product to be use d only in conjunction with a Cypress
integrated circuit as specified in th e applicable agreement. Any reproductio n, modification, translation, co mpilation, o r representati on of this Sour ce Code except as specified above is prohibited without
the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the ap plicati on or u se o f any pr oduct o r circui t descri bed h erein. Cypr ess does not aut horize it s product s for use a s critical compo nent s in life-support systems whe re
a malfunction or failure may reasonab ly be expected to resu lt in significant injury t o the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-06551 Rev. *E Revised March 11, 2008 Page 28 of 28

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.

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