Cypress CY7C1527KV18, CY7C1516KV18, CY7C1520KV18, CY7C1518KV18 User Manual

72-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Features

Functional Description

■ 72-Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 333 MHz Clock for High Bandwidth

■ 2-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces

(data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Synchronous Internally Self-timed Writes

■ DDR-II operates with 1.5 Cycle Read Latency when DOFF is

asserted HIGH

■ Operates similar to DDR-I Device with 1 Cycle Read Latency

when DOFF

■ 1.8V Core Power Supply with HSTL Inputs and Outputs

■ Variable Drive HSTL Output Buffers

■ Expanded HSTL Output Voltage (1.4V–V
❐ Supports both 1.5V and 1.8V IO supply

■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ JTAG 1149.1 compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

is asserted LOW

DD

)

The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and
CY7C1520KV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K
driven on the rising edges of C and C
edge of K and K

if C/C are not provided. Each address location

if provided, or on the rising

. Read data is

is associated with two 8-bit words in the case of CY7C1516KV18
and two 9-bit words in the case of CY7C1527KV18 that burst
sequentially into or out of the device. The burst counter always
starts with a “0” internally in the case of CY7C1516KV18 and
CY7C1527KV18. On CY7C1518KV18 and CY7C1520KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1518KV18 and two 36-bit words in the case of
CY7C1520KV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ

, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by
the K or K
registers controlled by the C or C

input clocks. All data outputs pass through output

(or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.

Configurations

CY7C1516KV18 – 8M x 8

CY7C1527KV18 – 8M x 9

CY7C1518KV18 – 4M x 18

CY7C1520KV18 – 2M x 36

Table 1. Selection Guide

Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 333 300 250 200 167 MHz

Maximum Operating Current x8 510 480 420 370 340 mA

x9 510 480 420 370 340

x18 520 490 430 380 340

x36 640 600 530 450 400

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-00437 Rev. *E Revised March 30, 2009

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Logic Block Diagram (CY7C1516KV18)

Write
Reg

Write
Reg

CLK

A

(21:0)

Gen.

K

K

Control

Logic

Address

Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

Reg.

Reg.

8

16

8

NWS

[1:0]

V

REF

Write Add. Decode

8

22

C

C

8

LD

Control

R/W

DOFF

4M x 8 Array

4M x 8 Array

8

DQ

[7:0]

8

CQ

CQ

Write
Reg

Write
Reg

CLK

A

(21:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

Reg.

Reg.

9

18

9

BWS

[0]

V

REF

Write Add. Decode

9

22

C

C

9

LD

Control

R/W

DOFF

4M x 9 Array

4M x 9 Array

9

DQ

[8:0]

9

CQ

CQ

Logic Block Diagram (CY7C1527KV18)

Document Number: 001-00437 Rev. *E Page 2 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Logic Block Diagram (CY7C1518KV18)

Write
Reg

Write
Reg

CLK

A

(21:0)

Gen.

K

K

Control

Logic

Address
Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

Reg.

Reg.

18

36

18

BWS

[1:0]

V

REF

Write Add. Decode

18

22

C

C

18

LD

Control

Burst

Logic

A0

A

(21:1)

R/W

DOFF

2M x 18 Array

2M x 18 Array

21

18

DQ

[17:0]

18

CQ

CQ

Write
Reg

Write
Reg

CLK

A

(20:0)

Gen.

K

K

Control

Logic

Address

Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

Reg.

Reg.

36

72

36

BWS

[3:0]

V

REF

Write Add. Decode

36

21

C

C

36

LD

Control

Burst
Logic

A0

A

(20:1)

R/W

DOFF

1M x 36 Array

1M x 36 Array

20

36

DQ

[35:0]

36

CQ

CQ

Logic Block Diagram (CY7C1520KV18)

Document Number: 001-00437 Rev. *E Page 3 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Pin Configuration

Note

1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configurations for CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1516KV18 (8M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAR/WNWS

1

B NC NC NC A NC/288M K NWS

C NC NC NC V

D NC NC NC V

E NC NC DQ4 V

F NC NC NC V

G NC NC DQ5 V

H DOFF V

REF

V

DDQ

V

J NC NC NC V

K NC NC NC V

L NC DQ6 NC V

M NC NC NC V

N NC NC NC V

SS

SS

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

SS

SS

AAAVSSNC NC NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

P NC NC DQ7 A A C A A NC NC NC

R TDO TCK A A A C AAATMSTDI

K NC/144M LD AACQ

0

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

ANCNCDQ3

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

[1]

NC NC NC

NC NC DQ2

NC NC NC

NC NC NC

V

DDQ

V

REF

NC DQ1 NC

NC NC NC

NC NC DQ0

NC NC NC

ZQ

CY7C1527KV18 (8M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAR/WNC K NC/144M LD AACQ

B NC NC NC A NC/288M K BWS

C NC NC NC V

D NC NC NC V

E NC NC DQ4 V

F NC NC NC V

G NC NC DQ5 V

H DOFF V

REF

V

DDQ

V

J NC NC NC V

K NC NC NC V

L NC DQ6 NC V

M NC NC NC V

N NC NC NC V

SS

SS

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

SS

SS

AAAVSSNC NC NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

0

ANCNCDQ3

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

SS

NC NC NC

NC NC DQ2

NC NC NC

NC NC NC

V

DDQ

V

REF

NC DQ1 NC

NC NC NC

NC NC DQ0

NC NC NC

ZQ

P NC NC DQ7 A A C A A NC NC DQ8

R TDO TCK A A A C AAATMSTDI

Document Number: 001-00437 Rev. *E Page 4 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Pin Configuration (continued)

The pin configurations for CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1518KV18 (4M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAR/WBWS

1

B NC DQ9 NC A NC/288M K BWS

C NC NC NC V

D NC NC DQ10 V

E NC NC DQ11 V

F NC DQ12 NC V

G NC NC DQ13 V

H DOFF V

REF

V

DDQ

V

J NC NC NC V

K NC NC DQ14 V

L NC DQ15 NC V

M NC NC NC V

N NC NC DQ16 V

SS

SS

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

SS

SS

AA0AVSSNC DQ7 NC

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC NC

P NC NC DQ17 A A C A A NC NC DQ0

R TDO TCK A A A C AAATMSTDI

K NC/144M LD AACQ

0

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

ANCNCDQ8

V

SS

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

[1]

NC NC NC

NC NC DQ6

NC NC DQ5

NC NC NC

V

DDQ

V

REF

NC DQ4 NC

NC NC DQ3

NC NC DQ2

NC DQ1 NC

ZQ

CY7C1520KV18 (2M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A R/W BWS

B NC DQ27 DQ18 A BWS

C NC NC DQ28 V

D NC DQ29 DQ19 V

E NC NC DQ20 V

F NC DQ30 DQ21 V

G NC DQ31 DQ22 V

H DOFF V

REF

V

DDQ

V

J NC NC DQ32 V

K NC NC DQ23 V

L NC DQ33 DQ24 V

M NC NC DQ34 V

N NC DQ35 DQ25 V

SS

SS

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

SS

SS

AA0AVSSNC DQ17 DQ7

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

AAAVSSNC NC DQ10

2

3

K BWS

LD AACQ

1

KBWS0ANCNCDQ8

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

SS

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

V

SS

SS

NC NC DQ16

NC DQ15 DQ6

NC NC DQ5

NC NC DQ14

V

DDQ

V

REF

ZQ

NC DQ13 DQ4

NC DQ12 DQ3

NC NC DQ2

NC DQ11 DQ1

P NC NC DQ26 A A C A A NC DQ9 DQ0

R TDO TCK A A A C AAATMSTDI

Document Number: 001-00437 Rev. *E Page 5 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Pin Definitions

Pin Name I/O Pin Description

DQ

[x:0]

LD Input-

NWS
NWS

BWS
BWS
BWS
BWS

A, A0 Input-

R/W

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

C

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

K

,

0
1

,

0

,

1

,

2
3

Input Output­Synchronous

Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C
mode. When read access is deselected, Q
CY7C1516KV18 − DQ
CY7C1527KV18 − DQ
CY7C1518KV18 − DQ
CY7C1520KV18 − DQ

[7:0]
[8:0]
[17:0]
[35:0]

clocks during read operations or K and K when in single clock

are automatically tristated.

[x:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition

Synchronous

Input-

Synchronous

includes address and read/write direction. All transactions operate on a burst of 2 data.
Nibble Write Select 0, 1 − Active LOW (CY7C1516KV18 Only). Sampled on the rising edge of the K

and K

clocks during write operations. Used to select which nibble is written into the device during the
current portion of the write operations. Nibbles not written remain unaltered.
NWS0 controls D
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

and NWS1 controls D

[3:0]

[7:4]

.

ignores the corresponding nibble of data and it is not written into the device.

Input-

Synchronous

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1527KV18 − BWS
CY7C1518KV18 − BWS0 controls D
CY7C1520KV18 − BWS0 controls D

.

D

[35:27]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

controls D

0

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

and BWS3 controls

[26:18]

ignores the corresponding byte of data and it is not written into the device.

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the

Synchronous

device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1516KV18 and 8M x 9 (2 arrays each
of 4M x9) for CY7C1527KV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1518KV18, and 2M x 36 (2
arrays each of 1M x 36) for CY7C1520KV18.
CY7C1516KV18 – Since the least significant bit of the address internally is a “0,” only 22 external address
inputs are needed to access the entire memory array.
CY7C1527KV18 – Since the least significant bit of the address internally is a “0,” only 22 external address
inputs are needed to access the entire memory array.
CY7C1518KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
22 address inputs are needed to access the entire memory array.
CY7C1520KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
21 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.

Input-

Synchronous

Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read when
R/W

is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See application example for further details.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See application example for further details.

and to drive out data through Q
edge of K.

when in single clock mode. All accesses are initiated on the rising

[x:0]

Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and

to drive out data through Q

when in single clock mode.

[x:0]

Document Number: 001-00437 Rev. *E Page 6 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Pin Definitions (continued)

Pin Name I/O Pin Description

CQ Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.

CQ

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG.

TCK Input TCK Pin for JTAG.

TDI Input TDI Pin for JTAG.

TMS Input TMS Pin for JTAG.

NC N/A Not Connected to the Die. Can be tied to any voltage level.

NC/144M Input Not Connected to the Die. Can be tied to any voltage level.

NC/288M Input Not Connected to the Die. Can be tied to any voltage level.

V

REF

V

DD

V

SS

V

DDQ

Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

Input PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

Input-

Reference

Power Supply Power supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C
for the echo clocks is shown in the AC Timing table.

impedance. CQ, CQ, and Q
between ZQ and ground. Alternatively, this pin can be connected directly to V
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR-I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR-I timing.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.

) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document Number: 001-00437 Rev. *E Page 7 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Functional Overview

The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and
CY7C1520KV18 are synchronous pipelined Burst SRAMs
equipped with a DDR interface, which operates with a read
latency of one and a half cycles when DOFF
When DOFF

pin is set LOW or connected to VSS the device

behaves in DDR-I mode with a read latency of one clock cycle.

Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K
referenced to the rising edge of the output clocks (C/C
when in single clock mode).

All synchronous data inputs (D
controlled by the rising edge of the input clocks (K and K
synchronous data outputs (Q
controlled by the rising edge of the output clocks (C/C

) pass through input registers

[x:0]

) pass through output registers

[x:0]

when in single clock mode).

All synchronous control (R/W, LD, BWS
input registers controlled by the rising edge of the input clock (K).

CY7C1518KV18 is described in the following sections. The
same basic descriptions apply to CY7C1516KV18,
CY7C1527KV18, and CY7C1520KV18.

Read Operations

The CY7C1518KV18 is organized internally as a two arrays of
2M x 18. Accesses are completed in a burst of 2 sequential 18-bit
data words. Read operations are initiated by asserting R/W
HIGH and LD LOW at the rising edge of the positive input clock
(K). The address presented to address inputs is stored in the
read address register and the least significant bit of the address
is presented to the burst counter. The burst counter increments
the address in a linear fashion. Following the next K clock rise,
the corresponding 18-bit word of data from this address location
is driven onto the Q
On the subsequent rising edge of C the next 18-bit data word

using C as the output timing reference.

[17:0]

from the address location generated by the burst counter is
driven onto the Q
the rising edge of the output clock (C or C

. The requested data is valid 0.45 ns from

[17:0]

single clock mode, 200 MHz, 250 MHz, and 300 MHz device). To
maintain the internal logic, each read access must be allowed to
complete. Read accesses can be initiated on every rising edge
of the positive input clock (K).

When read access is deselected, the CY7C1518KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive output clock (C). This enables for a transition
between devices without the insertion of wait states in a depth
expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments the
address in a linear fashion. On the following K clock rise, the data
presented to D

is latched and stored into the 18-bit write

[17:0]

pin is tied HIGH.

) and all output timing is

, or K/K

). All

, or K/K

) inputs pass through

[0:X]

, or K and K when in

data register, provided BWS
subsequent rising edge of the Negative Input Clock (K
mation presented to D
register, provided BWS
of data are then written into the memory array at the specified

[17:0]

[1:0]

are both asserted active. On the

[1:0]

) the infor-

is also stored into the write data

are both asserted active. The 36 bits

location. Write accesses can be initiated on every rising edge of
the positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K

).

When the write access is deselected, the device ignores all
inputs after the pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C1518KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS

, which are sampled with each set of 18-bit data words.

BWS

1

Asserting the appropriate Byte Write Select input during the data

and

0

portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature is used to simplify
read, modify, or write operations to a byte write operation.

Single Clock Mode

The CY7C1518KV18 is used with a single clock that controls
both the input and output registers. In this mode, the device
recognizes only a single pair of input clocks (K and K

) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C

clocks. All timing parameters remain the same in this mode.

To use this mode of operation, the user must tie C and C

HIGH
at power on. This function is a strap option and not alterable
during device operation.

DDR Operation

The CY7C1518KV18 enables high-performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C1518KV18 requires a single
No Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications may require a
second NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the read(s), the stored data from the earlier write is written
into the SRAM array. This is called a posted write.

If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.

Depth Expansion

Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.

Document Number: 001-00437 Rev. *E Page 8 of 30

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CY7C1518KV18, CY7C1520KV18

Programmable Impedance

Vterm = 0.75V

Vterm = 0.75V

R = 50ohms

R = 250ohms

LD# C C#R/W#

DQ
A

K

LD# C C#R/W#

DQ
A

K

SRAM#1

SRAM#2

R = 250ohms

BUS

MASTER

(CPU

or

ASIC)

DQ

Addresses

Cycle Start#

R/W#
Return CLK
Source CLK

Return CLK#

Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2

ZQ

CQ/CQ#

K#

ZQ

CQ/CQ#

K#

An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.

to allow the SRAM to adjust its output

SS

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C

. These are free running clocks and are synchro­nized to the output clock of the DDR-II. In single clock mode, CQ
is generated with respect to K and CQ is generated with respect
to K

. The timing for the echo clocks is shown in the Switching

Characteristics on page 23.

Application Example

Figure 1 shows two DDR-II used in an application.

Figure 1. Application Example

PLL

These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 μs of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 μs after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR-I mode (with one cycle latency and a longer
access time).

for a minimum of 30 ns.

Document Number: 001-00437 Rev. *E Page 9 of 30

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Truth Table

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tristate condition.

4. On CY7C1518KV18 and CY7C1520KV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst. On CY7C1516KV18 and CY7C1527KV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.

8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS

0

, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on

different portions of a write cycle, as long as the setup and hold requirements are achieved.

The truth table for the CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 follow.

Operation K LD R/W DQ DQ

Write Cycle:

L-H L L D(A1) at K(t + 1) ↑ D(A2) at K

Load address; wait one cycle;
input write data on consecutive K and K

Read Cycle:

rising edges.

L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑

Load address; wait one and a half cycle;
read data on consecutive C

and C rising edges.

NOP: No Operation L-H H X High-Z High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State

[2, 3, 4, 5, 6, 7]

(t + 1) ↑

Burst Address Table

(CY7C1518KV18, CY7C1520KV18)

First Address (External) Second Address (Internal)

X..X0 X..X1

X..X1 X..X0

Write Cycle Descriptions

The write cycle description table for CY7C1516KV18 and CY7C1518KV18 follows.

BWS0/

NWS

0

BWS1/

NWS

K

1

K

Comments

L L L–H – During the data portion of a write sequence:

CY7C1516KV18 − both nibbles (D
CY7C1518KV18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence:

CY7C1516KV18 − both nibbles (D
CY7C1518KV18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence:

CY7C1516KV18 − only the lower nibble (D
CY7C1518KV18 − only the lower byte (D

[3:0]

[8:0]

L H – L–H During the data portion of a write sequence:

CY7C1516KV18 − only the lower nibble (D
CY7C1518KV18 − only the lower byte (D

[3:0]

[8:0]

H L L–H – During the data portion of a write sequence:

CY7C1516KV18 − only the upper nibble (D
CY7C1518KV18 − only the upper byte (D

[7:4]

[17:9]

H L – L–H During the data portion of a write sequence:

CY7C1516KV18 − only the upper nibble (D
CY7C1518KV18 − only the upper byte (D

[7:4]

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation.

H H – L–H No data is written into the devices during this portion of a write operation.

[2, 8]

) is written into the device, D

) is written into the device, D

) is written into the device, D

) is written into the device, D

) is written into the device, D

) is written into the device, D

) is written into the device, D

) is written into the device, D

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

Document Number: 001-00437 Rev. *E Page 10 of 30

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Write Cycle Descriptions

The write cycle description table for CY7C1527KV18 follows.

[2, 8]

BWS

L L–H – During the data portion of a write sequence, the single byte (D

L – L–H During the data portion of a write sequence, the single byte (D

0

K K

) is written into the device.

[8:0]

) is written into the device.

[8:0]

H L–H – No data is written into the device during this portion of a write operation.

H – L–H No data is written into the device during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1520KV18 follows.

BWS0BWS1BWS2BWS3K K Comments

LLLLL–H–During the data portion of a write sequence, all four bytes (D

the device.

LLLL–L–HDuring the data portion of a write sequence, all four bytes (D

the device.

L H H H L–H – During the data portion of a write sequence, only the lower byte (D

into the device. D

L H H H – L–H During the data portion of a write sequence, only the lower byte (D

into the device. D

H L H H L–H – During the data portion of a write sequence, only the byte (D

the device. D

H L H H – L–H During the data portion of a write sequence, only the byte (D

the device. D

H H L H L–H – During the data portion of a write sequence, only the byte (D

the device. D

H H L H – L–H During the data portion of a write sequence, only the byte (D

the device. D

H H H L L–H – During the data portion of a write sequence, only the byte (D

the device. D

H H H L – L–H During the data portion of a write sequence, only the byte (D

the device. D

HHHHL–H–No data is written into the device during this portion of a write operation.

HHHH–L–HNo data is written into the device during this portion of a write operation.

[2, 8]

[35:9]

[35:9]

and D

[8:0]

and D

[8:0]

and D

[17:0]

and D

[17:0]

remains unaltered.

[26:0]

remains unaltered.

[26:0]

remains unaltered.

remains unaltered.

remains unaltered.

[35:18]

remains unaltered.

[35:18]

remains unaltered.

[35:27]

remains unaltered.

[35:27]

[35:0]

[35:0]

[17:9]

[17:9]

[26:18]

[26:18]

[35:27]

[35:27]

) are written into

) are written into

) is written

[8:0]

) is written

[8:0]

) is written into

) is written into

) is written into

) is written into

) is written into

) is written into

Document Number: 001-00437 Rev. *E Page 11 of 30

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter­nally pulled up and may be unconnected. They may alternatively
be connected to V
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up inter­nally, resulting in a logic HIGH level.

Test Data-In ( T D I)

The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State

Diagram on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
High-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.

through a pull up resistor. TDO must be left

DD

Instruction Register

Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.

When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (V
the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.

The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.

The Boundary Scan Order on page 18 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other infor­mation described in Identification Register Definitions on page

17.

SS

) when

TAP Instruction Set

Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction

Codes on page 17. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions
are described in this section in detail.

Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.

Document Number: 001-00437 Rev. *E Page 12 of 30

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IDCODE

The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.

SAMPLE Z

The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.

The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.

To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (t
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.

and tCH). The SRAM clock input might not be captured

CS

PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.

EXTEST OUTPUT BUS TRISTATE

IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.

The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.

This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document Number: 001-00437 Rev. *E Page 13 of 30

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TAP Controller State Diagram

TEST-LOGIC
RESET

TEST-LOGIC/
IDLE

SELECT
DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

1

0

1

1

0

1

0

1

0

0

0

1

1

1

0

1

0

1

0

0

0

1

0

1

1

0

1

0

0

1

1

0

SELECT
IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAU SE-IR

EXIT2-IR

UPDATE-IR

Note

9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

The state diagram for the TAP controller follows.

[9]

Document Number: 001-00437 Rev. *E Page 14 of 30

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TAP Controller Block Diagram

0

012..29

3031

Boundary Scan Register

Identification Register

012..

.

.108

012

Instruction Register

Bypass Register

Selection
Circuitry

Selection
Circuitry

TAP Contro ll e r

TDI

TDO

TCK

TMS

Notes

10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

11. Overshoot: V

IH

(AC) < V

DDQ

+ 0.85V (Pulse width less than t

CYC

/2), Undershoot: V

IL

(AC) > −1.5V (Pulse width less than t

CYC

/2).

12. All voltage referenced to Ground.

TAP Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Max Unit

V

OH1

V

OH2

V

OL1

V

OL2

V

IH

V

IL

I

X

Output HIGH Voltage I

Output HIGH Voltage I

Output LOW Voltage IOL = 2.0 mA 0.4 V

Output LOW Voltage IOL = 100 μA0.2V

Input HIGH Voltage 0.65VDDV

Input LOW Voltage –0.3 0.35V

Input and Output Load Current GND ≤ VI ≤ V

[10, 11, 12]

= −2.0 mA 1.4 V

OH

= −100 μA1.6 V

OH

DD

–5 5 μA

+ 0.3 V

DD

DD

V

Document Number: 001-00437 Rev. *E Page 15 of 30

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TAP AC Switching Characteristics

t

TL

t

TH

(a)

TDO

C

L

= 20 pF

Z

0

= 50

Ω

GND

0.9V

50

Ω

1.8V

0V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In
TDI

Test Data Out

t

TCYC

t

TMSH

t

TMSS

t

TDIS

t

TDIH

t

TDOV

t

TDOX

TDO

Notes

13. t

CS

and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14. Test conditions are specified using the load in TAP AC Test Conditions. t

R/tF

= 1 ns.

Over the Operating Range

Parameter Description Min Max Unit

t

TCYC

t

TF

t

TH

t

TL

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH 20 ns

TCK Clock LOW 20 ns

Setup Times

t

TMSS

t

TDIS

t

CS

TMS Setup to TCK Clock Rise 5 ns

TDI Setup to TCK Clock Rise 5 ns

Capture Setup to TCK Rise 5 ns

Hold Times

t

TMSH

t

TDIH

t

CH

TMS Hold after TCK Clock Rise 5 ns

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

Output Times

t

TDOV

t

TDOX

TCK Clock LOW to TDO Valid 10 ns

TCK Clock LOW to TDO Invalid 0 ns

[13, 14]

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.

Figure 2. TAP Timing and Test Conditions

[14]

Document Number: 001-00437 Rev. *E Page 16 of 30

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Identification Register Definitions

Instruction Field

Revision Number
(31:29)

Cypress Device ID
(28:12)

Cypress JEDEC ID
(11:1)

ID Register
Presence (0)

CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18

000 000 000 000 Version number.

11010100010000100 11010100010001100 11010100010010100 11010100010100100 Defines the type of

00000110100 00000110100 00000110100 00000110100 Allows unique

1111Indicates the

Value

Description

SRAM.

identification of
SRAM vendor.

presence of an ID
register.

Scan Register Sizes

Register Name Bit Size

Instruction 3

Bypass 1

ID 32

Boundary Scan 109

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the input and output ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

and TDO. Does not affect the SRAM operation.

operation.

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CY7C1518KV18, CY7C1520KV18

Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 1J

16P299G575B852J

2 6N 30 11F 58 5A 86 3K

3 7P 31 11G 59 4A 87 3J

47N329F605C882K

5 7R 33 10F 61 4B 89 1K

6 8R 34 11E 62 3A 90 2L

7 8P 35 10E 63 2A 91 3L

8 9R 36 10D 64 1A 92 1M

9 11P 37 9E 65 2B 93 1L

10 10P 38 10C 66 3B 94 3N

11 10N 39 11D 67 1C 95 3M

12 9P 40 9C 68 1B 96 1N

13 10M 41 9D 69 3D 97 2M

14 11N 42 11B 70 3C 98 3P

15 9M 43 11C 71 1D 99 2N

16 9N 44 9B 72 2C 100 2P

17 11L 45 10B 73 3E 101 1P

18 11M 46 11A 74 2D 102 3R

19 9L 47 10A 75 2E 103 4R

20 10L 48 9A 76 1E 104 4P

21 11K 49 8B 77 2F 105 5P

22 10K 50 7C 78 3F 106 5N

23 9J 51 6C 79 1G 107 5R

24 9K 52 8A 80 1F 108 Internal

25 10J 53 7A 81 3G

26 11J 54 7B 82 2G

27 11H 55 6B 83 1H

Document Number: 001-00437 Rev. *E Page 18 of 30

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Power Up Sequence in DDR-II SRAM

~

~

DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.

Power Up Sequence

■ Apply power and drive DOFF either HIGH or LOW (All other

inputs can be HIGH or LOW).

❐ Apply V
❐ Apply V
❐ Drive DOFF HIGH.

■ Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs

to lock the PLL.

before V

DD

DDQ

K

before V

.

DDQ

or at the same time as V

REF

.

REF

Figure 3. Power Up Waveforms

PLL Constraints

■ PLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as t

■ The PLL functions at frequencies down to 120 MHz.

■ If the input clock is unstable and the PLL is enabled, then the

PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 μs of stable clock to
relock to the desired clock frequency.

~

KC Var

.

K

~

Unstable Clock

> 20Ps Stable clock

Start Normal
Operation

/

Clock Start

/

V

V

DDQDD

(Clock Starts after Stable)

/

V

V

DDQDD

DOFF

V

V

DD

DDQ

Stable (< +/- 0.1V DC per 50ns )

Fix HIGH (or tie to V

DDQ

)

Document Number: 001-00437 Rev. *E Page 19 of 30

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Maximum Ratings

Notes

15. Power up: assumes a linear ramp from 0V to V

DD

(min) within 200 ms. During this time V

IH

< V

DD

and V

DDQ

< VDD.

16. Outputs are impedance controlled. I

OH

= –(V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

17. Outputs are impedance controlled. I

OL

= (V

DDQ

/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.

18. V

REF

(min) = 0.68V or 0.46V

DDQ

, whichever is larger, V

REF

(max) = 0.95V or 0.54V

DDQ

, whichever is smaller.

19. The operation current is calculated with 50% read cycle and 50% write cycle.

Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V

Supply Voltage on V

DC Applied to Outputs in High-Z .........–0.5V to V

DC Input Voltage

Relative to GND.......–0.5V to +V

DDQ

[11]

..............................–0.5V to VDD + 0.3V

DDQ

DD

+ 0.3V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V

Latch up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to

Industrial –40°C to +85°C

Ambient

Temperature (TA) V

DD

[15]

V

DDQ

V

DD

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

V

DD

V

DDQ

V

OH

V

OL

V

OH(LOW)

V

OL(LOW)

V

IH

V

IL

I

X

I

OZ

V

REF

[19]

I

DD

Power Supply Voltage 1.7 1.8 1.9 V

IO Supply Voltage 1.4 1.5 V

Output HIGH Voltage Note 16 V

Output LOW Voltage Note 17 V

Output HIGH Voltage I

Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V

Input HIGH Voltage V

Input LOW Voltage –0.3 V
Input Leakage Current GND ≤ VI ≤ V
Output Leakage Current GND ≤ VI ≤ V

Input Reference Voltage

VDD Operating Supply V

[12]

DD

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

= −0.1 mA, Nominal Impedance V

OH

DDQ

Output Disabled −5 5 μA

DDQ,

[18]

Typical Value = 0.75V 0.68 0.75 0.95 V

DD

I

OUT

f = f

= Max,

= 0 mA,

= 1/t

MAX

CYC

333 MHz (x8) 510 mA

(x9) 510

– 0.2 V

DDQ

SS

+ 0.1 V

REF

−5 5 μA

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

DDQ

0.2 V

+ 0.3 V

DDQ

– 0.1 V

REF

(x18) 520

(x36) 640

300 MHz (x8) 480 mA

(x9) 480

(x18) 490

(x36) 600

250 MHz (x8) 420 mA

(x9) 420

(x18) 430

(x36) 530

[15]

V

V

Document Number: 001-00437 Rev. *E Page 20 of 30

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Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

[19]

I

DD

I

SB1

VDD Operating Supply V

Automatic Power Down
Current

[12]

= Max,

DD

= 0 mA,

I

OUT

f = f

MAX

= 1/t

CYC

Max VDD,
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = f
Inputs Static

MAX

= 1/t

CYC,

200 MHz (x8) 370 mA

(x9) 370

(x18) 380

(x36) 450

167 MHz (x8) 340 mA

(x9) 340

(x18) 340

(x36) 400

333 MHz (x8) 290 mA

(x9) 290

(x18) 290

(x36) 290

300 MHz (x8) 280 mA

(x9) 280

(x18) 280

(x36) 280

250 MHz (x8) 270 mA

(x9) 270

(x18) 270

(x36) 270

200 MHz (x8) 250 mA

(x9) 250

(x18) 250

(x36) 250

167 MHz (x8) 250 mA

(x9) 250

(x18) 250

(x36) 250

AC Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions Min Typ Max Unit

V

IH

V

IL

Input HIGH Voltage V

Input LOW Voltage – – V

Document Number: 001-00437 Rev. *E Page 21 of 30

[11]

+ 0.2 – – V

REF

– 0.2 V

REF

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CY7C1518KV18, CY7C1520KV18

Capacitance

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device

R

L

= 50Ω

Z

0

= 50Ω

V

REF

= 0.75V

V

REF

= 0.75V

[20]

0.75V

Under
Te st

0.75V

Device
Under
Te st

OUTPUT

0.75V

V

REF

V

REF

OUTPUT

ZQ

ZQ

(a)

Slew Rate = 2 V/ns

RQ =
250

Ω

(b)

RQ =
250

Ω

Note

20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, V

REF

= 0.75V, RQ = 250Ω, V

DDQ

= 1.5V, input pulse

levels of 0.25V to 1.25V, and output loading of the specified I

OL/IOH

and load capacitance shown in (a) of AC Test Loads and Waveforms.

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions Max Unit

C

Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, V

IN

C

O

Output Capacitance 3pF

= 1.5V 2 pF

DDQ

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions

Θ

Θ

Thermal Resistance

JA

(Junction to Ambient)

Thermal Resistance

JC

(Junction to Case)

Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.

Figure 4. AC Test Loads and Waveforms

165 FBGA

Package

13.7 °C/W

3.73 °C/W

Unit

Document Number: 001-00437 Rev. *E Page 22 of 30

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Switching Characteristics

Notes

21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.

22. This part has an internal voltage regulator; t

POWER

is the time that the power is supplied above V

DD

min initially before a read or write operation can be initiated.

Over the Operating Range

[20, 21]

Cypress

Parameter

t

POWER

t

CYC

t

KH

t

KL

t

KHKH

t

KHCH

Consortium

Parameter

t

KHKH

t

KHKL

t

KLKH

t

KHKH

t

KHCH

Setup Times

t

SA

t

SC

t

SCDDR

t

SD

t

AVKH

t

IVKH

t

IVKH

t

DVKH

Hold Times

t

HA

t

HC

t

HCDDRtKHIX

t

HD

t

KHAX

t

KHIX

t

KHDX

Description

VDD(Typical) to the First Access

333 MHz 300 MHz 250 MHz 200 MHz 167 MHz

Min Max Min Max Min Max Min Max Min Max

[22]

1–1–1–1–1–ms

Unit

K Clock and C Clock Cycle Time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns

Input Clock (K/K and C/C) HIGH 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns

Input Clock (K/K and C/C) LOW 1.20 – 1.32 – 1.6 – 2.0 – 2.4 – ns

K Clock Rise to K Clock Rise and C
to C

Rise (rising edge to rising edge)

K/K Clock Rise to C/C Clock Rise

1.35 – 1.49 – 1.8 – 2.2 – 2.7 – ns

0.0 1.30 0.0 1.45 0.0 1.8 0.0 2.2 0.0 2.7 ns

(rising edge to rising edge)

Address Setup to K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

Control Setup to K Clock Rise
(LD

, R/W)

Double Data Rate Control Setup to
Clock (K/K
(BWS

D

[X:0]

) Rise

, BWS1, BWS2, BWS3)

0

Setup to Clock (K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Address Hold after K Clock Rise 0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

Control Hold after K Clock Rise
(LD

, R/W)

Double Data Rate Control Hold after
Clock (K/K
(BWS

D

[X:0]

) Rise

, BWS1, BWS2, BWS3)

0

Hold after Clock (K/K) Rise 0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Document Number: 001-00437 Rev. *E Page 23 of 30

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Switching Characteristics (continued)

Notes

23. These parameters are extrapolated from the input timing parameters (t

CYC/2

- 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by

design and are not tested in production.

24. t

CHZ

, t

CLZ

are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady-state voltage.

25. At any voltage and temperature t

CHZ

is less than t

CLZ

and t

CHZ

less than tCO.

Over the Operating Range

[20, 21]

Cypress

Parameter

Consortium

Parameter

Output Times

t

CO

t

DOH

t

CCQO

t

CQOH

t

CQD

t

CQDOHtCQHQX

t

CQH

t

CQHCQHtCQHCQH

t

CHZ

t

CLZ

t

CHQV

t

CHQX

t

CHCQV

t

CHCQX

t

CQHQV

t

CQHCQL

t

CHQZ

t

CHQX1

PLL Timing

t

KC Var

t

KC lock

t

KC ResettKC Reset

t

KC Var

t

KC lock

Description

C/C Clock Rise (or K/K in single

333 MHz 300 MHz 250 MHz 200 MHz 167 MHz

Min Max Min Max Min Max Min Max Min Max

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

Unit

clock mode) to Data Valid

Data Output Hold after Output C/C

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

Clock Rise (Active to Active)

C/C Clock Rise to Echo Clock Valid – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

Echo Clock Hold after C/C Clock

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

Rise

Echo Clock High to Data Valid – 0.25 – 0.27 – 0.30 – 0.35 – 0.40 ns

Echo Clock High to Data Invalid –0.25 – –0.27 – –0.30 – –0.35 – –0.40 – ns

Output Clock (CQ/CQ) HIGH

CQ Clock Rise to CQ Clock Rise
(rising edge to rising edge)

Clock (C/C) Rise to High-Z
(Active to High-Z)

[24, 25]

Clock (C/C) Rise to Low-Z

[23]

[23]

[24, 25]

1.25–1.40–1.75–2.25–2.75– ns

1.25–1.40–1.75–2.25–2.75– ns

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns
PLL Lock Time (K, C) 20–20–20–20–20– μs

K Static to PLL Reset 30–30–30–30–30– ns

Document Number: 001-00437 Rev. *E Page 24 of 30

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Switching Waveforms

Notes

26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

27. Outputs are disabled (High-Z) one clock cycle after a NOP.

28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Figure 5. Read/Write/Deselect Sequence

[26, 27, 28]

R/W

DQ

LD

NOP

1

K

t

KH

K

A

C

t

KHCH

READ READREAD NOP NOP WRITEWRITE

2345678 910

A1

t

KHKH

t

CLZ

t

CO

Q00 Q11Q01 Q10

t

CQDOH

t

DOH

t

CQD

A2

t

CHZ

A3

t

HD

t

SD

D20

t

t

KH

KL

A4

t

SD

D21 D30

t

CYC

t

HD

t

D31

KHKH

Q40

t

t

t

SA

KL

SC

A0

t

HC

t

HA

t

CYC

t

KHCH

Q41

C#

t

CCQO

t

CQH

t

CQHCQH

DON’T CARE

UNDEFINED

CQ

CQ#

t

CQOH

t

CCQO

t

CQOH

Document Number: 001-00437 Rev. *E Page 25 of 30

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Ordering Information

The following table lists all possible speed, package, and temperature range options supported for these devices. Note that some
options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at

www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales

representative for the status of availability of parts.

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=

201&PageID=230.

Table 2. Ordering Information

Speed

(MHz) Ordering Code

333 CY7C1516KV18-333BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1527KV18-333BZC

CY7C1518KV18-333BZC

CY7C1520KV18-333BZC

CY7C1516KV18-333BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-333BZXC

CY7C1518KV18-333BZXC

CY7C1520KV18-333BZXC

CY7C1516KV18-333BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1527KV18-333BZI

CY7C1518KV18-333BZI

CY7C1520KV18-333BZI

CY7C1516KV18-333BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-333BZXI

CY7C1518KV18-333BZXI

CY7C1520KV18-333BZXI

300 CY7C1516KV18-300BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1527KV18-300BZC

CY7C1518KV18-300BZC

CY7C1520KV18-300BZC

CY7C1516KV18-300BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-300BZXC

CY7C1518KV18-300BZXC

CY7C1520KV18-300BZXC

CY7C1516KV18-300BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1527KV18-300BZI

CY7C1518KV18-300BZI

CY7C1520KV18-300BZI

CY7C1516KV18-300BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-300BZXI

CY7C1518KV18-300BZXI

CY7C1520KV18-300BZXI

Package
Diagram Package Type

Operating

Range

Document Number: 001-00437 Rev. *E Page 26 of 30

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Table 2. Ordering Information (continued)

Speed

(MHz) Ordering Code

250 CY7C1516KV18-250BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1527KV18-250BZC

CY7C1518KV18-250BZC

CY7C1520KV18-250BZC

CY7C1516KV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-250BZXC

CY7C1518KV18-250BZXC

CY7C1520KV18-250BZXC

CY7C1516KV18-250BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1527KV18-250BZI

CY7C1518KV18-250BZI

CY7C1520KV18-250BZI

CY7C1516KV18-250BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-250BZXI

CY7C1518KV18-250BZXI

CY7C1520KV18-250BZXI

200 CY7C1516KV18-200BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1527KV18-200BZC

CY7C1518KV18-200BZC

CY7C1520KV18-200BZC

CY7C1516KV18-200BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-200BZXC

CY7C1518KV18-200BZXC

CY7C1520KV18-200BZXC

CY7C1516KV18-200BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1527KV18-200BZI

CY7C1518KV18-200BZI

CY7C1520KV18-200BZI

CY7C1516KV18-200BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-200BZXI

CY7C1518KV18-200BZXI

CY7C1520KV18-200BZXI

Package
Diagram Package Type

Operating

Range

Document Number: 001-00437 Rev. *E Page 27 of 30

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Table 2. Ordering Information (continued)

Speed

(MHz) Ordering Code

167 CY7C1516KV18-167BZC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial

CY7C1527KV18-167BZC

CY7C1518KV18-167BZC

CY7C1520KV18-167BZC

CY7C1516KV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-167BZXC

CY7C1518KV18-167BZXC

CY7C1520KV18-167BZXC

CY7C1516KV18-167BZI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial

CY7C1527KV18-167BZI

CY7C1518KV18-167BZI

CY7C1520KV18-167BZI

CY7C1516KV18-167BZXI 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

CY7C1527KV18-167BZXI

CY7C1518KV18-167BZXI

CY7C1520KV18-167BZXI

Package
Diagram Package Type

Operating

Range

Document Number: 001-00437 Rev. *E Page 28 of 30

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Package Diagram

A

1

PIN 1 CORNER

15.00±0.10

13.00±0.10

7.00

1.00

Ø0.50 (165X)

Ø0.25MCAB

Ø0.05 M C

B

A

0.15(4X)

0.35±0.06

SEATING PLANE

0.53±0.05

0.25 C

0.15 C

PIN 1 CORNER

TOP VIEW

BOTTOM VIEW

2345678910

10.00

14.00

B

C

D

E

F

G

H

J

K

L

M

N

11

1110986754321

P

R

P

R

K

M

N

L

J

H

G

F

E

D

C

B

A

A

15.00±0.10

13.00±0.10

B

C

1.00

5.00

0.36

-0.06

+0.14

1.40 MAX.

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

NOTES :

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AC

51-85180-*A

Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180

Document Number: 001-00437 Rev. *E Page 29 of 30

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CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18

Document History Page

Document Title: CY7C1516KV18/CY7C1527KV18/CY7C1518KV18/CY7C1520KV18, 72-Mbit DDR-II SRAM 2-Word
Burst Architecture
Document Number: 001-00437

Rev. ECN No.

Orig. of
Change

Submission

Date

Description of Change

** 374703 SYT See ECN New Data Sheet

*A 1103864 VKN See ECN Updated I

Updated ordering information table

DD

spec

*B 1699246 VKN/AESA See ECN Converted from Advance Information to Preliminary
*C 1939726 VKN/AESA See ECN Changed PLL lock time from 1024 cycles to 20 μs

Added footnote #19 related to I
Corrected typo in the footnote #23

DD

*D 2606839 VKN/PYRS 11/13/08 Changed JTAG ID [31:29] from 001 to 000,

Updated power up sequence waveform and its description,
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings” on page 20,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.

*E 2681899 VKN/PYRS 04/01/2009 Converted from preliminary to final

Added note on top of the Ordering Information table
Moved to external web

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© Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
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Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-00437 Rev. *E Revised March 30, 2009 Page 30 of 30

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of thei r respective holders.

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