Cypress CY7C1513KV18, CY7C1511KV18, CY7C1526KV18, CY7C1515KV18 User Manual

72-Mbit QDR™-II SRAM 4-Word

Burst Architecture

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Features

Configurations

■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions

■ 333 MHz Clock for High Bandwidth

■ 4-word Burst for Reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for precise DDR Timing ❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Single Multiplexed Address Input Bus latches Address Inputs

for Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous Internally Self-timed Writes

■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF

is asserted HIGH

■ Operates similar to QDR-I Device with 1 Cycle Read Latency

when DOFF

■ Available in x8, x9, x18, and x36 Configurations

■ Full Data Coherency, providing Most Current Data

■ Core V ❐ Supports both 1.5V and 1.8V IO supply

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

is asserted LOW

= 1.8V (±0.1V); IO V

= 1.4V to V

DDQ

CY7C1511KV18 – 8M x 8

CY7C1526KV18 – 8M x 9

CY7C1513KV18 – 4M x 18

CY7C1515KV18 – 2M x 36

Functional Description

The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common IO devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II read and write ports are independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1511KV18), 9-bit words (CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit words (CY7C1515KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K

), memory bandwidth is maximized while simplifying

and C system design by eliminating bus “turnarounds”.

Depth expansion is accomplished with port selects, which enables each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C

input clocks. All data outputs pass through output

(or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

and C

Table 1. Selection Guide

Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 333 300 250 200 167 MHz

Maximum Operating Current x8 600 560 490 430 380 mA

x9 600 560 490 430 380

x18 620 570 500 440 390

x36 850 790 680 580 510

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 001-00435 Rev. *E Revised March 30, 2009

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Logic Block Diagram (CY7C1511KV18)

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write

Reg

(20:0)

DOFF

[7:0]

Write

Reg

Write

Reg

Write

Reg

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[0]

REF

Write Add. Decode

Write

Reg

(20:0)

DOFF

[8:0]

Write

Reg

Write

Reg

Write

Reg

2M x 9 Array

Logic Block Diagram (CY7C1526KV18)

Document Number: 001-00435 Rev. *E Page 2 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Logic Block Diagram (CY7C1513KV18)

CLK

(19:0)

Gen.

Control

Logic

Address Register

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(19:0)

DOFF

[17:0]

Write

Reg

Write

Reg

Write

Reg

1M x 18 Array

512K x 36 Array

CLK

(18:0)

Gen.

Control

Logic

Address Register

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

144

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(18:0)

512K x 36 Array

DOFF

[35:0]

Write

Reg

Write

Reg

Write

Reg

Logic Block Diagram (CY7C1515KV18)

Document Number: 001-00435 Rev. *E Page 3 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Configuration

Note

1. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1511KV18 (8M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAWPSNWS

B NC NC NC A NC/288M K NWS

C NC NC NC V

D NC D4 NC V

E NC NC Q4 V

F NC NC NC V

G NC D5 Q5 V

H DOFF V

REF

DDQ

J NC NC NC V

K NC NC NC V

L NC Q6 D6 V

M NC NC NC V

N NC D7 NC V

DDQ

ANCAVSSNC NC D3

AAAVSSNC NC NC

P NC NC Q7 A A C A A NC NC NC

R TDO TCK A A A C AAATMSTDI

K NC/144M RPS AACQ

ANCNCQ3

DDQ

[1]

NC NC NC

NC D2 Q2

NC NC NC

DDQ

REF

NC Q1 D1

NC NC NC

NC NC Q0

NC NC D0

CY7C1526KV18 (8M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ AAWPSNC K NC/144M RPS AACQ

B NC NC NC A NC/288M K BWS

C NC NC NC V

D NC D5 NC V

E NC NC Q5 V

F NC NC NC V

G NC D6 Q6 V

H DOFF V

REF

DDQ

J NC NC NC V

K NC NC NC V

L NC Q7 D7 V

M NC NC NC V

N NC D8 NC V

DDQ

ANCAVSSNC NC D4

AAAVSSNC NC NC

ANCNCQ4

DDQ

NC NC NC

NC D3 Q3

NC NC NC

DDQ

REF

NC Q2 D2

NC NC NC

NC NC Q1

NC NC D1

P NC NC Q8 A A C A A NC D0 Q0

R TDO TCK A A A C AAATMSTDI

Document Number: 001-00435 Rev. *E Page 4 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Configuration (continued)

The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow.

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1513KV18 (4M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A WPS BWS

B NC Q9 D9 A NC K BWS

C NC NC D10 V

D NC D11 Q10 V

E NC NC Q11 V

F NC Q12 D12 V

G NC D13 Q13 V

H DOFF V

REF

DDQ

J NC NC D14 V

K NC NC Q14 V

L NC Q15 D15 V

M NC NC D16 V

N NC D17 Q16 V

DDQ

ANCAVSSNC Q7 D8

AAAVSSNC NC D1

P NC NC Q17 A A C A A NC D0 Q0

R TDO TCK A A A C AAATMSTDI

K NC/288M RPS AACQ

ANCNCQ8

DDQ

[1]

NC NC D7

NC D6 Q6

NC NC Q5

NC NC D5

DDQ

REF

NC Q4 D4

NC D3 Q3

NC NC Q2

NC Q1 D2

CY7C1515KV18 (2M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/288M A WPS BWS

B Q27 Q18 D18 A BWS

C D27 Q28 D19 V

D D28 D20 Q19 V

E Q29 D29 Q20 V

F Q30 Q21 D21 V

G D30 D22 Q22 V

H DOFF V

REF

DDQ

J D31 Q31 D23 V

K Q32 D32 Q23 V

L Q33 Q24 D24 V

M D33 Q34 D25 V

N D34 D26 Q25 V

DDQ

ANCAVSSD16 Q7 D8

AAAVSSQ10 D9 D1

K BWS

RPS A NC/144M CQ

KBWS0AD17Q17Q8

DDQ

Q16 D15 D7

Q15 D6 Q6

D14 Q14 Q5

Q13 D13 D5

DDQ

REF

D12 Q4 D4

Q12 D3 Q3

D11 Q11 Q2

D10 Q1 D2

P Q35 D35 Q26 A A C A A Q9 D0 Q0

R TDO TCK A A A C AAATMSTDI

Document Number: 001-00435 Rev. *E Page 5 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Definitions

Pin Name I/O Pin Description

[x:0]

WPS Input-

NWS

BWS0,

BWS

A Input-

[x:0]

RPS Input-

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

Input-

Synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. CY7C1511KV18 − D CY7C1526KV18 − D CY7C1513KV18 − D CY7C1515KV18 − D

[7:0] [8:0] [17:0] [35:0]

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

Synchronous

Input-

Synchronous

Input-

Synchronous

write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D Nibble Write Select 0, 1 − Active LOW (CY7C1511KV18 Only). Sampled on the rising edge of the K

and K

clocks

when write operations are active the current portion of the write operations. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device

. Used to select which nibble is written into the device

NWS

controls D

and NWS1 controls D

[3:0]

[7:4]

during

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when write operations are active. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1526KV18 − BWS CY7C1513KV18 − BWS0 controls D CY7C1515KV18 − BWS0 controls D BWS

controls D

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

[26:18]

ignores the corresponding byte of data and it is not written into the device

controls D

and BWS3 controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[35:27].

[17:9]

[17:9].

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

Synchronous

address inputs are multiplexed for both read and write operations. Internally, the device is organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1511KV18, 8M x 9 (4 arrays each of 2M x 9) for CY7C1526KV18, 4M x 18 (4 arrays each of 1M x 18) for CY7C1513KV18 and 2M x 36 (4 arrays each of 512K x 36) for CY7C1515KV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1511KV18 and CY7C1526KV18, 20 address inputs for CY7C1513KV18 and 19 address inputs for CY7C1515KV18. These inputs are ignored when the appropriate port is deselected.

Outputs-

Synchronous

Data Output Signals. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of the C and C single clock mode. On deselecting the read port, Q CY7C1511KV18 − Q CY7C1526KV18 − Q CY7C1513KV18 − Q CY7C1515KV18 − Q

[7:0]

[8:0] [17:0] [35:0]

clocks during read operations, or K and K when in

are automatically tristated.

[x:0]

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

Synchronous

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tristated following the next rising edge of the C clock. Each read access consists of a burst of four sequential transfers.

to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 10 for further details.

Input Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 10 for further details.

and to drive out data through Q edge of K.

when in single clock mode. All accesses are initiated on the rising

[x:0]

Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q

when in single clock mode.

[x:0]

Document Number: 001-00435 Rev. *E Page 6 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Pin Definitions (continued)

Pin Name I/O Pin Description

CQ Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 24.

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG.

TCK Input TCK Pin for JTAG.

TDI Input TDI Pin for JTAG.

TMS Input TMS Pin for JTAG.

NC N/A Not Connected to the Die. Can be tied to any voltage level.

NC/144M N/A Not Connected to the Die. Can be tied to any voltage level.

NC/288M N/A Not Connected to the Die. Can be tied to any voltage level.

REF

DDQ

Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock

Input PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C for the echo clocks are shown in the Switching Characteristics on page 24.

impedance. CQ, CQ, and Q between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document Number: 001-00435 Rev. *E Page 7 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Functional Overview

The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, CY7C1515KV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II completely eliminates the need to turn around the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1511KV18, four 9-bit data transfers in the case of CY7C1526KV18, four 18-bit data transfers in the case of CY7C1513KV18, and four 36-bit data transfers in the case of CY7C1515KV18 in two clock cycles.

This device operates with a read latency of one and half cycles when DOFF connected to V read latency of one clock cycle.

Accesses for both ports are initiated on the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K enced to the output clocks (C and C clock mode).

All synchronous data inputs (D controlled by the input clocks (K and K outputs (Q rising edge of the output clocks (C and C single clock mode).

All synchronous control (RPS through input registers controlled by the rising edge of the input clocks (K and K).

CY7C1513KV18 is described in the following sections. The same basic descriptions apply to CY7C1511KV18, CY7C1526KV18 and CY7C1515KV18.

pin is tied HIGH. When DOFF pin is set LOW or

then device behaves in QDR-I mode with a

) and all output timing is refer-

, or K and K when in single

) pass through input registers

[x:0]

) pass through output registers controlled by the

[x:0]

, WPS, BWS

). All synchronous data

, or K and K when in

) inputs pass

[x:0]

from the rising edge of the output clock (C or C

, or K or K when in single clock mode). To maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C

, or K and K when in single clock

mode).

When the read port is deselected, the CY7C1513KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the outputs following the next rising edge of the positive output clock (C). This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D the lower 18-bit write data register, provided BWS asserted active. On the subsequent rising edge of the negative input clock (K

) the information presented to D into the write data register, provided BWS active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Write accesses can be initiated on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When deselected, the write port ignores all inputs after the pending write operations are completed.

is latched and stored into

[17:0]

[1:0]

is also stored

[17:0]

are both asserted

[1:0]

are both

Read Operations

The CY7C1513KV18 is organized internally as four arrays of 1M x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q

using C as the output timing reference. On the subse-

[17:0]

quent rising edge of C, the next 18-bit data word is driven onto the Q are driven out onto Q

. This process continues until all four 18-bit data words

[17:0]

. The requested data is valid 0.45 ns

[17:0]

Byte Write Operations

Byte write operations are supported by the CY7C1513KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS

, which are sampled with each set of 18-bit data words.

BWS

Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature is used to simplify read, modify, or write operations to a byte write operation.

and

Document Number: 001-00435 Rev. *E Page 8 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Single Clock Mode

The CY7C1511KV18 is used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K

clocks. All timing parameters remain the same in this mode.

C/C To use this mode of operation, the user must tie C and C at power on. This function is a strap option and not alterable during device operation.

and

HIGH

Concurrent Transactions

The read and write ports on the CY7C1513KV18 operate independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Read access and write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports are deselected, the read port takes priority. If a read was initiated on the previous cycle, the write port takes priority (as read operations cannot be initiated on consecutive cycles). If a write was initiated on the previous cycle, the read port takes priority (as write operations cannot be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state results in alternating read or write operations being initiated, with the first access being a read.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, the allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

to allow the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C nized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K

Switching Characteristics on page 24.

. These are free running clocks and are synchro-

. The timing for the echo clocks is shown in the

PLL

These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF 20 μs of stable clock. The PLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 μs after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF behaves in QDR-I mode (with one cycle latency and a longer access time).

is tied HIGH, the PLL is locked after

pin. When the PLL is turned off, the device

Depth Expansion

The CY7C1513KV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.

Document Number: 001-00435 Rev. *E Page 9 of 31

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CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Application Example

R = 250ohms

Vt = Vddq/2

R = 50ohms

CC#

D A

SRAM #4

P S #

S #

CQ/CQ#

CC#

D A

SRAM #1

R P S #

P S #

S #

CQ/CQ#

BUS

MASTER

(CPU

ASIC)

DATA IN

DATA OUT

Address

RPS# WPS# BWS#

Source K

Source K#

Delayed K

Delayed K#

CLKIN/CLKIN#

Notes

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

↑represents rising edge.

3. Device powers up deselected with the outputs in a tristate condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the second read or write request.

Figure 1 shows four QDR-II used in an application.

Figure 1. Application Example

Truth Table

[2, 3, 4, 5, 6, 7]

D = X Q = High-Z

The truth table for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follows.

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

L-H H

[8]L [9]

D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑

Load address on the rising edge of K; input write data on two consecutive K and

rising edges.

Read Cycle:

L-H L

[9]

XQ(A) at C(t + 1)↑ Q(A + 1) at C(t + 2)↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3)↑

Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C

and C

rising edges.

NOP: No Operation L-H H H D = X

Standby: Clock Stopped Stopped X X Previous State Previous State Previous State Previous State

Document Number: 001-00435 Rev. *E Page 10 of 31

Q = High-Z

D = X Q = High-Z

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Cypress CY7C1513KV18, CY7C1511KV18, CY7C1526KV18, CY7C1515KV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Configurations

Functional Description

Logic Block Diagram (CY7C1511KV18)

Logic Block Diagram (CY7C1526KV18)

Logic Block Diagram (CY7C1513KV18)

Logic Block Diagram (CY7C1515KV18)

Pin Configuration

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

Pin Definitions

Functional Overview

Write Operations

Read Operations

Byte Write Operations

Single Clock Mode

Concurrent Transactions

Programmable Impedance

Echo Clocks

Depth Expansion

Application Example

Truth Table