Cypress CY7C150 User Manual

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CY7C150

Features

• Memory reset function

• 1024 x 4 static RA M for control store in high-spee d computers

• CMOS for optimum speed/power

• High speed

—10 ns (commercial) —12 ns (military)

• Low power

—495 mW (co mmercial) —550 mW (military)

• Separate inputs and outputs

• 5-volt power supply ±10% tolerance in both commercial and military

• Capable of withstanding greater than 2001V static dis-

charge

• TTL-compatible inputs and outputs

Functional Description

The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY 7C150 has a memory reset feature that allows the entire memory to be reset in two memory cycles.

Separate I/O paths eliminates the need to multiplex data in and data out, pro viding for simpl er board layout and faster system performance. Output s are three-stated d uring write, reset, deselect, or when output enable (OE for easy memory expansion.

Reset is initiat ed by sele cting the device (CS ing the reset (RS

) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with onl y selected dev ices being cle ared at any given time.

Writing to the device is accomplished when the chip select

) and write enable (W E) inpu ts are both L OW. Data o n the

(CS four data inputs (D0−D3) is written into the memory location specified on the address pins (A

Reading the device is accomplishe d by taking chip sele ct (CS) and output enable (OE HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O

through O3).

The output pins remain in high-impedance state when chip enable (CE (WE

) or output enable (OE) is HIGH, or write enable

) or reset (RS) is LOW.

A die coat is used to insure alpha immunity.

1Kx4 Static RAM

) LOW while write enable (WE) re mains

) is held HIGH, allowing

= LOW) and tak-

through A9).

Logic Block Diagram

D0D1D2D

DATAINPUT

CONTROL

RS CS

OE WE

C150–1

ROW DECODER

64x64 ARRA

SENSE AMPS

COLUMN

COLUMNDECODER

DECODER

A6A7A

PinConfiguration

DIP/SOIC

Top View

A A A A

A D D

O O

GND

7 8

6 7

7C150

24 23 22 21 20 19 18 17 16 15 14 13

C150-2

V A A

A RS CS WE

CC 2 1 0

2 3 2

Selection Guide

Maximum Access Time (ns) Commercial 10 12 15 25

Maximum Operating Current (mA) Commercial 90 90 90 90 90

7C150−10 7C150−12 7C150−15 7C150−25 7C150−35

Military 12 15 25 35

Military 100 100 100 100

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-05024 Rev. ** Revised August 24, 2001

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CY7C150

Maximum Ratings

(Above which the useful life may be im pai red. For user guidelines, not tested.)

Storage Temperature ......................................−65°C to+150°C

Ambient Temperature with

Power Applied...................................................−55°C to+125°C

Supply Voltage to Ground Potential

(Pin 24 to Pin 12)..................................................−0.5V to+7.0V

DC Voltage Applied to Outputs

in High Z State......................................................−0.5V to+7.0V

DC Input Voltage.................................................−3.0V to +7.0V

Output Current into Outputs (LOW).............................20 mA

Electrical Characteristics Ov er the Op erat ing Range

Static Discharge Voltage.......................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%

[1]

Military

Note:

1. T

is the “instant on” case temperature.

[2]

Ambient

Temperature V

−55°C to +125°C 5V ± 10%

Parameter Description Test Conditions

V I

Notes:

2. See the last page of this specification for Group A sub gro up test ing in for ma tion .

3. Not more than 1 output should be shorted at a time. Duration of the short circuit should not exceed 30 seconds.

Output HIGH Voltage VCC = Min., I Output LOW Current VCC = Min., I Input HIGH Level 2.0 V Input LOW Level −3.0 0.8 V Input Load Current GND < VI < V Output Current (High Z) VOL < V

Output Short Circuit Current VCC Operating Supply Current V

Output Disabled

[3]

VCC = Max., V

OUT

= Max., = 0 mA

= − 0.4 mA 2.4 V

= 12 mA 0.4 V

< VOH,

= GND −300 mA

OUT

Commercial 90 mA Military 100 mA

Capacitance

Parameter Description Test Conditions Max. Unit

OUT

Note:

4. Tested initially and after any design or process changes that may affect these parameters.

[4]

Input Capacitance TA = 25°C, f = 1 MHz, Output Capacitance 10 pF

= 5.0V

AC Test Loads and Waveforms

7C150

UnitMin. Max.

−10 +10 µA

−50 +50 µA

10 pF

OUTPUT

INCLUDING

30 pF

JIG AND

SCOPE

R1329

(a) (b)

Ω

R2 202

Ω

OUTPUT

5 pF

INCLUDING

JIG AND

SCOPE

R1329

Ω

R2 202

C150–3

3.0V

Ω

GND

10%

<3ns <3ns

ALL INPUT PULSES

90%

10%

C150–4

Equivalent to: THÉ VENIN EQUIVALENT

Ω

OUTPUT 1.9V

Document #: 38-05024 Rev. ** Page 2 of 11

125

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CY7C150

Switching Characteristics Over the Operating Range

7C150−10 7C150−12 7C150−15 7C150−25 7C150−35

Parameter Description

READ CYCL E

OHA

ACS

LZCS

HZCS

DOE

LZOE

HZOE

WRITE CYCLE

SCS

PWE

LZWE

HZWE

RESET CYCLE

RRC

SAR

SWER

SCSR

PRS

HCSR

HWER

HAR

LZRS

HZRS

Notes:

5. T est conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V , and outpu t loadin g of the spe cified I

OL/IOH

6. At any given temperature and voltage condition, t

7. t

HZCS

8. The internal write time of the memory is defined by the overlap of CS a write by going HIGH. The data input set -up and hold timing sho uld be reference to the ri sing edge of the signa l that terminates the write.

Read Cycle Time 10 12 15 25 35 ns Address to Data Valid 10 12 15 25 35 ns Output Hold from Address

Change CS LOW to Data Valid 8 10 12 15 20 ns CS LOW to Low Z CS HIGH to High Z OE LOW to Data Valid 6 8 10 15 20 ns OE LOW to Low Z OE HIGH to High Z

[8]

Write Cycle Time 10 12 15 25 35 ns CS LOW to Write End 6 8 11 15 20 ns Address Set-Up to Write End 8 10 13 20 30 ns Address Hold from Write End 2 2 2 5 5 ns Address Set-Up to Write Start 2 2 2 5 5 ns WE Pulse Width 6 8 11 15 20 ns Data Set-Up to Write End 6 8 11 15 20 ns Data Hold from Write End 2 2 2 5 5 ns WE HIGH to Low Z WE LOW to High Z

[6]

[6,7]

[6]

[6,7]

[6] [6,7]

2 2 2 2 2 ns

0 0 0 0 0 ns

Reset Cycle Time 20 24 30 50 70 ns Address Valid to Beginning of

Reset Write Enable HIGH to Beginning

of Reset Chip Select LOW to Begi nni ng of

Reset Reset Pulse Width 10 12 15 20 30 ns Chip Select Hold After End of

Reset Write Enable Hold After End of

Reset Address Hold After End of Reset 10 12 15 30 40 ns Reset HIGH to Output in Low Z Reset LOW to Output in

High Z

and 30-pF load c apacitan ce.

, t

HZOE

0 0 0 0 0 ns

8 12 15 30 40 ns

[6]

0 0 0 0 0 ns

is less than tLZ for any given dev ice.

HZR

, and t

[6,7]

are tested with CL = 5 pF as in part (b) o f AC Test Loads. Transition is meas ured ±500 mV from steady-stat e voltage.

HZWE

[2,5]

6 8 11 20 25 ns

6 8 9 20 25 ns

6 8 12 20 25 ns

LOW and WE LOW . Bot h signals must be L OW to initi ate a wr ite and eit her signal can terminat e

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Document #: 38-05024 Rev. ** Page 3 of 11

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Switching Waveforms

CY7C150

ReadCycleNo.1

ADDRESS

DATA OUT PREVIOUS DATA VALID DATA VALID

[9,10]

OHA

Read CycleNo. 2

[9,11]

ACS

DATA OUT

HIGH IMPEDANCE

LZCS

LZOE

DOE

DATA VALID

Write CycleNo.1(WE

Controlled)

[8]

SCS

HZWE

PWE

DATA

VALID

HIGH IMPEDANCE

LZWE

ADDRESS

DATA IN

DATA I/O

DATA UNDEFINED

HZOE

HZCS

C150-5

HIGH

IMPEDANCE

C150-6

C150-7

Notes:

9. WE

is HIGH for read cycle .

10. Device is continuously selected, CS

11. Address prior to or coincident with CS

Document #: 38-05024 Rev. ** Page 4 of 11

and OE = VIL.

transition LOW.

+ 7 hidden pages

Cypress CY7C150 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual