Cypress CY7C1480V25, CY7C1482V25, CY7C1486V25 User Manual
CY7C1480V25
CY7C1482V25
CY7C1486V25
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined Sync SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5V core power supply
• 2.5V/1.8V IO operation
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel
Pentium
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• Single cycle chip deselect
• CY7C1480V25, CY7C1482V25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1486V25
available in Pb-free and non-Pb-free 209-ball FBGA
package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode option
®
interleaved or linear burst sequences
®
Functional Description
The CY7C1480V25/CY7C1482V25/CY7C1486V25 SRAM
integrates 2M x 36/4M x 18/1M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE2 and CE3), Burst
1
Control inputs (ADSC
and BWE
include the Output Enable (OE
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
addresses can be internally generated as controlled by the
Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. This part supports Byte
Write operations (see “Pin Definitions” on page 7 and “Truth
Table” on page 10 for further details). Write cycles can be one
to two or four bytes wide, as controlled by the byte write control
inputs. When it is active LOW, GW
written.
The CY7C1480V25/CY7C1482V25/CY7C1486V25 operates
from a +2.5V core power supply while all outputs may operate
with either a +2.5 or +1.8V supply. All inputs and outputs are
JEDEC-standard JESD8-5-compatible.
), and Global Write (GW). Asynchronous inputs
, ADSP, and ADV), Write Enables (BWX,
[1]
) and the ZZ pin.
) or
) is active. Subsequent burst
causes all bytes to be
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 450 450 400 mA
Maximum CMOS Standby Current 120 120 120 mA
Note
1. For best practices recommendations, refer to the Cypress application note System Design Guidelines at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05282 Rev. *H Revised April 23, 2007
[+] Feedback
Logic Block Diagram – CY7C1480V25 (2M x 36)
CY7C1480V25
CY7C1482V25
CY7C1486V25
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BW
BW
BWE
GW
CE
CE
CE
ADDRESS
REGISTER
D,
D
DQP
DQ
D
C
B
A
1
2
3
OE
ZZ
BYTE
WRITE REGISTER
C,DQP
DQ
BYTE
WRITE REGISTER
B,DQP
DQ
BYTE
WRITE REGISTER
DQ A,DQP
BYTE
WRITE REGISTER
SLEEP
CONTROL
C
B
A
ENABLE
REGISTER
2
BURST
COUNTER
AND
CLR
LOGIC
PIPELINED
ENABLE
A
[1:0]
Q1
Q0
D ,DQP
DQ
D
BYTE
WRITE DRIVER
C,DQP
C
DQ
BYTE
WRITE DRIVER
B,DQP
B
DQ
BYTE
WRITE DRIVER
A,DQP
A
DQ
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
DQP
DQP
A
B
C
D
Logic Block Diagram – CY7C1482V25 (4M x 18)
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BWE
GW
CE
CE2
CE3
OE
B
A
1
ZZ
ADDRESS
REGISTER
DQB,DQP
B
WRITE REGISTER
DQA,DQP
A
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
2
BURST
COUNTER AND
LOGIC
CLR
PIPELINED
ENABLE
A[1:0]
Q1
Q0
WRITE DRIVER
WRITE DRIVER
DQB,DQP
DQA,DQP
B
MEMORY
A
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
DQP
A
B
INPUT
REGISTERS
Document #: 38-05282 Rev. *H Page 2 of 32
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Logic Block Diagram – CY7C1486V25 (1M x 72)
CY7C1480V25
CY7C1482V25
CY7C1486V25
A0, A1,A
MODE
ADV
ADSC
ADSP
BW
BW
BW
BW
BW
BW
BW
BW
BWE
ADDRESS
REGISTER
CLK
DQH, DQP
H
G
F
E
D
C
B
A
GW
CE1
CE2
CE3
OE
WRITE DRIVER
DQF, DQP
WRITE DRIVER
DQF, DQP
WRITE DRIVER
DQE, DQP
WRITE DRIVER
DQD, DQP
WRITE DRIVER
DQC, DQP
WRITE DRIVER
DQB, DQP
WRITE DRIVER
DQA, DQP
WRITE DRIVER
ENABLE
REGISTER
H
F
F
E
D
C
B
A
COUNTER
CLR
PIPELINED
ENABLE
BINARY
A[1:0]
Q1
Q0
DQH, DQP
H
WRITE DRIVER
DQG, DQP
G
WRITE DRIVER
DQF, DQP
F
WRITE DRIVER
E
DQE, DQP
BYTE
“a”
WRITE DRIVER
WRITE DRIVER
DQD, DQP
WRITE DRIVER
DQC, DQP
WRITE DRIVER
DQB, DQP
WRITE DRIVER
DQA, DQP
WRITE DRIVER
MEMORY
ARRAY
D
C
SENSE
B
A
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
A
B
C
D
E
F
G
H
ZZ
SLEEP
CONTROL
Document #: 38-05282 Rev. *H Page 3 of 32
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Pin Configurations
100-Pin TQFP Pinout
CY7C1480V25
CY7C1482V25
CY7C1486V25
DQP
DQC
DQc
V
DDQ
V
SSQ
DQC
DQC
DQC
DQC
V
SSQ
V
DDQ
DQC
DQC
NC
V
NC
V
DQD
DQD
V
DDQ
V
SSQ
DQD
DQD
DQD
DQD
V
SSQ
V
DDQ
DQD
DQD
DQPD
1CE2
A
A
BWD
BWC
CE
100999897969594939291908988878685848382
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DD
15
16
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BWB
CY7C1480V25
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
SS
BWA
CE3VDDV
(2M x 36)
SS
A
A
DD
V
V
CLKGWBWEOEADSC
A
A
ADSP
AAAAA
ADV
A
A
81
DQPB
80
DQB
79
DQB
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
DQB
DQB
DQB
DQB
V
SSQ
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
DQPA
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQB
V
SSQ
V
DDQ
DQB
DQB
NC
V
NC
V
DQB
DQB
V
DDQ
V
SSQ
DQB
DQB
DQPB
NC
V
SSQ
V
DDQ
NC
NC
NC
B
DD
SS
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1482V25
SS
CE3VDDV
(4M x 18)
CLKGWBWEOEADSC
ADSP
31323334353637383940414243444546474849
MODE
AAA
1A0
A
A
A
A
A
A
DD
V
AAAAA
SS
V
ADV
A
A
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
50
A
A
Document #: 38-05282 Rev. *H Page 4 of 32
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Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1480V25 (2M x 36)
CY7C1480V25
CY7C1482V25
CY7C1486V25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
234 5671
NC/288M
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
A
CE
CE2
V
DDQ
V
C
C
C
C
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
D
D
D
D
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CY7C1482V25 (4M x 18)
234 5671
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
A
A
CE
CE2
V
DDQ
V
B
B
B
B
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC/288M
NC/144M
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
891011
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADSC
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC/1G DQP
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
NC
NC/576M
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
AA
891011
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
ADSC
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC/1G DQP
NC
NC
NC
NC
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
NC/576M
DQ
A
DQ
A
DQ
A
DQ
A
ZZ
NCV
NC
NC
NC
NC
A
AA
A
Document #: 38-05282 Rev. *H Page 5 of 32
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Pin Configurations (continued)
123456789 1110
DQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQ
DQ
DQ
DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
DQP
DQ
DQ
DQ
DQ
DQ
G
G
G
G
C
C
C
C
G
DQ
G
DQ
G
DQ
G
DQP
G
DQ
DQ
DQ
DQ
C
C
C
C
C
NC
DQ
H
H
H
H
D
D
D
D
D
DQ
DQ
DQ
DQP
DQ
DQ
DQ
DQ
H
H
H
H
H
D
D
D
D
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1486V25 (1M × 72)
A
BWS
BWS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CLK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
A
AA
TMS
CE
BWS
C
BWS
H
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
2
G
D
ADSP
NC/288M
NC/144M
NC/1G
V
V
V
V
V
NC MODE
A
TDI TDO TCK
ADSC
BWE
CE
1
OE
DD
DD
SS
DD
SS
DD
V
NC
NC
NC
NC
V
NC
NC
NC
ZZ
V
DD
SS
DD
DD
SS
DD
SS
V
SS
V
V
V
V
V
NC
AA A
A
AA
AA
A1
A0
ADV A
A
NC/576M
GW
V
DD
V
SS
V
DD
V
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
SS
CE
BWS
BWS
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
AA
3
B
E
BWS
BWS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
CY7C1480V25
CY7C1482V25
CY7C1486V25
DQ
DQ
F
DQ
A
DQ
DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
DQP
DQ
DQ
DQ
DQ
DQ
B
B
B
B
F
F
F
F
F
DQ
DQ
DQ
DQP
DQ
DQ
DQ
DQ
B
B
B
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
DQ
E
DQ
E
DQ
E
DQ
E
B
F
F
F
F
A
A
A
A
E
E
E
E
E
Document #: 38-05282 Rev. *H Page 6 of 32
[+] Feedback
Pin Definitions
Pin Name I/O Description
, A1, A Input-
A
0
BW
, BWB, BWC,
A
, BWE, BWF,
BW
D
BW
, BW
G
GW
H
Synchronous
Input-
Synchronous
Input-
Synchronous
BWE
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
OE Input-
Asynchronous
ADV Input-
Synchronous
ADSP Input-
Synchronous
ADSC
Input-
Synchronous
ZZ Input-
Asynchronous
DQs, DQPs
I/O-
Synchronous
V
DD
V
SS
[2]
V
SSQ
V
DDQ
Note
2. Applicable for TQFP package. For BGA package V
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP
or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BW
BWE
).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input. Captures all synchronous inputs to the device. Also increments the burst
counter when ADV
is asserted LOW during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE
is sampled only when a new external address is loaded.
1
and CE3 to select/deselect the device. ADSP is ignored if CE1 is
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
new external address is loaded.
and CE3 to select/deselect the device. CE2 is sampled only when a
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
new external address is loaded.
and CE2 to select/deselect the device. CE3 is sampled only when a
1
Output Enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when
emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP
asserted, only ADSP
is recognized.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull down.
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE
the pins behave as outputs. When HIGH, DQs and DQP
serves as ground for the core and the IO circuitry.
SS
CY7C1480V25
CY7C1482V25
CY7C1486V25
and
X
and ADSC are both
. When OE is asserted LOW,
are placed in a tri-state condition.
X
Document #: 38-05282 Rev. *H Page 7 of 32
[+] Feedback
CY7C1480V25
CY7C1482V25
CY7C1486V25
Pin Definitions (continued)
Pin Name I/O Description
MODE Input Static Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
TDO JTAG Serial
Output
Synchronous
TDI JTAG Serial Input
Synchronous
TMS JTAG Serial Input
Synchronous
TCK JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.
connected to V
expansion pins and are not internally connected to the die.
. This pin is not available on TQFP packages.
SS
. This pin is not available on
DD
. This pin is not available on
DD
DD
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250 MHz device).
The CY7C1480V25/CY7C1482V25/CY7C1486V25 supports
secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that use a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP
Strobe (ADSC
sequence is controlled by the ADV
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
, CE2, CE3 are all asserted active, and (3) the write signals
CE
1
(GW
, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs (A) is
stored into the address advancement logic and the Address
Register while being presented to the memory array. The
). Address advancement through the burst
) overrides all byte write inputs and writes data to
) or the Controller Address
input. A two-bit on-chip
, CE2, CE3) and an
1
) provide easy bank
or ADSC is asserted LOW, (2)
) is 3.0 ns
CO
is ignored if CE
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (250-MHz device) if OE
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported. After the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
, CE2, CE3 are all asserted active. The address
1
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The write signals (GW
ADV
inputs are ignored during this first cycle.
ADSP
-triggered write accesses require two clock cycles to
complete. If GW
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW
then the write operation is controlled by the BWE
signals.
The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides
Byte Write capability that is described in the “Truth Table for
1
Read/Write” on page 11. Asserting the Byte Write Enable input
(BWE
) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during
a byte write operation remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a
1
common IO device, the Output Enable (OE
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
is asserted LOW on the second clock rise, the
is asserted LOW, and
, BWE, and BWX) and
is active
is HIGH,
and BW
) must be
X
Document #: 38-05282 Rev. *H Page 8 of 32
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CY7C1480V25
CY7C1482V25
CY7C1486V25
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE
.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the write inputs (GW
BWE
, and BWX) are asserted active to conduct a write to the
desired byte(s). ADSC
is asserted LOW, (2) ADSP is
, CE2, CE3 are all asserted active,
1
-triggered write accesses need a single
clock cycle to complete. The address presented to A is loaded
into the address register and the address advancement logic
while being delivered to the memory array. The ADV
input is
ignored during this cycle. If a global write is conducted, the
data presented to the DQs is written into the corresponding
address location in the memory core. If a byte write is
conducted, only the selected bytes are written. Bytes not
selected during a byte write operation remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Because CY7C1480V25/CY7C1482V25/CY7C1486V25 is a
common IO device, the Output Enable (OE
) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so tri-states the output drivers. As a safety precaution,
DQs are automatically tri-stated whenever a write cycle is
detected, regardless of the state of OE
.
Burst Sequences
The CY7C1480V25/CY7C1482V25/CY7C1486V25 provides
a two-bit wraparound counter, fed by A1: A0, that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel
Pentium applications. The linear burst sequence is designed
to support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Asserting ADV
LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
,
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
, CE2, CE3, ADSP, and ADSC must
1
after the ZZ input
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
DD
)
Third
Address
A1: A0
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Fourth
Address
A1: A0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 38-05282 Rev. *H Page 9 of 32
Sleep Mode Standby Current ZZ > VDD – 0.2V 120 mA
Device Operation to ZZ ZZ > VDD – 0.2V 2t
ZZ Recovery Time ZZ < 0.2V 2t
CYC
ZZ Active to Sleep Current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to Exit Sleep Current This parameter is sampled 0 ns
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CY7C1480V25
CY7C1482V25
CY7C1486V25
Truth Table
The truth table for CY7C1480V25, CY7C1482V25, and CY7C1486V25 follows.
Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
[3, 4, 5, 6, 7]
Notes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
5. The DQ pins are controlled by the current cycle and the OE
6. The SRAM always initiates a read cycle when ADSP
7. OE
= L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
after the ADSP
don't care for the remainder of the write cycle
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE
or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a
signal. OE is asynchronous and is not sampled with the clock.
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
is active (LOW).
Document #: 38-05282 Rev. *H Page 10 of 32
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