Cypress CY7C1474V33, CY7C1472V33, CY7C1470V33 User Manual
p
CY7C1470V33
a
b
c
d
C
C
Pi
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output time
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN
• Synchronous self-timed writes
• CY7C1470V33, CY7C1472V33 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V33
available in lead-free and non-lead-free 209 ball FBGA
package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
) pin to suspend operation
elined SRAM with NoBL™ Architecture
CY7C1472V33
CY7C1474V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1470V33, CY7C1472V33,
and CY7C1474V33 are pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BWh for CY7C1474V33, BWa–BWd for CY7C1470V33
a
and BW
input. All writes are conducted with on-chip synchronous
–BWb for CY7C1472V33) and a Write Enable (WE)
a
self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram-CY7C1470V33 (2M x 36)
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05289 Rev. *I Revised June 20, 2006
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
[+] Feedback
s
P
a
P
b
P
c
P
d
P
e
P
f
P
g
P
h
C
C
a
b
C
C
Logic Block Diagram-CY7C1472V33 (4M x 18)
CY7C1470V33
CY7C1472V33
CY7C1474V33
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A1
D1D0Q1
A0
BURST
LOGIC
WE
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Logic Block Diagram-CY7C1474V33 (1M x 72)
A0, A1, A
MODE
C
LK
EN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
D1D0Q1
BURST
LOGIC
A1'
A0'
Q0
O
U
T
P
S
U
E
T
N
S
WRITE
DRIVERS
A1'
A0'
Q0
MEMORY
ARRAY
INPUT
REGISTER 1
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
REGISTER 0
INPUT
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
E
E
R
I
N
G
E
DQP
F
DQP
E
R
S
E
O
U
T
P
S
U
ARRAY
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
WE
INPUT
E
REGISTER 1
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
D
A
T
A
S
T
E
E
R
N
G
INPUT
REGISTER 0
O
U
T
P
U
T
B
DQ
U
F
DQ
F
DQ
E
R
DQ
S
I
DQ
DQ
E
DQ
DQ
DQ
E
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 500 500 450 mA
Maximum CMOS Standby Current 120 120 120 mA
Document #: 38-05289 Rev. *I Page 2 of 29
[+] Feedback
a
Pin Configurations
100-pin TQFP Packages
CY7C1470V33
CY7C1472V33
CY7C1474V33
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWa
BWd
BWc
BWb
CE3VDDV
SS
CLKWECEN
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
CY7C1470V33
(2M x 36)
31323334353637383940414243444546474849
OE
ADV/LD
A
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
SS
VDDV
CE
BW
NC
NC
CY7C1472V33
(4M x 18)
CLKWECEN
OE
ADV/LD
A
A
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
MODE
AAA
0
A
A1A
SS
DD
V
V
NC(288)
NC(144)
AAA
A
A
A
A
A
A
A
AAA
MODE
1A0
A
AAA
A
A
A
DD
SS
V
V
NC(288)
NC(144)
A
A
A
Document #: 38-05289 Rev. *I Page 3 of 29
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Pin Configurations (continued)
2345671
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
A
A
CE
CE2
V
V
c
V
c
V
c
V
c
NC
V
d
V
d
V
d
V
d
V
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470V33 (2M x 36)
CE
b
CLK
a
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
BW
d
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CY7C1470V33
CY7C1472V33
CY7C1474V33
891011
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC
NC
NC DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
b
b
b
b
a
a
a
a
DQ
DQ
DQ
DQ
ZZ
DQ
DQ
DQ
DQ
DQP
NC/288M
b
b
b
b
b
a
a
a
a
a
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1472V33 (4M x 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
A
CE
CE2
V
DDQ
V
b
b
b
b
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
BW
1
b
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
a
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
891011
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQP
NC
NC
NC
NC
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
A
NC
a
DQ
a
DQ
a
DQ
a
DQ
a
ZZ
NCV
NC
NC
NC
NC
NC/288M
AA
Document #: 38-05289 Rev. *I Page 4 of 29
[+] Feedback
Pin Configurations (continued)
1234 56789 1110
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1474V33 (1M x 72)
CY7C1470V33
CY7C1472V33
CY7C1474V33
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
AAAA
BWScBWS
BWS
V
V
DDQ
V
V
DDQ
V
V
DDQ
CLK
V
DDQ
V
V
DDQ
V
V
DDQ
V
NC/144M
AA
TMS
SS
SS
SS
SS
SS
SS
CE
2
g
NC
V
V
DDQ
SS
DDQ
SS
DDQ
NC/576M
d
NC/1G
BWS
h
V
V
V
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC MODE
A
TDI TDO TCK
ADV/LD
NC
WE
CE
OE
V
V
V
V
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
NC
A A NC/288M
A
AA
AA
A1
A0
A
NC
1
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
CE
3
BWS
BWS
b
BWSeBWS
V
V
V
V
V
V
NC
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
NC
SS
SS
SS
SS
V
V
V
V
V
V
V
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
V
AA
SS
SS
SS
SS
SS
SS
DQb
DQb
f
DQb
a
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Document #: 38-05289 Rev. *I Page 5 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
A
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADV/LD Input-
CLK Input-
CE
1
CE
2
CE
3
OE
CEN
DQ
S
DQP
X
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
TDO JTAG Serial
TDI JTAG Serial Input
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Synchronous
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
I/O-
Synchronous
I/O-
Synchronous
Output
Synchronous
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
c
controls DQ
and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
f
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, acti ve LOW . Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
new address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a
should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
during the previous clock rise of the read cycle. The direction of the pins is
[17:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
from a deselected state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQX. During write
sequences, DQP
and DQP
is controlled by BW
is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg
d
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
a
, DQPh is controlled by BWh.
g
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Document #: 38-05289 Rev. *I Page 6 of 29
[+] Feedback
Pin Definitions (continued)
Pin Name I/O Type Pin Description
TMS T est Mode Select
Synchronous
TCK JTAG Clock Clock input to the JTAG circuitry.
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
NC – No connects. This pin is not connected to the die.
NC(144M,
– These pins are not connected. They will be used for expansion to the 144M, 288M, 576M, and
288M,
576M, 1G)
ZZ Input-
Asynchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
1G densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
CY7C1470V33
CY7C1472V33
CY7C1474V33
Functional Overview
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 3.0 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
, CE2, CE3) active at the rising edge of the clock. If Clock
(CE
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
Writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 3.0 ns
). If CEN is HIGH, the clock
). BW
can be used to
[x]
). All
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
(250-MHz device) provided OE is active LOW. After the first
clock of the Read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33
have an on-chip burst counter that allows the user the ability
to supply a single address and conduct up to four Reads
without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load a new address into the SRAM, as
described in the Single Read Access section above. The
sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enables inputs or WE
will increment the internal burst counter regardless of
. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V33). In addition, the address for the subsequent
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V33 and DQ
a,b,c,d
for CY7C1474V33,
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
Document #: 38-05289 Rev. *I Page 7 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
On the next clock rise the data presented to DQ and DQP
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V33 & DQ
a,b,c,d
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V33) (or a subset for byte write operations, see
for CY7C1474V33,
a,b
/DQP
a,b
for
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
CY7C1470V33 and BW
CY7C1470V33, CY7C1472V33, and CY7C1474V33 provides
for CY7C1474V33, BW
for CY7C1472V33) signals. The
a,b
a,b,c,d
for
Byte Write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE
the selected Byte Write Select (BW
) input will selectively write
) with
to only the desired bytes. Bytes not selected during a Byte
Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple Byte Write operations.
Because the CY7C1470V33, CY7C1472V33, and
CY7C1474V33 are common I/O devices, data should not be
driven into the device while the outputs are active. The Output
Enable (OE
to the DQ
CY7C1474V33, DQ
DQ
a,b
the output drivers. As a safety precaution, DQ
(DQ
DQ
a,b,c,d
CY7C1472V33) are automatically tri-stated during the data
) can be deasserted HIGH before presenting data
/DQP
a,b
a,b,c,d,e,f,g,h
/DQP
and DQP (DQ
a,b,c,d
for CY7C1472V33) inputs. Doing so will tri-state
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V33 and DQ
a,b,c,d
a,b,c,d,e,f,g,h
/DQP
a,b,c,d
for CY7C1474V33,
/DQP
for CY7C1470V33 and
a,b,c,d,e,f,g,h
and DQP
/DQP
a,b
a,b
for
for
portion of a Write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
CY7C1474V33, BW
CY7C1472V33) inputs must be driven in each cycle of the
for CY7C1470V33 and BW
a,b,c,d
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Third
Address
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
driven HIGH on the subsequent clock rise, the Chip Enables
, CE2, and CE3) and WE inputs are ignored and the burst
(CE
1
counter is incremented. The correct BW
(BW
a,b,c,d,e,f,g,h
for
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 120 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
a,b
Fourth
Address
Fourth
Address
ns
ns
ns
for
Document #: 38-05289 Rev. *I Page 8 of 29
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CY7C1470V33
CY7C1472V33
CY7C1474V33
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Operation Address Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue
None X L H X X X L L-H Tri-State
Deselect Cycle
Read Cycle
External L L L H X L L L-H Data Out (Q)
(Begin Burst)
Read Cycle
Next X L H X X L L L-H Data Out (Q)
(Continue Burst)
NOP/Dummy Read
External L L L H X H L L-H Tri-State
(Begin Burst)
Dummy Read
Next X L H X X H L L-H Tri-State
(Continue Burst)
Write Cycle
External L L L L L X L L -H Data In (D)
(Begin Burst)
Write Cycle
Next X L H X L X L L-H Data In (D)
(Continue Burst)
NOP/Write Abort
None L L L L H X L L-H Tri-State
(Begin Burst)
Write Abort
Next X L H X H X L L-H Tri-State
(Continue Burst)
Ignore Clock Edge
Current X L X X X X H L-H -
(Stall)
Sleep Mode None X H X X X X X X Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQP
7. OE
is inactive or when the device is deselected, and DQs= data when OE is active.
and BW
. See Write Cycle Description table for details.
[a:d]
stands for ALL Chip Enables active. BWx = 0 signifies at least one B yte W rite Select is active, BWx = Valid
signal.
.
= tri-state when OE
[a:d]
Document #: 38-05289 Rev. *I Page 9 of 29
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