Cypress CY7C1474BV33, CY7C1470BV33, CY7C1472BV33 User Manual
72-Mbit (2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Features
■ Pin-compatible and functionally equivalent to ZBT™
■ Supports 250 MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte Write capability
■ Single 3.3V power supply
■ 3.3V/2.5V IO power supply
■ Fast clock-to-output time
❐ 3.0 ns (for 250-MHz device)
■ Clock Enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ CY7C1470BV33, CY7C1472BV33 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1474BV33
available in Pb-free and non-Pb-free 209-ball FBGA package
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst capability—linear or interleaved burst order
■ “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are 3.3V , 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back re ad
or write operations with no wait states. The CY7C1470BV33,
CY7C1472BV33, and CY7C1474BV33 are equipped with the
advanced (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data in
systems that require frequent read or write transitions. The
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clo ck. The clock
input is qualified by the Clock Enable (CEN
deasserted suspends operation and extends the previou s clock
cycle.
Write operations are controlled by the Byte Write Selects
–BWd for CY7C1470BV33, BWa–BW
(BW
a
CY7C1472BV33, and BW
Write Enable (WE
) input. All writes are conducted with on-chip
–BWh for CY7C1474BV33) and a
a
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
) signal, which when
for
b
, CE2, CE3) and an
1
) provide for easy bank
Selection Guide
Description 250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 500 500 450 mA
Maximum CMOS Standby Current 120 120 120 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-15031 Rev. *C Revised February 29, 2008
[+] Feedback
CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Logic Block Diagram – CY7C1470BV33 (2M x 36)
s
P
a
P
b
Pc
Pd
C
C
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQ
s
DQ
P
a
DQ
P
b
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1D0Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
C
LK
C
EN
WRITE
DRIVERS
ZZ
Sleep
Control
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADDRESS
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
Logic Block Diagram – CY7C1472BV33 (4M x 18)
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQ
U
DQ
F
DQ
F
DQ
E
DQ
R
S
E
Document #: 001-15031 Rev. *C Page 2 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Logic Block Diagram – CY7C1474BV33 (1M x 72)
A0, A1, A
MODE
C
CLK
CEN
ADV/LD
a
BW
BW
b
BW
c
BW
d
BW
e
BW
f
g
BW
BW
h
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
INPUT
REGISTER 0
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP
a
b
c
d
e
f
g
h
E
Document #: 001-15031 Rev. *C Page 3 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations
AAA
A
A
1A0
V
SS
V
DD
A
AAA
A
A
V
DDQ
V
SS
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
NC
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
V
SS
V
DDQ
V
DDQ
V
SS
DQc
DQc
V
SS
V
DDQ
DQc
V
DD
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
V
SS
V
DDQ
A
A
CE
1CE2
BWa
CE
3
VDDV
SS
CLKWECEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
A
A
ADV/LD
ZZ
CY7C1470BV33
A
AAA
A
1A0
V
SS
V
DD
A
A
AAA
A
A
NC
NC
V
DDQ
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
DD
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1CE2
NC
NC
BW
bBWa
CE
3
VDDV
SS
CLKWECEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
A
A
ADV/LD
ZZ
MODE
CY7C1472BV33
BWd
MODE
BWc
DQc
DQc
DQc
DQc
DQPc
DQd
DQd
DQd
DQPb
DQb
DQa
DQa
DQa
DQa
DQPa
DQb
DQb
(2M x 36)
(4M x 18)
BWb
NC
NC
NC
DQc
NC
NC(288)
NC(144)
A
NC(288)
NC(144)
DQPd
A
A
A
A
A
Figure 1. 100-Pin TQFP Pinout
Document #: 001-15031 Rev. *C Page 4 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470BV33 (2M x 36)
CY7C1472BV33 (4M x 18)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
DQP
c
DQ
c
DQP
d
NC
DQ
d
A
CE
1
BW
b
CE
3
BW
c
CEN
A
CE2
DQ
c
DQ
d
DQ
d
MODE
NC
DQ
c
DQ
c
DQ
d
DQ
d
DQ
d
A
V
DDQ
BW
d
BW
a
CLK
WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCKA0
V
SS
TDI
A
A
DQ
c
V
SS
DQ
c
V
SS
DQ
c
DQ
c
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
d
DQ
d
NC/144M
NC
V
DDQ
V
SS
TMS
891011
NC/288M
A
A
ADV/LD
NC
OE
A
A
NC
V
SS
V
DDQ
NC DQP
b
V
DDQ
V
DD
DQ
b
DQ
b
DQ
b
NC
DQ
b
NC
DQ
a
DQ
a
V
DD
V
DDQ
V
DD
V
DDQ
DQ
b
V
DD
NC
V
DD
DQ
a
V
DD
V
DDQ
DQ
a
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
a
V
DDQ
AA
V
SS
A
A
A
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQP
a
DQ
a
A
V
DDQ
A
A
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
NC
NC
DQP
b
NC
DQ
b
A
CE
1
CE
3
BW
b
CEN
A
CE2
NC
DQ
b
DQ
b
MODE
NC
DQ
b
DQ
b
NC
NC
NC
A
V
DDQ
BW
a
CLK
WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCKA0
V
SS
TDI
A
A
DQ
b
V
SS
NC V
SS
DQ
b
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
b
NC
NC/144M
NC
V
DDQ
V
SS
TMS
891011
NC/288M
A A
ADV/LD
A
OE
A
A
NC
V
SS
V
DDQ
NC DQP
a
V
DDQ
V
DD
NC
DQ
a
DQ
a
NC
NC
NC
DQ
a
NC
V
DD
V
DDQ
V
DD
V
DDQ
DQ
a
V
DD
NC
V
DD
NCV
DD
V
DDQ
DQ
a
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
NC
V
DDQ
AA
V
SS
A
A
A
DQ
a
NC
NC
ZZ
DQ
a
NC
NC
DQ
a
A
V
DDQ
A
A
NC
NC
Document #: 001-15031 Rev. *C Page 5 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
Pin Configurations (continued)
CY7C1474BV33 (1M × 72)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
123456789 1110
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DQPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQPd
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DQPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQPa
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
AAAA
NC
NC
NC/144M
A A NC/288M
A
AA
AA
A
A1
A0
A
AA
AA
A
NC/576M
NC
NC
NC
NC
NC
BWS
b
BWS
f
BWSeBWS
a
BWScBWS
g
BWS
d
BWS
h
TMS
TDI TDO TCK
NC
NC MODE
NC
CEN
V
SS
NC
CLK
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/1G
V
DD
NC
OE
CE
3
CE
1
CE
2
ADV/LD
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
V
SS
NC
V
DDQ
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Document #: 001-15031 Rev. *C Page 6 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
T able 1. Pin Definitions
Pin Name IO Type Pin Description
A0
A1
Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK.
A
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADV/LD Input-
Input-
Synchronous
Input-
Synchronous
Synchronous
Byte Write Select Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
c
controls DQ
and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
f
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, Active LOW . Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input Used to Advance the On-chip Address Counter or Load a New
Address. When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD
must be driven LOW to load a new address.
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, Active LOW . Sampled on the rising edge of CLK. Used in conjunction with
and CE3 to select or deselect the device.
CE
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select or deselect the device.
1
Chip Enable 3 Input, Active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select or deselect the device.
1
Output Enable, Active LOW. Combined with the synchronous logic block inside the device to
control the direction of the IO pins. When LOW, the IO pins are enabled to behave as outputs.
When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
DQ
DQP
Input-
Synchronous
S
X
IO-
Synchronous
IO-
Synchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE
during the previous clock rise of the read cycle. The direction of the pins is
[17:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
.
Bidirectional Data P arity IO Lines. Functionally , these signals are identical to DQX. During write
sequences, DQP
and DQP
is controlled by BW
is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf, DQPg
d
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
a
, DQPh is controlled by BWh.
g
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the inte rleaved burst order .
Pulled LOW selects the linear burst order. MODE must not change states during operation. When
left floating MODE defaults HIGH, to an interleaved burst order.
TDO JTAG Serial
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK.
Output
Synchronous
TDI JT AG Serial Input
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK.
Synchronous
Document #: 001-15031 Rev. *C Page 7 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
T able 1. Pin Definitions (continued)
Pin Name IO Type Pin Description
TMS T est Mode Select
This Pin Controls the Test Access Port State Machine. Sampled on the rising edge of TCK.
Synchronous
TCK JTAG Clock Clock Input to the JTAG Circuitry.
V
V
V
DD
DDQ
SS
Power Supply Power Supply Inputs to the Core of the Device.
IO Power Supply Power Supply for the IO Circuitry.
Ground Ground for the Device. Should be connected to ground of the system.
NC – No Connects. This pin is not connected to the die.
NC(144M,
288M,
– These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and
1G densities.
576M, 1G)
ZZ Input-
Asynchronous
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin must be LOW or left floating.
ZZ pin has an internal pull-down.
Functional Overview
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during read or write transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 3.0 ns
(250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If CEN is
1
active LOW and ADV/LD
presented to the device is latched. The access can either be a
read or write operation, depending on the status of the Write
Enable (WE
tions.
). BW
can be used to conduct Byte Write opera-
[x]
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
deasserted HIGH, and (4) ADV/LD
address presented to the address inputs is latched into the
Address Register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
requested data is allowed to propagate through the output
are ALL asserted active, (3) the input signal WE is
3
). If CEN is HIGH, the clock signal
. All data outputs
is asserted LOW, the address
). All
, CE2, CE3) and an
1
) simplify depth expansion. All
is asserted LOW, (2) CE1, CE2,
is asserted LOW. The
register and onto the data bus within 3.0 ns (250-MHz device)
provided OE
access the output buffers are controlled by OE
control logic. OE
is active LOW. After the first clock of the read
and the internal
must be driven LOW to drive out the requested
data. During the second clock, a subsequent operation (read,
write, or deselect) can be initiated. Deselecting the device is also
pipelined. Therefore, when the SRAM is deselected at clock rise
by one of the chip enable signals, its output tri-states following
the next clock rise.
Burst Read Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four reads without reasserting
the address inputs. ADV/LD
must be driven LOW to load a new
address into the SRAM, as described in the Single Read
Accesses section. The sequence of the burst counter is deter-
mined by the MODE input signal. A LOW input on MODE selects
a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD
regardless of the state of chip enables inputs or WE
increments the internal burst counter
. WE is
latched at the beginning of a burst cycle. Therefore, the type of
access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
asserted LOW. The address presented to the address inputs is
are ALL asserted active, and (3) the signal WE is
3
loaded into the Address Register. The write signals are latched
into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1472BV33, and DQ
a,b,c,d
/DQP
for CY7C1470BV33, DQ
a,b,c,d
CY7C1474BV33). In addition, the address for the subsequent
is asserted LOW, (2) CE1, CE2,
input signal. This
and DQP
a,b,c,d,e,f,g,h
/DQP
/DQP
a,b
a,b,c,d,e,f,g,h
a,b
for
for
Document #: 001-15031 Rev. *C Page 8 of 30
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CY7C1470BV33
CY7C1472BV33, CY7C1474BV33
access (read, write, or deselect) is latched into the Address
Register (provided the appropriate control signals are asserted).
On the next clock rise the data presented to DQ
a,b,c,d
/DQP
(DQ
CY7C1472BV33, and DQ
CY7C1474BV33) (or a subset for byte write operations, see
for CY7C1470BV33, DQ
a,b,c,d
a,b,c,d,e,f,g,h
/DQP
and DQP
/DQP
a,b
a,b,c,d,e,f,g,h
a,b
for
for
“Partial Write Cycle Description” on page 11 for details) input s is
latched into the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
BW
CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
for CY7C1470BV33, BW
a,b,c,d
a,b,c,d,e,f,g,h
for CY7C1474BV33) signals. The
for CY7C1472BV33, and
a,b
provides Byte Write capability that is described in “Partial Write
Cycle Description” on page 11. Asserting the Write Enable input
(WE
) with the selected BW input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte Write
capability has been included to greatly simplify read, modify, or
write sequences, which can be reduced to simple Byte Write
operations.
Because the CY7C1470BV33, CY7C1472BV33, and
CY7C1474BV33 are common IO devices, data must not be
driven into the device while the outputs are active. The OE
be deasserted HIGH before presenting data to the DQ
(DQ
CY7C1472BV33, and DQ
CY7C1474BV33) inputs. Doing so tri-states the output drivers.
As a safety precaution, DQ
CY7C1470BV33, DQ
DQ
automatically tri-stated during the data portion of a write cycle,
/DQP
a,b,c,d
a,b,c,d,e,f,g,h
for CY7C1470BV33, DQ
a,b,c,d
a,b,c,d,e,f,g,h
and DQP (DQ
/DQP
/DQP
a,b
a,b,c,d,e,f,g,h
for CY7C1472BV33, and
a,b
for CY7C1474BV33) are
/DQP
a,b,c,d
/DQP
a,b
a,b,c,d,e,f,g,h
/DQP
can
and DQP
for
a,b
for
for
a,b,c,d
regardless of the state of OE.
Burst Write Accesses
The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33
has an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD
load the initial address, as described in “Single Write Accesses”
on page 8. When ADV/LD
is driven HIGH on the subsequent
must be driven LOW to
clock rise, the Chip Enables (CE
are ignored and the burst counter is incremented. The corre ct
BW (BW
and BW
in each cycle of the burst wri te to write t he correct b ytes of dat a.
for CY7C1470BV33, BW
a,b,c,d
a,b,c,d,e,f,g,h
for CY7C1474BV33) inputs must be driven
, CE2, and CE3) and WE inputs
1
for CY7C1472V33,
a,b
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE
and CE
ZZ input returns LOW.
, must remain inactive for the duration of t
3
ZZREC
Table 2. Interleaved Burst Address Table
(MODE = Floating or V
First
Address
)
DD
Second
Address
Third
Address
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Table 3. Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
after the
Fourth
Fourth
, CE2,
1
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 120 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Document #: 001-15031 Rev. *C Page 9 of 30
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