Cypress CY7C1471BV25, CY7C1475BV25, CY7C1473BV25 User Manual
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Features
Functional Description
■ No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
■ Supports up to 133 MHz bus operations with zero wait states
■ Data transfers on every clock
■ Pin compatible and functionally equivalent to ZBT™ devices
■ Internally self timed output buffer control to eliminate the need
to use OE
■ Registered inputs for flow through operation
■ Byte Write capability
■ 2.5V IO supply (V
■ Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■ Clock Enable (CEN) pin to enable clock and suspend operation
■ Synchronous self timed writes
■ Asynchronous Output Enable (OE)
■ CY7C1471BV25, CY7C1473BV25 available in
DDQ
)
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-ball FBGA package. CY7C1475BV25
available in Pb-free and non-Pb-free 209-ball FBGA package.
■ Three Chip Enables (CE
expansion.
■ Automatic power down feature available using ZZ mode or CE
, CE2, CE3) for simple depth
1
deselect.
■ IEEE 1149.1 JTAG Boundary Scan compatible
■ Burst Capability - linear or interleaved burst order
■ Low standby power
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471BV25, CY7C1473BV25, and
CY7C1475BV25 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data transferred on every clock cycle. This
feature dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent write-read
transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock inpu t is qualified by the
Clock Enable (CEN
) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are conducted
X
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
) provide easy bank selection
, CE2, CE3) and an
1
and output tri-state control. To avoid bus contention, the output
drivers are synchronously tri-stated during the data portion of a
write sequence.
For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Selection Guide
Description 133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 305 275 mA
Maximum CMOS Standby Current 120 120 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-15013 Rev. *E Revised February 29, 2008
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Logic Block Diagram – CY7C1471BV25 (2M x 36)
ADDRESS
REGISTER
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
D1
D0
BURST
LOGIC
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BW
BW
BW
BW
WE
CE1
CE2
CE3
ZZ
CE
A
B
C
D
OE
Logic Block Diagram – CY7C1473BV25 (4M x 18)
A1'
Q1
A0'
Q0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
DQP
DQP
A
B
C
D
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER
S
E
N
S
E
A
M
P
S
E
CLK
C
EN
A0, A1, A
MODE
C
ADV/LD
BW A
BW B
WE
OE
CE1
CE2
CE3
ZZ
CE
ADDRESS
REGISTER
READ LOGIC
A1
D1
A0
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
SLEEP
CONTROL
BURST
LOGIC
Q1
Q0
A1'
A0'
WRITE
DRIVERS
MEMORY
ARRAY
REGISTER
INPUT
O
U
T
P
S
E
N
S
E
A
M
P
S
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
E
DQs
DQP
DQPB
A
G
E
Document #: 001-15013 Rev. *E Page 2 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Logic Block Diagram – CY7C1475BV25 (1M x 72)
A0, A1, A
C
MODE
CE1
CE2
CE3
OE
READ LOGIC
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CEN
WRITE
DRIVERS
BW
a
BW
b
WE
ZZ
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
Sleep Control
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
Document #: 001-15013 Rev. *E Page 3 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations
A
A
A
A
A1
A0
NC/288M
NC/144M
V
SS
V
DD
A
A
A
A
A
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
A
A
CE
1CE2
BWDBW
C
BWBBWACE3VDDV
SS
CLKWECEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3132333435
36
37
38394041424344454647484950
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
9998979695949392919089
888786
85
848382
81
A
A
ADV/LD
ZZ
MODE
A
CY7C1471BV25
BYTE A
BYTE B
BYTE D
BYTE C
A
A
Figure 1. 100- Pin TQFP Pinout
Document #: 001-15013 Rev. *E Page 4 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations (continued)
A
A
A
A
A1
A0
NC/288M
NC/144M
V
SS
V
DD
A
A
A
A
A
A
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1CE2
NC
NC
BW
BBWA
CE3VDDV
SS
CLK
WE
CEN
OE
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3132333435
36
37
38394041424344454647484950
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10099989796959493929190
89
888786
85
848382
81
A
A
ADV/LD
ZZ
MODE
A
CY7C1473BV25
BYTE A
BYTE B
A
A
Figure 2. 100-Pin TQFP Pinout
Document #: 001-15013 Rev. *E Page 5 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1471BV25 (2M x 36)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
DQP
C
DQ
C
DQP
D
NC
DQ
D
CE
1
BW
B
CE
3
BW
C
CEN
A
CE2
DQ
C
DQ
D
DQ
D
MODE
NC
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
A
V
DDQ
BW
D
BW
A
CLK
WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCK
V
SS
TDI
A
A
DQ
C
V
SS
DQ
C
V
SS
DQ
C
DQ
C
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
D
DQ
D
NC/144M
NC
V
DDQ
V
SS
TMS
891011
NC/288M
A
A
ADV/LD
NC
OE
A
NC
V
SS
V
DDQ
NC DQP
B
V
DDQ
V
DD
DQ
B
DQ
B
DQ
B
NC
DQ
B
NC
DQ
A
DQ
A
V
DD
V
DDQ
V
DD
V
DDQ
DQ
B
V
DD
NC
V
DD
DQ
A
V
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DDQ
AA
V
SS
A
A
A
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQP
A
DQ
A
A
V
DDQ
A
A0
A
V
SS
NC
CY7C1473BV25 (4M x 18)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/576M
NC/1G
NC
NC
DQP
B
NC
DQ
B
CE
1
NC CE
3
BW
B
CEN
A
CE2
NC
DQ
B
DQ
B
MODE
NC
DQ
B
DQ
B
NC
NC
NC
A
V
DDQ
NC
BW
A
CLK
WE
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCK
V
SS
TDI
A
A
DQ
B
V
SS
NC V
SS
DQ
B
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
B
NC
NC/144M
NC
V
DDQ
V
SS
TMS
891011
NC/288M
A
A
ADV/LD
A
OE
A
NC
V
SS
V
DDQ
NC DQP
A
V
DDQ
V
DD
NC
DQ
A
DQ
A
NC
NC
NC
DQ
A
NC
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DD
NC
V
DD
NCV
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
NC
V
DDQ
AA
V
SS
A
A
A
DQ
A
NC
NC
ZZ
DQ
A
NC
NC
DQ
A
A
V
DDQ
A
A0
A
V
SS
NC
A
A
A
A
Document #: 001-15013 Rev. *E Page 6 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Pin Configurations (continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
123456789 1110
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DQPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQPd
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DQPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQPa
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
AA AA
NC
NC
NC/144M
A A NC/288M
A
AA
AA
A
A1
A0
A
AA
AA
A
NC/576M
NC
NC
NC NC
NC
BWS
b
BWS
f
BWSeBWS
a
BWScBWS
g
BWS
d
BWS
h
TMS
TDI TDO TCK
NC
NC MODE
NC
CEN
V
SS
NC
CLK
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/1G
V
DD
NC
OE
CE
3
CE
1
CE
2
ADV/LD
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
V
SS
NC
V
DDQ
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
CY7C1475BV25 (1M × 72)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
Document #: 001-15013 Rev. *E Page 7 of 30
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CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 1. Pin Definitions
Name IO Description
, A1, A Input-
A
0
BW
BW
BW
BW
, BWB,
A
, BWD,
C
, BWF,
E
, BW
G
H
Synchronous
Input-
Synchronous
WE Input-
Synchronous
ADV/LD Input-
Synchronous
Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD
be driven LOW to load a new address.
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN
is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select or deselect the device.
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select or deselect the device.
1
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select or deselect the device.
1
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic
block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled
to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins.
OE
is masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
CEN Input-
Synchronous
ZZ Input-
Asynchronous
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN
not deselect the device, CEN
can be used to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin must be LOW or left
floating. ZZ pin has an internal pull down.
DQ
s
IO-
Synchronous
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycl e. The
direction of the pins is controlled by OE
When HIGH, DQ
tri-stated during the data portion of a write sequence, during the first clock when emerging from
and DQPX are placed in a tri-state condition.The outputs are automatically
s
. When OE is asserted LOW, the pins behave as outputs.
a deselected state, and when the device is deselected, regardless of the state of OE
DQP
X
IO-
Synchronous
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During
write sequences, DQP
is controlled by BWX correspondingly.
X
MODE Input Strap Pin Mode Input. Selects the Burst Order of the Device.
When tied to Gnd selects linear burst sequence. When tied to V
leaved burst sequence.
V
DD
V
DDQ
V
SS
TDO JTAG serial output
Power Supply Power Supply Inputs to the Core of the Device.
IO Power Supply Power Supply for the IO Circuitry.
Ground Ground for the Device.
Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not used, this pin must be left unconnected. This pin is not available on TQFP
packages.
.
or left floating selects inter-
DD
must
does
Document #: 001-15013 Rev. *E Page 8 of 30
[+] Feedback
CY7C1471BV25
CY7C1473BV25, CY7C1475BV25
Table 1. Pin Definitions (continued)
Name IO Description
TDI JTAG serial input
Synchronous
TMS JTAG serial input
Synchronous
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not used, leave this pin floating or connected to V
available on TQFP packages.
through a pull up resistor. This pin is not
DD
Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not used, this pin can be disconnected or connected to V
packages.
. This pin is not available on TQFP
DD
TCK JTAG-Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, connect this pin to VSS.
This pin is not available on TQFP packages.
NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
Functional Overview
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
are synchronous flow through burst SRAMs designed specifically to eliminate wait states during write read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (t
device).
Accesses are initiated by asserting all th ree Chip Enables (CE
CE
, CE3) active at the rising edge of the clock. If CEN is active
2
LOW and ADV/LD
is asserted LOW, the address presented to
the device is latched. The access is either a read or write
operation, depending on the status of the Write Enable (WE
Use Byte Write Select (BW
Write operations are qualified by the WE. All writes are simplified
with on-chip synchronous self- timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
operations (reads, writes, and deselects) are pipelined. ADV/LD
must be driven LOW after the device is deselected to load a new
address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise:
■ CEN is asserted LOW
■ CE
, CE2, and CE3 are ALL asserted active
1
■ WE is deasserted HIGH
■ ADV/LD is asserted LOW.
The address presented to the address inputs is latched into the
Address Register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE
read access, the output buffers are controlled by OE
internal control logic. OE
requested data. On the subsequent clock, another operation
(read/write/deselect) can be initiated. When the SRAM is
is active LOW. After the first clock of the
). If CEN is HIGH, the clock signal
) is 6.5 ns (133-MHz
CDV
) to conduct Byte Write operations.
X
, CE2, CE3) and an
1
) simplify depth expansion. All
and the
must be driven LOW to drive out the
deselected at clock rise by one of the chip enable signals, the
output is tri-stated immediately.
Burst Read Accesses
The CY7C1471BV25, CY7C1473BV25, and CY7C1475BV25
has an on-chip burst counter that enables the user the ability to
supply a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD
must be driven LOW to
load a new address into the SRAM, as described in the Single
Read Access section. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved burst
sequence. Both burst counters use A0 and A1 in the burst
,
1
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD
regardless of the state of chip enable inputs or WE
at the beginning of a burst cycle. Therefore, the type of access
).
(read or write) is maintained throughout the burst sequence.
increments the internal burst counter
. WE is latched
Single Write Accesses
Write accesses are initiated when these conditions are satisfied
at clock rise:
■ CEN is asserted LOW
■ CE
, CE2, and CE3 are ALL asserted active
1
■ WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE
external logic to present the data on DQs and DQP
On the next clock rise the data presented to DQs and DQP
a subset for Byte Write operations, see “Truth Table for
Read/Write” on page 12 for details) inputs is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BW
signals. The CY7C1471BV25, CY7C1473BV25, and
CY7C1475BV25 provide Byte Write capability that is described
in the “Truth Table for Read/Write” on page12. The input WE
with the selected BWx input selectively writes to only the desired
bytes. Bytes not selected during a Byte Write operation remain
unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte Write capability is
input signal. This allows the
.
X
(or
X
X
Document #: 001-15013 Rev. *E Page 9 of 30
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