Cypress CY7C1475V25, CY7C1471V25, CY7C1473V25 User Manual
CY7C1471V25
CY7C1473V25
CY7C1475V25
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 2.5V/1.8V IO supply (V
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self timed writes
• Asynchronous Output Enable (OE)
• CY7C1471V25, CY7C1473V25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475V25
available in Pb-free and non-Pb-free 209-Ball FBGA
package.
• Three Chip Enables (CE
expansion.
• Automatic power down feature available using ZZ mode or
CE deselect.
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst Capability - linear or interleaved burst order
• Low standby power
)
DDQ
, CE2, CE3) for simple depth
1
Functional Description
The CY7C1471V25, CY7C1473V25, and CY7C1475V25 are
2.5V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst
SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V25, CY7C1473V25, and
CY7C1475V25 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data transferred on every clock cycle.
This feature dramatically improves the throughput of data
through the SRAM, especially in systems that require frequent
write-read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by two or four Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are conducted
X
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
[1]
) signal, which when deasserted
, CE2, CE3) and an
1
) provide easy bank
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 305 275 mA
Maximum CMOS Standby Current 120 120 mA
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05287 Rev. *I Revised July 04, 2007
[+] Feedback
Logic Block Diagram – CY7C1471V25 (2M x 36)
CY7C1471V25
CY7C1473V25
CY7C1475V25
ADDRESS
REGISTER
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
D1
D0
BURST
LOGIC
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BW
BW
BW
BW
WE
CE1
CE2
CE3
ZZ
CE
A
B
C
D
OE
Logic Block Diagram – CY7C1473V25 (4M x 18)
A1'
Q1
A0'
Q0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
DQP
DQP
A
B
C
D
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER
S
E
N
S
E
A
M
P
S
E
CLK
C
EN
A0, A1, A
MODE
C
ADV/LD
BW A
BW B
WE
OE
CE1
CE2
CE3
ZZ
CE
ADDRESS
REGISTER
READ LOGIC
A1
D1
A0
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
SLEEP
CONTROL
BURST
LOGIC
Q1
Q0
A1'
A0'
WRITE
DRIVERS
MEMORY
ARRAY
REGISTER
INPUT
O
U
T
P
S
E
N
S
E
A
M
P
S
E
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
A
B
Document #: 38-05287 Rev. *I Page 2 of 32
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Logic Block Diagram – CY7C1475V25 (1M x 72)
CY7C1471V25
CY7C1473V25
CY7C1475V25
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BW
BW
BW
BW
BW
BW
BW
BW
WE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
a
b
c
d
e
f
g
h
OE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep Control
A1
D1
A0
D0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
BURST
LOGIC
A1'
Q1
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
INPUT
REGISTER 0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
Document #: 38-05287 Rev. *I Page 3 of 32
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Pin Configurations
CY7C1471V25
CY7C1473V25
CY7C1475V25
100-Pin TQFP Pinout
BYTE C
BYTE D
DQP
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
DQP
SS
SS
NC
DD
NC
SS
SS
SS
1CE2
A
CE
A
100
999897
1
C
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
D
C
BWDBW
BWBBWACE3VDDV
9695949392919089888786
SS
CLKWECEN
CY7C1471V25
OE
A
ADV/LD
858483
A
A
A
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
DQP
B
B
B
B
BYTE B
B
B
B
B
B
A
A
A
A
BYTE A
A
A
A
A
A
31323334353637383940414243444546474849
A
A
A
A
A1
A0
MODE
NC/288M
NC/144M
SS
DD
A
V
A
V
A
A
A
A
50
A
A
A
Document #: 38-05287 Rev. *I Page 4 of 32
[+] Feedback
Pin Configurations (continued)
CY7C1471V25
CY7C1473V25
CY7C1475V25
100-Pin TQFP Pinout
BYTE B
V
DDQ
V
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQP
V
V
DDQ
NC
NC
NC
SS
NC
NC
SS
NC
DD
NC
SS
SS
NC
SS
NC
NC
NC
1CE2
A
A
100
99989796959493929190898887
CE
NC
1
2
3
4
5
6
7
8
B
9
B
10
11
12
B
13
B
14
15
16
17
18
B
19
B
20
21
22
B
23
B
24
B
25
26
27
28
29
30
BBWA
NC
BW
CE3VDDV
CY7C1473V25
SS
CLKWECEN
OE
86
A
ADV/LD
858483
A
A
A
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
A
A
A
A
A
BYTE A
A
A
A
A
31323334353637383940414243444546474849
A
A
A
A
A1
A0
MODE
NC/288M
NC/144M
SS
DD
V
A
V
A
A
A
A
A
50
A
A
A
Document #: 38-05287 Rev. *I Page 5 of 32
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Pin Configurations (continued)
CY7C1471V25
CY7C1473V25
CY7C1475V25
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1471V25 (2M x 36)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
234 5671
NC/576M
NC/1G
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC/144M
MODE
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
A
CE
CE2
V
DDQ
V
C
C
C
C
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
D
D
D
D
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CY7C1473V25 (4M x 18)
234 5671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC/144M
MODE
A
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
A
A
CE
CE2
V
DDQ
V
B
B
B
B
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
B
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC CE
BW
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
891011
A
A
NC
NC
NC DQP
B
B
B
B
A
A
A
A
DQ
DQ
DQ
DQ
ZZ
DQ
DQ
DQ
DQ
DQP
NC/288M
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
B
B
B
B
B
A
A
A
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
891011
A
A
NC
NC DQP
A
A
A
A
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
NC/288M
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
Document #: 38-05287 Rev. *I Page 6 of 32
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Pin Configurations (continued)
12 34 5 6 78 9 1110
CY7C1471V25
CY7C1473V25
CY7C1475V25
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1475V25 (1M × 72)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
SS
SS
SS
SS
SS
SS
DQb
DQb
f
DQb
a
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
AA A A
BWScBWS
BWS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CLK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC/144M
AA
TMS
CE
2
g
NC/576M
BWS
V
V
V
NC
DDQ
V
DDQ
V
DDQ
d
NC/1G
SS
SS
h
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC MODE
A
TDI TDO TCK
ADV/LD
NC
WE
CE
1
OE
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
NC
A A NC/288M
A
AA
AA
A1
A0
A
NC
NC NC
V
V
V
V
V
V
V
V
V
V
V
NC
A
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
CE
3
BWS
BWS
b
BWSeBWS
V
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
V
V
V
V
V
V
V
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
NC
AA
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Document #: 38-05287 Rev. *I Page 7 of 32
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Pin Definitions
Name IO Description
, A1, A Input-
A
0
BW
BW
BW
BW
, BWB,
A
, BWD,
C
, BWF,
E
, BW
G
H
Synchronous
Input-
Synchronous
WE Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
ZZ Input-
Asynchronous
DQ
DQP
s
X
IO-
Synchronous
IO-
Synchronous
MODE Input Strap Pin Mode Input. Selects the burst order of the device.
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground Ground for the device.
TDO JTAG serial output
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access. After being deselected,
ADV/LD must be driven LOW to load a new address.
Clock Input. Captures all synchronous inputs to the device. CLK is qualified with CEN
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select or deselect the device.
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
and CE3 to select or deselect the device.
1
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select or deselect the device.
1
Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic
block inside the device to control the direction of the IO pins. When LOW, the IO pins are
enabled to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as
input data pins. OE
is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN
does not deselect the device, CEN
can be used to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep”
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.
Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE
pins behave as outputs. When HIGH, DQ
outputs are automatically tri-stated during the data portion of a write sequence, during the
and DQPX are placed in a tri-state condition.The
s
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE
.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs. During
write sequences, DQP
is controlled by BWX correspondingly.
X
When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects
interleaved burst sequence.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be left unconnected. This pin is not available on
TQFP packages.
CY7C1471V25
CY7C1473V25
CY7C1475V25
.
. When OE is asserted LOW, the
Document #: 38-05287 Rev. *I Page 8 of 32
[+] Feedback
CY7C1471V25
CY7C1473V25
CY7C1475V25
Pin Definitions (continued)
Name IO Description
TDI JTAG serial input
Synchronous
TMS JTAG serial input
Synchronous
TCK JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
NC - No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be left floating or connected to V
pin is not available on TQFP packages.
through a pull up resistor. This
DD
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not used, this pin can be disconnected or connected to V
TQFP packages.
connected to V
. This pin is not available on TQFP packages.
SS
. This pin is not available on
DD
expansion pins and are not internally connected to the die.
Functional Overview
The CY7C1471V25, CY7C1473V25, and CY7C1475V25 are
synchronous flow through burst SRAMs designed specifically
to eliminate wait states during write-read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (t
device).
Accesses are initiated by asserting all three Chip Enables
, CE2, CE3) active at the rising edge of the clock. If CEN
(CE
1
is active LOW and ADV/LD is asserted LOW, the address
presented to the device is latched. The access can either be
a read or write operation, depending on the status of the Write
Enable (WE
). Byte Write Select (BWX) can be used to conduct
Byte Write operations.
Write operations are qualified by the WE
simplified with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (reads, writes, and deselects) are pipelined.
ADV/LD must be driven LOW after the device is deselected to
load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
and (4) ADV/LD
are ALL asserted active, (3) WE is deasserted HIGH,
3
is asserted LOW. The address presented to
the address inputs is latched into the Address Register and
presented to the memory array and control logic. The control
logic determines that a read access is in progress and allows
the requested data to propagate to the output buffers. The data
is available within 6.5 ns (133-MHz device) provided OE
active LOW. After the first clock of the read access, the output
buffers are controlled by OE
must be driven LOW to drive out the requested data. On the
subsequent clock, another operation (read/write/deselect) can
be initiated. When the SRAM is deselected at clock rise by one
of the chip enable signals, the output is tri-stated immediately.
). If CEN is HIGH, the clock
) is 6.5 ns (133-MHz
CDV
. All writes are
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is
and the internal control logic. OE
Burst Read Accesses
The CY7C1471V25, CY7C1473V25, and CY7C1475V25 has
an on-chip burst counter that enables the user the ability to
supply a single address and conduct up to four reads without
reasserting the address inputs. ADV/LD
must be driven LOW
to load a new address into the SRAM, as described in the
Single Read Access section. The sequence of the burst
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in
the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD
increments the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (read or write) is maintained throughout the
burst sequence.
Single Write Accesses
Write accesses are initiated when these conditions are
satisfied at clock rise:
•CEN
is asserted LOW
, CE2, and CE3 are ALL asserted active
•CE
1
is asserted LOW.
•WE
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE
external logic to present the data on DQs and DQP
input signal. This allows the
.
X
On the next clock rise the data presented to DQs and DQP
(or a subset for Byte Write operations, see “Truth Table for
Read/Write” on page 12 for details) inputs is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by
BW
signals. The CY7C1471V25, CY7C1473V25, and
X
CY7C1475V25 provide Byte Write capability that is described
in the “Truth Table for Read/Write” on page 12. The input WE
with the selected BWx input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write
operation remain unaltered. A synchronous self timed write
mechanism is provided to simplify the write operations. Byte
Write capability is included to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
X
Document #: 38-05287 Rev. *I Page 9 of 32
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CY7C1471V25
CY7C1473V25
CY7C1475V25
Because the CY7C1471V25, CY7C1473V25, and
CY7C1475V25 are common IO devices, data must not be
driven into the device while the outputs are active. The OE
be deasserted HIGH before presenting data to the DQs and
DQPX inputs. This tri-states the output drivers. As a safety
precaution, DQs and DQP
the data portion of a write cycle, regardless of the state of OE
Burst Write Accesses
The CY7C1471V25, CY7C1473V25, and CY7C1475V25
have an on-chip burst counter that enables the user to supply
a single address and conduct up to four Write operations
without reasserting the address inputs. ADV/LD
driven LOW to load the initial address, as described in the
Single Write Access section. When ADV/LD
the subsequent clock rise, the Chip Enables (CE
CE
) and WE inputs are ignored and the burst counter is incre-
3
mented. The correct BW
of the Burst Write, to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected before entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of t
ZZREC
are automatically tri-stated during
X
is dri ven HIGH on
1
inputs must be driven in each cycle
X
after the ZZ input returns LOW.
can
must be
, CE2, and
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1: A0
.
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
DD
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
)
Third
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Fourth
Address
A1: A0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD – 0.2V 120 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
CYC
CYC
CYC
ns
ns
ns
Document #: 38-05287 Rev. *I Page 10 of 32
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