Cypress CY7C1474V25, CY7C1472V25, CY7C1470V25 User Manual
p
CY7C1470V25
a
b
c
d
C
C
CY7C1472V25
CY7C1474V25
72-Mbit(2M x 36/4M x 18/1M x 72)
elined SRAM with NoBL™ Architecture
Pi
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V/1.8V I/O supply (V
• Fast clock-to-output times
— 3.0 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• CY7C1470V25, CY7C1472V25 available in
JEDEC-standard lead-free 100-pin TQFP, lead-free and
non-lead-free 165-ball FBGA package. CY7C1474V25
available in lead-free and non-lead-free 209 ball FBGA
package
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
DDQ
)
Functional Description
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5V,
2M x 36/4M x 18/1M x 72 Synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped
with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data in systems that require frequent Write/Read
transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25
are pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BW
for CY7C1470V25 and BWa–BWb for CY7C1472V25) and a
Write Enable (WE
–BWh for CY7C1474V25, BWa–BW
a
) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
) signal,
d
Logic Block Diagram-CY7C1470V25 (2M x 36)
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05290 Rev. *I Revised June 21, 2006
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
[+] Feedback
a
b
C
C
Logic Block Diagram-CY7C1472V25 (4M x 18)
s
P
a
P
b
P
c
P
d
P
e
P
f
P
g
P
h
C
C
A0, A1, A
MODE
C
LK
EN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
CY7C1470V25
CY7C1472V25
CY7C1474V25
A1'
A0'
Q0
ADV/LD
BW
BW
a
b
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WE
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Logic Block Diagram-CY7C1474V25 (1M x 72)
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
D1D0Q1
BURST
LOGIC
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
REGISTER 0
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
MEMORY
ARRAY
INPUT
REGISTER 1
WRITE
DRIVERS
A1'
A0'
Q0
INPUT
REGISTER 0
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
O
U
T
P
U
T
B
DQs
U
F
DQP
F
DQP
E
R
S
E
E
O
U
T
P
D
U
A
T
T
A
B
DQ
U
S
F
T
E
E
R
I
N
G
DQ
F
DQ
E
R
DQ
S
DQ
DQ
E
DQ
DQ
DQ
E
OE
CE1
CE2
CE3
Selection Guide
ZZ
READ LOGIC
Sleep
Control
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 3.0 3.0 3.4 ns
Maximum Operating Current 450 450 400 mA
Maximum CMOS Standby Current 120 120 120 mA
Document #: 38-05290 Rev. *I Page 2 of 28
[+] Feedback
Pin Configurations
a
100-pin TQFP Pinout
CY7C1470V25
CY7C1472V25
CY7C1474V25
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWd
BWc
3
CE
VDDV
SS
CLKWECEN
BWa
BWb
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
CY7C1470V25
(2M × 36)
31323334353637383940414243444546474849
OE
ADV/LD
A
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
ZZ
DDQ
SS
DQa
SS
DDQ
DQPa
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
DQb
DQb
V
DDQ
V
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
56
V
55
V
54
DQa
53
DQa
52
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
BW
NC
NC
VDDVSSCLKWECEN
CE
CY7C1472V25
(4M × 18)
OE
ADV/LD
A
A
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
0
A
A1A
SS
DD
V
V
NC(144)
NC(288)
AAA
A
A
A
A
A
A
A
AAA
MODE
1A0
A
AAA
A
A
A
A
DD
SS
V
V
NC(144)
NC(288)
A
A
Document #: 38-05290 Rev. *I Page 3 of 28
[+] Feedback
Pin Configurations (continued)
234 5671
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
A
A
CE
CE2
V
V
c
V
c
V
c
V
c
NC
V
d
V
d
V
d
V
d
V
A
2345671
A
A
A
A
CE
CE2
V
V
b
V
b
V
b
V
b
NC
V
V
V
V
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1470V25 (2M x 36)
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
BW
d
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CY7C1472V25 (4M x 18)
BW
1
b
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
b
CLK
a
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CE
CLK
a
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CY7C1470V25
CY7C1472V25
CY7C1474V25
891011
A AADV/LD
OE A
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
NC DQP
DQ
b
DQ
b
DQ
b
DQ
b
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
891011
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQPa
NC
NC
NC
NC
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
NC
NC
b
DQ
b
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
NC/288M
AA
A
NC
DQ
a
DQ
a
DQ
a
DQ
a
ZZ
NCV
NC
NC
NC
NC
NC/288M
AA
Document #: 38-05290 Rev. *I Page 4 of 28
[+] Feedback
Pin Configurations (continued)
123456789 1110
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1474V25 (1M x 72)
CY7C1470V25
CY7C1472V25
CY7C1474V25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
AAAA
BWScBWS
BWS
V
V
DDQ
V
V
DDQ
V
V
DDQ
CLK
V
DDQ
V
V
DDQ
V
V
DDQ
V
NC/144M
AA
TMS
CE
2
g
NC/576M
BWS
V
V
V
NC
DDQ
V
DDQ
V
DDQ
d
NC/1G
SS
SS
h
SS
SS
SS
NC
V
DDQ
V
SS
SS
SS
SS
V
DDQ
V
SS
V
DDQ
NC MODE
A
TDI TDO TCK
ADV/LD
NC
WE
CE
1
OE
V
V
V
V
V
V
V
V
V
V
V
DD
SS
DD
SS
DD
SS
DD
SS
DD
SS
DD
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
NC
A
A
AA
AA
A1
A0
A
NC
NC NC
V
DD
V
V
DD
V
V
DD
V
V
DD
V
V
DD
V
V
DD
NC
A NC/288M
A
SS
SS
SS
SS
SS
CE
3
BWS
BWS
b
BWSeBWS
V
SS
SS
SS
SS
V
V
V
V
V
V
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
V
V
V
V
V
V
V
DDQ
V
DDQ
V
DDQ
NC
DDQ
V
DDQ
V
DDQ
NC
AA
SS
SS
SS
SS
SS
SS
DQb
DQb
f
DQb
a
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
Input-
Synchronous
A
BW
BW
BW
BW
BW
BW
BW
BW
WE
a
b
c
d
e
f
g
h
Input-
Synchronous
Input-
Synchronous
Document #: 38-05290 Rev. *I Page 5 of 28
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
BW
controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQP
c
controls DQ
and DQP
f
controls DQg and DQP
f, BWg
controls DQa and DQPa, BWb controls DQb and DQPb,
a
controls DQh and DQPh.
g, BWh
e, BWf
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW . This
signal must be asserted LOW to initiate a write sequence.
[+] Feedback
CY7C1470V25
CY7C1472V25
CY7C1474V25
Pin Definitions (continued)
Pin Name I/O Type Pin Description
ADV/LD
CLK Input-
CE
1
CE
2
CE
3
OE
CEN
DQ
s
DQP
X
MODE Input Strap Pin Mode Input. Selects the burst order of the devic e. Tied H IGH selects the interleaved burst or der .
TDO JTAG Serial
TDI JTAG Serial Input
TMS Test Mode Select
TCK JTAG Clock Clock input to the JTAG circuitry.
V
DD
V
DDQ
V
SS
NC – No connects. This pin is not connected to the die.
NC(144M,
288M,
576M, 1G)
ZZ Input-
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CLK is only recognized if CEN
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
is active LOW.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Input-
Synchronous
I/O-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write sequence, during the first clock when emerging
during the previous clock rise of the read cycle. The direction of the pins is
[18:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQh are placed in a tri-state cond ition. The outputs are automat-
a
from a deselected state, and when the device is deselected, regardless of the state of OE.
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQP
BW
, and DQPd is controlled by BWd, DQPe is controlled by BW
c
DQPg is controlled by BW
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
a
DQPh is controlled by BWh.
g,
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Output
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
– These pins are not connected. They will be used for expansion to the 144M, 288M, 576M and
1G densities.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous
with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
is masked during
does not
[71:0]
DQPf is controlled by BW
e,
should
. During
f,
Document #: 38-05290 Rev. *I Page 6 of 28
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CY7C1470V25
CY7C1472V25
CY7C1474V25
Functional Overview
The CY7C1470V25/CY7C1472V25/CY7C1474V25 are
synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 3.0 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
). BW
can be used to
[x]
). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A Read access is initiated when the following con ditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
is asserted LOW, (2) CE1, CE2,
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a Read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE
is active LOW. After the first
clock of the Read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 have an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD
must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD
will increment
the internal burst counter regardless of the state of chip
enables inputs or WE
. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The Write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V25). In addition, the address for the subsequent
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V25 and DQ
a,b,c,d
for CY7C1474V25,
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V25 & DQ
a,b,c,d
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V25) (or a subset for Byte Write operations, see
for CY7C1474V25,
a,b
/DQP
a,b
for
Write Cycle Description table for details) inputs is latched into
the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
CY7C1470V25 and BW
CY7C1470V25/CY7C1472V25/CY7C1474V25 provides Byte
for CY7C1474V25, BW
for CY7C1472V25) signals. The
a,b
a,b,c,d
for
Write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE
Byte Write Select (BW
) input will selectively write to only the
) with the selected
desired bytes. Bytes not selected during a Byte Write
operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the Write
operations. Byte Write capability has been included in order to
greatly simplify Read/Modify/Write sequences, which can be
reduced to simple Byte Write operations.
Because the CY7C1470V25/CY7C1472V25/CY7C1474V25
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE
can be deasserted HIGH before presenting data to the DQ
DQP (DQ
DQ
a,b,c,d
CY7C1472V25) inputs. Doing so will tri-state the output
a,b,c,d,e,f,g,h
/DQP
a,b,c,d
/DQP
for CY7C1470V25 and DQ
a,b,c,d,e,f,g,h
for CY7C1474V25,
/DQP
a,b
a,b
and
for
drivers. As a safety precaution, DQ and DQP
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
CY7C1472V25) are automatically tri-stated during the data
portion of a Write cycle, regardless of the state of OE
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1470V25 and DQ
a,b,c,d
for CY7C1474V25,
a,b
/DQP
.
a,b
for
Burst Write Accesses
The CY7C1470V25/CY7C1472V25/CY7C1474V25 has an
on-chip burst counter that allows the user the ability to supply
a single address and conduct up to four Write operations
without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD
is
driven HIGH on the subsequent clock rise, the Chip Enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW
(BW
a,b,c,d,e,f,g,h
for
)
Document #: 38-05290 Rev. *I Page 7 of 28
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CY7C1470V25
CY7C1472V25
CY7C1474V25
CY7C1474V25, BW
CY7C1472V25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
for the duration of t
for CY7C1470V25 and BW
a,b,c,d
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
a,b
for
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
Fourth
Address
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
Second
Address
DD
)
Address
Third
Fourth
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
ZZ Mode Electrical Characteristics
Parameter Description T est Conditi ons Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Operation
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/Write Abort (Begin Burst) None L L L L H X L L-H Tri-State
Write Abort (Continue Burst) Next X L H X H X L L-H Tri-State
Ignore Clock Edge (Stall) Current X L X X X X H L-H –
Sleep Mode None X H X X X X X X Tri-S tate
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles.During a Read cycle DQs and DQP
7. OE
OE
is inactive or when the device is deselected, and DQs = data when OE is active.
Sleep mode standby current ZZ > VDD − 0.2V 120 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[1, 2, 3, 4, 5, 6, 7]
Address
Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
and BW
. See Write Cycle Description table for details.
[a:d]
signal.
.
CYC
CYC
= Tri-state when
[a:d]
ns
ns
ns
Document #: 38-05290 Rev. *I Page 8 of 28
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CY7C1470V25
CY7C1472V25
CY7C1474V25
Partial Write Cycle Description
Function (CY7C1470V25) WE BW
[1, 2, 3, 8]
d
BW
c
BW
b
BW
a
Read H X X X X
Write – No bytes written L H H H H
Write Byte a – (DQa and DQPa) LHHHL
Write Byte b – (DQ
and DQPb)LHHLH
b
Write Bytes b, a L H H L L
Write Byte c – (DQc and DQPc)LHLHH
Write Bytes c, a L H L H L
Write Bytes c, b L H LL L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQPd)LLHHH
d
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Function (CY7C1472V25) WE
BW
b
BW
a
Read H x x
Write – No Bytes Written L H H
Write Byte a – (DQ
and DQPa)LHL
a
Write Byte b – (DQb and DQPb)LLH
Write Both Bytes L L L
Function (CY7C1474V25) WE
BW
x
Read Hx
Write – No Bytes Written L H
Write Byte X − (DQ
Write All Bytes LAll BW
Note:
8. Table only lists a partial listing of the Byte Write combinations. Any combination of BW
active.
and DQP
x
x)
LL
= L
is valid. Appropriate Write will be done based on which Byte Write is
[a:d]
Document #: 38-05290 Rev. *I Page 9 of 28
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