CY7C1460AV25
a
b
c
d
C
CY7C1462AV25
CY7C1464AV25
36-Mbit (1M x 36/2M x 18/512K x 72)
Pipelined SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 2.5V core power supply
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN
• Synchronous self-timed writes
• CY7C1460AV25, CY7C1462AV25 available in
JEDEC-standa r d le ad-free 100-pin TQFP package,
lead-free and non-lead-free 165-ball FBGA package.
CY7C1464AV25 available in lead-free and non-lead-free
209-ball FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
) pin to suspend operation
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipe lined b urst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
pin-compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BW
–BWd for CY7C1460AV25 and BWa–BWb for
BW
a
CY7C1462AV25) and a Write Enable (WE
–BWh for CY7C1464AV25,
a
) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram–CY7C1460AV25 (1M x 36)
A0, A1, A
MODE
CLK
C
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05354 Rev. *D Revised June 22, 2006
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
[+] Feedback
a
b
C
s
P
a
P
b
P
c
P
d
P
e
P
f
P
g
P
h
C
C
Logic Block Diagram–CY7C1462AV25 (2M x 18)
A0, A1, A
MODE
CLK
C
EN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
D1D0Q1
BURST
LOGIC
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
A1'
A0'
Q0
ADV/LD
BW
BW
a
b
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WE
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Logic Block Diagram–CY7C1464AV25 (512K x 72)
A0, A1, A
MODE
C
LK
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
D1D0Q1
BURST
LOGIC
Q0
O
U
T
P
S
U
E
T
N
S
WRITE
DRIVERS
A1'
A0'
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
MEMORY
ARRAY
INPUT
REGISTER 1
E
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
S
E
N
S
E
A
M
P
S
REGISTER 0
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 0
INPUT
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
E
E
R
I
N
G
E
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQP
F
DQP
E
R
S
E
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.2 3.4 ns
Maximum Operating Current 435 385 335 mA
Maximum CMOS Standby Current 120 120 120 mA
Document #: 38-05354 Rev. *D Page 2 of 27
[+] Feedback
Pin Configurations
Q
Q
Q
Q
100-pin TQFP Pinout
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWd
BWc
3
CE
VDDV
SS
CLKWECEN
BWa
BWb
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
CY7C1460AV25
(1M × 36)
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
31323334353637383940414243444546474849
OE
A
ADV/LD
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
DQb
DQb
V
DDQ
V
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
SS
VDDV
CE
BW
NC
NC
CLKWECEN
CY7C1462AV25
(2M × 18)
OE
A
A
ADV/LD
A
A
81
A
80
NC
79
NC
78
V
77
DD
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DD
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
0
A
A1A
SS
DD
V
V
NC/144M
NC/288M
AAA
A
A
NC/72M
A
A
A
A
AAA
MODE
1A0
A
NC/288M
AAA
A
A
DD
SS
V
V
NC/144M
A
NC/72M
A
A
Document #: 38-05354 Rev. *D Page 3 of 27
[+] Feedback
Pin Configurations (continued)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
A
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
NC
NC/72M
A
CE
CE2
V
V
V
V
V
NC
V
V
V
V
V
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1460AV25 (1M × 36)
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
c
BW
d
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
b
CLK
a
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
891011
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQP
DQ
b
DQ
b
DQ
b
DQ
b
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQ
a
DQ
a
DQP
NC/288M
AA
b
a
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1462AV25 (2M × 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
NC
NC
NC/72M
A
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
b
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
NC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
a
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
891011
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC DQP
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
a
a
a
a
A
NC
DQ
a
DQ
a
DQ
a
DQ
a
ZZ
NCV
NC
NC
NC
NC
NC/288M
AA
a
Document #: 38-05354 Rev. *D Page 4 of 27
[+] Feedback
Pin Configurations (continued)
123456789 1110
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1464AV25 (512K x 72)
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
A
BWS
BWS
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CLK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC/144M
CE
BWS
c
BWS
h
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC MODE
A
AA
TMS
TDI TDO TCK
SS
DD
SS
CE
3
BWS
BWS
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
AA
ADV/LD
AA
2
V
V
V
V
V
V
V
V
V
V
V
NC
A
NC
NC
DD
SS
DD
DD
SS
DD
SS
DD
A
SS
DD
DD
SS
DD
SS
DD
WE
CE
OE
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
1
g
NC/576M
d
NC
NC/1G
V
DD
V
SS
V
DD
V
V
V
SS
V
V
V
V
V
NC
NC/72M A NC/288M
A
AA
AA
A1
A0
A
DQb
SS
DDQ
SS
DDQ
SS
DDQ
DDQ
SS
DDQ
SS
DDQ
SS
DQb
f
DQb
a
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
BWS
b
BWS
e
V
V
V
V
V
V
NC
V
V
V
V
V
V
DQe
DQe
DQe
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
Input-
Synchronous
A
BW
BW
BW
BW
BW
BW
BW
BW
WE
a
b
c
d
e
f
g
h
Input-
Synchronous
Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-
Clock
Document #: 38-05354 Rev. *D Page 5 of 27
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQP
BW
c
controls DQ
and DQP
f
controls DQg and DQP
f, BWg
controls DQa and DQPa, BWb controls DQb and DQPb,
a
controls DQh and DQPh.
g, BWh
e, BWf
Write Enable Input, active LOW . Sampled on the rising edge of CLK if CEN is active LOW . This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
new address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a
should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN
CLK is only recognized if CEN
is active LOW.
.
[+] Feedback
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Pin Definitions (continued)
Pin Name I/O Type Pin Description
CE
1
CE
2
CE
3
OE
CEN
DQ
a
DQ
b
DQ
c
DQ
d
DQ
e
DQ
f
DQ
g
DQ
h
DQP
a
DQP
b
DQP
c
DQP
d
DQP
e
DQP
f
DQP
g
DQP
h
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order .
TDO JT AG serial output
TDI JTAG serial input
TMS Test Mode Select
TCK JTAG-Clock Clock input to the JTAG circuitry.
V
DD
V
DDQ
V
SS
NC N/A No connects. This pin is not connected to the die.
NC/72M N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
NC/576M N/A Not connected to the die. Can be tied to any voltage level.
NC/1G N/A Not connected to the die. Can be tied to any voltage level.
ZZ Input-
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Input-
Synchronous
I/O-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
cally tri-stated during the data portion of a write sequence, during the first clock when emerging
during the previous clock rise of the read cycle. The direction of the pins is
X
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automati-
a
from a deselected state, and when the device is deselected, regardless of the state of OE.
I/O-
Synchronous
Bidirectional Data Parity I/O lines . Functionally, these signals are identical to DQ
write sequences, DQP
BW
, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
c
is controlled by BWg, DQPh is controlled by BWh.
DQP
g
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
a
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous
with data integrity preserved. During normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
does not
. During
[31:0]
Document #: 38-05354 Rev. *D Page 6 of 27
[+] Feedback
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Functional Overview
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.6 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.
Write operations are qualified by the Write Enable (WE
). BW
can be used to
[x]
). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
is asserted LOW, (2) CE1, CE2,
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(200-MHz device) provided OE
is active LOW. After the first
clock of the read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 have
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD
must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD
will increment
the internal burst counter regardless of the state of chip
enables inputs or WE
. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address inputs
are ALL asserted active, and (3) the write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
for CY7C1462AV25). In addition, the address for the subse-
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV25 and DQ
a,b,c,d
for CY7C1464AV25,
input signal. This
and DQP
/DQP
a,b
a,b
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV25 and DQ
a,b,c,d
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
for CY7C1462AV25) (or a subset for byte write operations, see
for CY7C1464AV25,
and DQP
/DQP
a,b
a,b
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
CY7C1460AV25 and BW
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 provides
for CY7C1464AV25, BW
for CY7C1462AV25) signals. The
a,b
a,b,c,d
for
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE
the selected Byte Write Select (BW
) input will selectively write
) with
to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE
can be deasserted HIGH before presenting data to the DQ
DQP (DQ
DQ
for CY7C1462AV25) inputs. Doing so will three-state the
a,b,c,d
a,b,c,d,e,f,g,h
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV25 and DQ
a,b,c,d
output drivers. As a safety precaution, DQ
(DQ
a,b,c,d,e,f,g,h
DQ
a,b,c,d
for CY7C1462AV25) are automatically three-stated during the
/DQP
/DQP
a,b,c,d,e,f,g,h
for CY7C1460AV25 and DQ
a,b,c,d
for CY7C1464AV25,
for CY7C1464AV25,
data portion of a write cycle, regardless of the state of OE
and
/DQP
a,b
a,b
and DQP
/DQP
a,b
a,b
.
Burst Write Accesses
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD
must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD
is
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW
(BW
a,b,c,d,e,f,g,h
for
)
Document #: 38-05354 Rev. *D Page 7 of 27
[+] Feedback
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
CY7C1460AV25, BW
CY7C1462AV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
for the duration of t
for CY7C1460AV25 and BW
a,b,c,d
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
a,b
for
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
Second
Address
DD
)
Third
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description T est Conditi ons Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Sleep mode standby current ZZ > VDD − 0.2V 100 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[1, 2, 3, 4, 5, 6, 7]
CYC
CYC
Fourth
Address
Fourth
Address
ns
ns
ns
Address
Operation
Used CE ZZ ADV/LD
WE
BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H –
Sleep MODE None X H X X X X X X Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
signifies that the desired byte write selects are asserted, see Write Cycle Descript i on table for details.
2. Write is defined by WE
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when
7. OE
OE
is inactive or when the device is deselected, and DQs=data when OE is active.
and BWX. See Write Cycle Description table for details.
stands for ALL Chip Enables active. BWx = L signifies at least one Byte Wri te Select is active, BW x = V a lid
signal.
.
Document #: 38-05354 Rev. *D Page 8 of 27
[+] Feedback
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Partial Write Cycle Description
Function (CY7C1460AV25) WE BW
[1, 2, 3, 8]
d
BW
c
BW
b
BW
a
Read H X X X X
Write – No bytes written L H H H H
Write Byte a – (DQ
Write Byte b – (DQ
and DQPa) LHHHL
a
and DQPb)LHHLH
b
Write Bytes b, a L H H L L
Write Byte c – (DQ
and DQPc)LHLHH
c
Write Bytes c, a L H L H L
Write Bytes c, b L H LL L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQPd)LLHHH
d
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Function (CY7C1462AV25) WE BW
b
BW
a
Read H X X
Write – No Bytes Written L H H
Write Byte a – (DQ
Write Byte b – (DQ
and DQPa)LHL
a
and DQPb)LLH
b
Write Both Bytes L L L
Function (CY7C1464AV25) WE
BW
x
Read HX
Write – No Bytes Written L H
Write Byte X − (DQ
and DQP
x
x)
Write All Bytes LAll BW
Note:
8. Table only lists a partial listing of the byte write combi nations. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
X
LL
= L
Document #: 38-05354 Rev. *D Page 9 of 27
[+] Feedback
CY7C1460AV25
T
O
CY7C1462AV25
CY7C1464AV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 2.5V/1.8V I/O logic level.
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 contains
a TAP controller, instruction register, boundary scan register,
bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1 1
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
0 0
EXIT2-DR
UPDATE-DR
1 0
1
0
0
0 0
1
1 1
0 0
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the T AP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
SELECT
0
0
1
1
1
1
0
0
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDI TD
TCK
MS TAP CONTROLLER
Selection
Circuitry
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Instruction Register
012293031 ...
Identification Register
012..x ...
Boundary Scan Register
S
election
Circuitr
y
) for five
DD
Document #: 38-05354 Rev. *D Page 10 of 27
[+] Feedback
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
) when the BYPASS instruction is executed.
SS
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of th e Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next comman d is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1-mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (t
captured correctly if there is no way in a design to stop (o r
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
(for 165-FBGA package) or bit #138 (for 209 FBGA package).
and tCH). The SRAM clock input might not be
CS
Document #: 38-05354 Rev. *D Page 11 of 27
[+] Feedback
CY7C1460AV25
123456
T
CY7C1462AV25
CY7C1464AV25
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
TAP Timing
Test Clock
(TCK)
t
est Mode Select
(TMS)
t
Test Data-In
(TDI)
Test Data-Out
(TDO)
TMSS
TDIS
t
TH
t
TMSH
t
TDIH
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
t
TL
t
CYC
t
TDOX
t
TDOV
DON’T CARE UNDEFINED
TAP AC Switching Characteristics Over the Operating Range
[9, 10]
Parameter Description Min. Max. Unit
Clock
t
TCYC
t
TF
t
TH
t
TL
TCK Clock Cycle Time 50 ns
TCK Clock Frequency 20 MHz
TCK Clock HIGH time 20 ns
TCK Clock LOW time 20 ns
Output Times
t
TDOV
t
TDOX
TCK Clock LOW to TDO Valid 10 ns
TCK Clock LOW to TDO Invalid 0 ns
Set-up Times
t
TMSS
t
TDIS
t
CS
TMS Set-up to TCK Clock Rise 5 ns
TDI Set-up to TCK Clock Rise 5 ns
Capture Set-up to TCK Rise 5 ns
Hold Times
t
TMSH
t
TDIH
t
CH
Notes:
and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
9. t
CS
10.Test conditions are specified using the load in TAP AC test Conditions. t
TMS Hold after TCK Clock Rise 5 ns
TDI Hold after Clock Rise 5 ns
Capture Hold after Clock Rise 5 ns
= 1 ns.
R/tF
Document #: 38-05354 Rev. *D Page 12 of 27
[+] Feedback
CY7C1460AV25
T
F
T
F
CY7C1462AV25
CY7C1464AV25
2.5V TAP AC Test Conditions
Input pulse levels ............................................... VSS to 2.5V
Input rise and fall time ....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
20p
1.8V TAP AC Test Conditions
Input pulse levels.....................................0.2V to V
Input rise and fall time .....................................................1 ns
Input timing reference levels...........................................0.9V
Output reference levels ..................................................0.9V
Test load termination supply voltage ..............................0.9V
1.8V TAP AC Output Load Equivalent
0.9V
50Ω
DO
Z = 50Ω
O
20p
TAP DC Electrical Characteristics And Operating Conditions
DDQ
[11]
= 2.5V 1.7 V
DDQ
= 2.5V 2.1 V
DDQ
V
= 1.8V 1.6 V
DDQ
= 2.5V 0.4 V
DDQ
= 2.5V 0.2 V
DDQ
V
= 1.8V 0.2 V
DDQ
= 2.5V 1.7 VDD + 0.3 V
DDQ
V
= 1.8V 1.26 VDD + 0.3 V
DDQ
= 2.5V –0.3 0.7 V
DDQ
V
= 1.8V –0.3 0.36 V
DDQ
–5 5 µA
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)
Parameter Description T est Conditions Min. Max. Unit
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage I
Output HIGH Voltage I
= –1.0 mA V
OH
= –100 µAV
OH
Output LOW Voltage IOL = 1.0 mA V
Output LOW Voltage IOL = 100 µAV
Input HIGH Voltage V
Input LOW Voltage V
Input Load Current GND ≤ VI ≤ V
DDQ
– 0.2
Identification Register Definitions
Instruction Field
(1M ×36)
Revision Number (31:29) 000 000 000 Describes the version number
Device Depth (28:24) 01011 01011 01011 Reserved for Internal Use
Architecture/Memory Type(23:18) 001000 001000 001000 Defines memory type and archi-
Bus Width/Density(17:12) 100111 010111 110111 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 Allows unique identification of
ID Register Presence Indicator (0) 1 1 1 Indicates the presence of an ID
CY7C1460AV25
Note:
11.All voltages referenced to V
Document #: 38-05354 Rev. *D Page 13 of 27
(GND).
SS
CY7C1462AV25
(2M ×18)
CY7C1464AV25
(512K ×72) Description
tecture
SRAM vendor
register
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Scan Register Sizes
Register Name Bit Size (x36) Bit Size (x18) Bit Size (x72)
Instruction 3 3 3
Bypass 1 1 1
ID 32 32 32
Boundary Scan Order (165-ball FBGA package) 89 89 –
Boundary Scan Order (209-ball FBGA package) – – 138
Identification Codes
Instruction Code Description
EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan regi ster between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
Does not affect SRAM operation.
operations.
Document #: 38-05354 Rev. *D Page 14 of 27
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CY7C1462AV25
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165-ball FBGA Boundary Scan Order
CY7C1460AV25 (1M x 36), CY7C1462AV25 (2M x 18)
Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID
1N6 26E11 51A3 76N1
2N7 27D11 52A2 77N2
3N10 28G10 53B2 78P1
4P11 29F10 54C2 79R1
5 P8 30 E10 55 B1 80 R2
6 R8 31 D10 56 A1 81 P3
7R9 32C11 57C1 82R3
8P9 33A11 58D1 83P2
9P10 34B11 59E1 84R4
10 R10 35 A10 60 F1 85 P4
11 R11 36 B10 61 G1 86 N5
12 H11 37 A9 62 D2 87 P6
13 N11 38 B9 63 E2 88 R6
14 M11 39 C10 64 F2 89 Internal
15 L11 40 A8 65 G2
16 K11 41 B8 66 H1
17 J11 42 A7 67 H3
18 M10 43 B7 68 J1
19 L10 44 B6 69 K1
20 K10 45 A6 70 L1
21 J10 46 B5 71 M1
22 H9 47 A5 72 J2
23 H10 48 A4 73 K2
24 G11 49 B4 74 L2
25 F11 50 B3 75 M2
[12]
Note:
12.Bit# 89 is preset HIGH.
Document #: 38-05354 Rev. *D Page 15 of 27
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
209-ball FBGA Boundary Scan Order
CY7C1464AV25 (512K x 72)
Bit# Ball ID Bit# Ball ID Bit# Ball ID Bit# Ball ID
1 W6 36 F6 71 H6 106 K3
2 V6 37 K8 72 C6 107 K4
3 U6 38 K9 73 B6 108 K6
4 W7 39 K10 74 A6 109 K2
5V7 40J11 75A5 110L2
6 U7 41 J10 76 B5 111 L1
7T7 42H11 77C5 112M2
8 V8 43 H10 78 D5 113 M1
9 U8 44 G11 79 D4 114 N2
10 T8 45 G10 80 C4 115 N1
11 V9 46 F11 81 A4 116 P2
12 U9 47 F10 82 B4 117 P1
13 P6 48 E10 83 C3 118 R2
14 W11 49 E11 84 B3 119 R1
15 W10 50 D11 85 A3 120 T2
16 V11 51 D10 86 A2 121 T1
17 V10 52 C11 87 A1 122 U2
18 U11 53 C10 88 B2 123 U1
19 U10 54 B11 89 B1 124 V2
20 T11 55 B10 90 C2 125 V1
21 T10 56 A11 91 C1 126 W2
22 R11 57 A10 92 D2 127 W1
23 R10 58 C9 93 D1 128 T6
24 P11 59 B9 94 E1 129 U3
25 P10 60 A9 95 E2 130 V3
26 N11 61 D8 96 F2 131 T4
27 N10 62 C8 97 F1 132 T5
28 M11 63 B8 98 G1 133 U4
29 M10 64 A8 99 G2 134 V4
30 L11 65 D7 100 H2 135 W5
31 L10 66 C7 101 H1 136 V5
32 K11 67 B7 102 J2 137 U5
33 M6 68 A7 103 J1 138 Internal
34 L6 69 D6 104 K1
35 J6 70 G6 105 N6
[12, 13]
Note:
13.Bit# 138 is preset HIGH.
Document #: 38-05354 Rev. *D Page 16 of 27
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CY7C1462AV25
CY7C1464AV25
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
Supply Voltage on V
DC to Outputs in Tri-State................... –0.5V to V
Relative to GND........–0.5V to +3.6V
DD
Relative to GND......–0.5V to +V
DDQ
+ 0.5V
DDQ
DD
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................... ... ........... > 200 mA
Operating Range
Range
Commercial 0°C to +70°C 2.5V –5%/+5% 1.7V to V
Industrial –40°C to +85°C
Ambient
Temperature V
DD
V
DDQ
DC Input Voltage....................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range
[14, 15]
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions Min. Max. Unit
V
V
DD
DDQ
Power Supply Voltage 2.375 2.625 V
I/O Supply Voltage for 2.5V I/O 2.375 V
DD
for 1.8V I/O 1.7 1.9 V
V
OH
V
OL
V
IH
V
IL
Output HIGH Voltage for 2.5V I/O, I
for 1.8V I/O, I
Output LOW Voltage for 2.5V I/O, I
for 1.8V I/O, I
Input HIGH Voltage
[14]
for 2.5V I/O 1.7 VDD + 0.3V V
for 1.8V I/O 1.26 V
Input LOW Voltage
[14]
for 2.5V I/O –0.3 0.7 V
= −1.0 mA 2.0 V
OH
= –100 µA1.6V
OH
= 1.0 mA 0.4 V
OL
= 100 µA, 0.2 V
OL
+ 0.3V V
DD
for 1.8V I/O –0.3 0.36 V
I
X
I
OZ
I
DD
Input Leakage Current
GND ≤ VI ≤ V
except ZZ and MODE
Input Current of MODE Input = V
Input = V
Input Current of ZZ Input = V
Input = V
SS
DD
SS
DD
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply V
DD
f = f
= Max., I
= 1/t
MAX
DDQ
–5 5 µA
–30 µA
–5 µA
Output Disabled –5 5 µA
DDQ,
OUT
CYC
= 0 mA,
4-ns cycle, 250 MHz 435 mA
5-ns cycle, 200 MHz 385 mA
5 µA
30 µA
6-ns cycle, 167 MHz 335 mA
I
SB1
I
SB2
I
SB3
I
SB4
Notes:
14.Overshoot: V
15.T
Power-up
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
(AC) < V
IH
: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time V
+1.5V (Pulse width less than t
DD
Max. VDD, Device Deselected,
≥ VIH or VIN ≤ VIL, f = f
V
IN
1/t
CYC
Max. V
V
IN
f = 0
Max. V
V
IN
f = f
, Device Deselected,
DD
≤ 0.3V or VIN > V
, Device Deselected,
DD
≤ 0.3V or VIN > V
= 1/t
MAX
CYC
DDQ
DDQ
MAX
− 0.3V,
− 0.3V,
Max. VDD, Device Deselected,
V
≥ VIH or VIN ≤ VIL, f = 0
IN
/2), undershoot: VIL(AC)> –2V (Pulse width less than t
CYC
=
All speed grades 185 mA
All speed grades 120 mA
All speed grades 160 mA
All speed grades 135 mA
/2).
< V
and V
IH
DD
DDQ
< VDD.
CYC
DD
V
Document #: 38-05354 Rev. *D Page 17 of 27
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Capacitance
[16]
Parameter Description Test Conditions
C
Input Capacitance TA = 25°C, f = 1 MHz,
IN
C
C
CLK
I/O
Clock Input Capacitance 3 7 5 pF
Input/Output Capacitance 5.5 6 7 pF
Thermal Resistance
[16]
V
DD
= 2.5V V
DDQ
= 2.5V
Parameters Description Test Conditions
Θ
JA
Θ
JC
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
T est conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
= 50Ω
0
R
L
VT= 1.5V
(a) (b)
3.3V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
2.5V I/O Test Load
OUTPUT
= 50Ω
Z
0
= 1.25V
V
T
R
L
(a) (b)
Note:
16.Tested initially and after any design or process change that may affect these parameters.
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 317Ω
R = 351Ω
R = 1667Ω
R = 1538Ω
100 TQFP
Max.
165 FBGA
Max.
209 FBGA
Max. Unit
6.5 7 5 pF
100 TQFP
Package
165 FBGA
Package
209 FBGA
Package Unit
25.21 20.8 25.31 °C/W
2.58 3.2 4.48 °C/W
V
DDQ
GND
≤ 1ns
ALL INPUT PULSES
10%
90%
90%
10%
(c)
V
GND
DDQ
≤ 1ns
ALL INPUT PULSES
10%
90%
90%
10%
(c)
≤ 1ns
≤ 1ns
Document #: 38-05354 Rev. *D Page 18 of 27
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Switching Characteristics Over the Operating Range
Parameter Description
[17]
t
Power
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
VCC (typical) to the first access read or write 1 1 1 ms
Clock Cycle Time 4.0 5.0 6.0 ns
Maximum Operating Frequency 250 200 167 MHz
Clock HIGH 1.5 2.0 2.4 ns
Clock LOW 1.5 2.0 2.4 ns
Data Output Valid After CLK Rise 2.6 3.2 3.4 ns
OE LOW to Output Valid 2.6 3.0 3.4 n s
Data Output Hold After CLK Rise 1.0 1.5 1.5 ns
Clock to High-Z
Clock to Low-Z
OE HIGH to Output High-Z
OE LOW to Output Low-Z
[18, 19, 20]
[18, 19, 20]
[18, 19, 20]
[18, 19, 20]
Address Set-up Before CLK Rise 1.2 1.4 1.5 ns
Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns
CEN Set-up Before CLK Rise 1.2 1.4 1.5 ns
WE, BWx Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise 1.2 1.4 1.5 ns
Chip Select Set-up 1.2 1.4 1.5 ns
Address Hold After CLK Rise 0.3 0.4 0.5 ns
Data Input Hold After CLK Rise 0.3 0.4 0.5 ns
CEN Hold After CLK Rise 0.3 0.4 0.5 ns
WE, BWx Hold After CLK Rise 0.3 0.4 0.5 ns
ADV/LD Hold after CLK Rise 0.3 0.4 0.5 ns
Chip Select Hold After CLK Rise 0.3 0.4 0.5 ns
[21, 22]
–250 –200 –167
UnitMin. Max. Min. Max. Min. Max.
2.6 3.0 3.4 ns
1.0 1.3 1.5 ns
2.6 3.0 3.4 ns
000ns
1.2 1.4 1.5 ns
Notes:
17.This part has a voltage regulator internally; t
initiated.
, t
, t
18.t
CHZ
CLZ
19.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition , bu t re flect p arame te rs g uara nteed over worst case user co ndit ions. Device is designe d
to achieve High-Z prior to Low-Z under the same system conditions.
20.This parameter is sampled and not 100% tested.
21.Timing reference is 1.25V when V
22.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
EOLZ
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-sta te voltage.
EOHZ
DDQ =
is the time power needs to be supplied above VDD minimum initially , bef ore a Read or Write operation can be
power
is less than t
EOHZ
2.5V and 0.9V when V
EOLZ
and t
DDQ
is less than t
CHZ
= 1.8V.
to eliminate bus contention between SRAMs when sharing the same
CLZ
Document #: 38-05354 Rev. *D Page 19 of 27
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Switching Waveforms
123456789
10
I
45678910
123
CLK
CEN
CE
WE
BW
[23, 24, 25]
t
CENS
t
CES
x
t
CENH
t
CEH
Read/Write/Timing
ADV/LD
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
t
CYC
t
t
CL
CH
ADDRESS
Data
n-Out (DQ)
A1 A2
t
t
AH
AS
A3
t
t
DH
DS
D(A1) D(A2) D(A5)Q(A4)Q(A3)
A4
t
CO
t
D(A2+1)
CLZ
t
DOH
A5 A6 A7
t
OEHZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
DON’T CARE UNDEFINED
NOP, STALL and DESELECT Cycles
CLK
CEN
CE
ADV/LD
WE
BWx
[23, 24, 26]
t
OEV
t
OELZ
Q(A4+1)
READ
Q(A6)
t
CHZ
t
DOH
WRITE
D(A7)
Q(A6)
DESELECT
ADDRESS
Data
A1
A2
A3 A4
D(A1) Q(A2) Q(A3)
A5
D(A4)
Q(A5)
t
CHZ
In-Out (DQ)
D(A1)
READ
Q(A2)
STALL NOP READ
READ
Q(A3)
WRITE
D(A4)
STALLWRITE
Q(A5)
DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
Notes:
23.For this waveform ZZ is tied low.
24.When CE
25.Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Int erleaved).Burst operations are optional.
26.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN
is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
being used to create a pause. A write is not performed during this cycle.
Document #: 38-05354 Rev. *D Page 20 of 27
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Switching Waveforms (continued)
A
ZZ Mode Timing
[27, 28]
CLK
t
ZZ
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
t
ZZREC
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
Outputs (Q)
Notes:
27.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28.I/Os are in High-Z when exiting ZZ sleep mode.
t
ZZI
I
DDZZ
High-Z
DON’T CARE
t
RZZI
DESELECT or READ Only
Document #: 38-05354 Rev. *D Page 21 of 27
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Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
167 CY7C1460AV25-167AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1462AV25-167AXC
CY7C1460AV25-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1462AV25-167BZC
CY7C1460AV25-167BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1462AV25-167BZXC
CY7C1464AV25-167BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1464AV25-167BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1460AV25-167AXI 51-85050 10 0-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1462AV25-167AXI
CY7C1460AV25-167BZI 51-85165 165-ball Fin e-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1462AV25-167BZI
CY7C1460AV25-167BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1462AV25-167BZXI
CY7C1464AV25-167BGI 51-85167 209-ball Fine-Pitch Ba ll Grid Array (14 × 22 × 1.76 mm)
CY7C1464AV25-167BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
200 CY7C1460AV25-200AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1462AV25-200AXC
CY7C1460AV25-200BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1462AV25-200BZC
CY7C1460AV25-200BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1462AV25-200BZXC
CY7C1464AV25-200BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1464AV25-200BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1460AV25-200AXI 51-85050 10 0-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free lndustrial
CY7C1462AV25-200AXI
CY7C1460AV25-200BZI 51-85165 165-ball Fin e-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1462AV25-200BZI
CY7C1460AV25-200BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1462AV25-200BZXI
CY7C1464AV25-200BGI 51-85167 209-ball Fine-Pitch Ba ll Grid Array (14 × 22 × 1.76 mm)
CY7C1464AV25-200BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05354 Rev. *D Page 22 of 27
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
Speed
(MHz) Ordering Code
250 CY7C1460AV25-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial
CY7C1462AV25-250AXC
CY7C1460AV25-250BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1462AV25-250BZC
CY7C1460AV25-250BZXC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1462AV25-250BZXC
CY7C1464AV25-250BGC 51-85167 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1464AV25-250BGXC 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
CY7C1460AV25-250AXI 51-85050 10 0-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial
CY7C1462AV25-250AXI
CY7C1460AV25-250BZI 51-85165 165-ball Fin e-Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1462AV25-250BZI
CY7C1460AV25-250BZXI 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free
CY7C1462AV25-250BZXI
CY7C1464AV25-250BGI 51-85167 209-ball Fine-Pitch Ba ll Grid Array (14 × 22 × 1.76 mm)
CY7C1464AV25-250BGXI 209-ball Fine-Pitch Ball Grid Array (14 × 22 × 1.76 mm) Lead-Free
visit www.cypress.com for actual products offered.
Package
Diagram Part and Package Type
Operating
Range
Document #: 38-05354 Rev. *D Page 23 of 27
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Package Diagrams
R 0.08 MIN.
0.20 MAX.
0.25
GAUGE PLANE
0°-7°
0.60±0.15
1.00 REF.
20.00±0.10
22.00±0.20
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
14.00±0.10
100
1
30
31 50
0° MIN.
R 0.08 MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
1.40±0.05
12°±1°
(8X)
SEATING PLANE
NOTE:
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
51-85050-*B
SEE DETAIL
0.20 MAX.
1.60 MAX.
0.10
A
Document #: 38-05354 Rev. *D Page 24 of 27
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Package Diagrams (continued)
TOP VIEW
PIN 1 CORNER
165-ball FBGA (15 x 17 x 1.4 mm) (51-85165)
1110986754321
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
BOTTOM VIEW
Ø0.05 M C
Ø0.25 M C A B
11
Ø0.45±0.05(165X)
PIN 1 CORNER
1
2345678910
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
+0.05
0.25 C
0.53±0.05
SEATING PLANE
C
0.36
0.35
-0.10
0.15 C
1.40 MAX.
17.00±0.10
A
14.00
0.15(4X)
1.00
7.00
5.00
B
15.00±0.10
1.00
10.00
51-85165-*A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Document #: 38-05354 Rev. *D Page 25 of 27
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Package Diagrams (continued)
209-ball FBGA (14 x 22 x 1.76 mm) (51-85167)
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
51-85167-**
ZBT is a registered trademark of Integrated Device Technology, Inc. No Bus Latency and NoBL are trademarks of Cypress
Semiconductor Corporation. All product and company names mentioned in this document are tradema rks of their respective
holders.
Document #: 38-05354 Rev. *D Page 26 of 27
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change wi t hou t notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not auth orize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document History Page
Document Title: CY7C1460AV25/CY7C1462A V25/CY7C1464AV25 36-Mbit (1-Mbit x 36/2-Mbit x 18/512K x 72) Pipelined
SRAM with NoBL™ Architecture
Document Number: 38-05354
REV. ECN No. Issue Date
** 254911 See ECN SYT New data sheet
*A 303533 See ECN SYT Changed H9 pin from V
*B 331778 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209
*C 417547 See ECN RXU Converted from Preliminary to Final
*D 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on V
Orig. of
Change Description of Change
Part number changed from previous revision (new and old part number
differ by the letter “A”)
to VSS on the Pin Configuration table for 209
FBGA on Page # 5
SSQ
Changed the test condition from VDD = Min. to VDD = Max for VOL in the
Electrical Characteristics table
Replaced Θ
Packages on the Thermal Resistance Table
Changed I
and 167 Mhz respectively
Changed I
Mhz respectively
Changed I
Changed I
Mhz respectively
Changed I
Changed C
TQFP Package
Changed tCO from 3.0 to 3.2 ns and t
Speed Bin
and Θ
JA
from 450, 400 & 350 mA to 435, 385 & 335 mA for 250, 200
DD
from 190, 180 and 170 mA to 185 mA for 250, 200 and 167
SB1
from 80 mA to 100 mA for all frequencies
SB2
from 180, 170 & 160 mA to 160 mA for 250, 200 and 167
SB3
from 100 mA to 110 mA for all frequencies
SB4
, C
IN
CLK
from TBD to respective Thermal Values for All
JC
and C
to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for
I/O
from 1.3 ns to 1.5 ns for 200 Mhz
DOH
Added lead-free information for 100 TQFP, 165 FBGA and 209 FBGA
packages
FBGA Package as per JEDEC standards and updated the Pin Definitions
accordingly
Modified V
Changed C
OL, VOH
FBGA Package
, C
IN
CLK
test conditions
and C
to 7, 7and 6 pF from 5, 5 and 7 pF for 165
I/O
Added Industrial Temperature Grade
Changed I
tively
SB2
and I
from 100 and 110 mA to 120 and 135 mA respec-
SB4
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified test condition from V
Changed IX current value in MODE from –5 & 30 µA to –30 & 5 µA respec-
tively and also Changed I
µA respectively on page# 19
current value in ZZ from –30 & 5 µA to –5 & 30
X
DDQ
< V
DD to VDDQ
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in
the Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Changed t
AC Switching Characteristics table.
, t
from 25 ns to 20 ns and t
TH
TL
TDOV
Updated the Ordering Information table.
≤ V
DD
Relative to GND.
DDQ
from 5 ns to 10 ns in TAP
Document #: 38-05354 Rev. *D Page 27 of 27
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