Cypress CY7C1462AV25, CY7C1460AV25, CY7C1464AV25 User Manual

CY7C1460AV25

a b c d

CY7C1462AV25 CY7C1464AV25

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined SRAM with NoBL™ Architecture

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz

• Internally self-timed output buffer control to eliminate the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined operation

• Byte Write capability

• 2.5V core power supply

• 2.5V/1.8V I/O power supply

• Fast clock-to-output times — 2.6 ns (for 250-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes

• CY7C1460AV25, CY7C1462AV25 available in JEDEC-standa r d le ad-free 100-pin TQFP package, lead-free and non-lead-free 165-ball FBGA package. CY7C1464AV25 available in lead-free and non-lead-free 209-ball FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

) pin to suspend operation

Functional Description

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are

2.5V, 1M x 36/2M x 18/512 x 72 Synchronous pipe lined b urst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are equipped with the advanced (NoBL) logic requi red to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are pin-compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BW

–BWd for CY7C1460AV25 and BWa–BWb for

CY7C1462AV25) and a Write Enable (WE

–BWh for CY7C1464AV25,

) input. All writes are

conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE

asynchronous Output Enable (OE

, CE2, CE3) and an

) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

) signal,

Logic Block Diagram–CY7C1460AV25 (1M x 36)

A0, A1, A

MODE

CLK

ADV/LD

OE CE1 CE2 CE3

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05354 Rev. *D Revised June 22, 2006

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

ADV/LD

WRITE ADDRESS

D1D0Q1

BURST LOGIC

A1' A0'

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

U T

S E

R E G

S T

R S

INPUT

U T

T B

S T E E R

I N G

DQs

DQP

R S

[+] Feedback

a b

s P

C C

Logic Block Diagram–CY7C1462AV25 (2M x 18)

A0, A1, A

MODE

CLK

ADDRESS

WRITE ADDRESS

A1 A0

ADV/LD

WRITE ADDRESS

D1D0Q1

BURST LOGIC

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

A1' A0'

ADV/LD

BW BW

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

OE CE1 CE2 CE3

READ LOGIC

Sleep

Control

Logic Block Diagram–CY7C1464AV25 (512K x 72)

A0, A1, A

MODE

ADV/LD

ADDRESS

WRITE ADDRESS

A1 A0

ADV/LD

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

D1D0Q1

BURST

LOGIC

O U T P

N S

WRITE

DRIVERS

A1' A0'

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

MEMORY

ARRAY

INPUT

E G

E R S

S E N S E

P S

O U T P U T

R E G

I S T E R S

INPUT

O U T P

T A

DQs

T E E R

I N G

O U T P

T A

B U

I N G

DQP

E R S

DQ DQ DQ DQ DQ DQ DQ DQ DQ

OE CE1 CE2 CE3

READ LOGIC

Sleep

Control

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.2 3.4 ns Maximum Operating Current 435 385 335 mA Maximum CMOS Standby Current 120 120 120 mA

Document #: 38-05354 Rev. *D Page 2 of 27

[+] Feedback

Pin Configurations

100-pin TQFP Pinout

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

DQPc

DQc

DDQ

DQc DQc

DDQ

DQc

DQd DQd

DDQ

DQd DQd DQd

DQd

DDQ

DQd DQd

DQPd

1CE2

BWd

BWc

VDDV

CLKWECEN

BWa

BWb

100999897969594939291908988878685848382

1 2 3 4 5

6 7 8 9 10 11 12 13 14 15 16

CY7C1460AV25

(1M × 36)

17 18 19 20 21 22 23 24 25

26 27 28 29 30

31323334353637383940414243444546474849

ADV/LD

DDQ SS

SS DDQ

DDQ SS

SS DDQ

NC NC NC

DDQ

NC DQb DQb

DDQ

DQb DQb

V DQb DQb

DDQ

V DQb

DQb

DQPb

DDQ

NC NC NC

DQPb

DQb

DQa

DQPa

1CE2

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

bBWa

VDDV

CLKWECEN

CY7C1462AV25

(2M × 18)

ADV/LD

DQP

DQa DQa V

NC V

ZZ DQa DQa V

DQa DQa NC NC V

NC NC NC

73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

AAA

MODE

A1A

NC/144M

NC/288M

AAA

NC/72M

AAA

MODE

1A0

NC/288M

AAA

NC/144M

NC/72M

Document #: 38-05354 Rev. *D Page 3 of 27

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Pin Configurations (continued)

234 5671

A B C

D E

F G H

J K

L M

N P

NC/576M

NC/1G

DQP

NC/144M

MODE

A A

NC/72M

CE2 V V V V V

V V V V V

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1460AV25 (1M × 36)

DDQ DDQ

DDQ DDQ DDQ

DDQ DDQ DDQ DDQ DDQ

A A

TDI

TMS

CLK

CEN

TDO

TCKA0

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

891011

ADV/LD

A A

DDQ

NC DQP

DQP

NC/288M

A B C

D E F

J K L

N P

CY7C1462AV25 (2M × 18)

2345671

NC/576M

NC/1G

NC NC

NC V NC NC

DQP

NC/144M

MODE

A A

NC NC NC NC

NC NC

NC/72M

CE CE2

DDQ

A A

NC TDI

TMS

CE CLK

SS SS

891011

A A

DDQ

A NC DQP NC NC NC NC

DQ DQ DQ DQ

SS SS

SS SS SS

SS SS SS SS

ADV/LD

DD DD

CEN

V V

V V V

V V V V

TDO TCKA0

a a a a

ZZ NCV NC NC

NC NC

NC/288M

Document #: 38-05354 Rev. *D Page 4 of 27

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Pin Configurations (continued)

123456789 1110

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV25 (512K x 72)

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

A B C D E F G H J K L M N P R T U V W

DQg DQg

DQPg

DQc

NC DQh

DQh DQh

DQh

DQPd

DQd DQd

DQg

DQg DQg

DQPc

DQc

DQc DQc

DQc

DQh DQh DQh

DQh DQPh

DQd

DQd DQd DQd

BWS

DDQ

CLK

DDQ

NC/144M

BWS

DDQ

NC MODE

TMS

TDI TDO TCK

BWS

DDQ

ADV/LD

V V V

V V

A NC NC

WE CE OE

NC NC

CEN

NC NC

NC/576M

NC/1G V

V V

NC/72M A NC/288M

AA A1 A0

DQb

DDQ

DQb

DQb DQPf

DQf DQf

DQf

DQf NC

DQa DQa

DQPa

DQe

BWS

V V V

V V

V V V

DQe

DQe DQe

DQb

DQb DQb

DQPb

DQf

DQf DQf

DQf

DQa DQa DQa

DQa DQPe

DQe

DQe DQe DQe

Pin Definitions

Pin Name I/O Type Pin Description

A0 A1

Input-

Synchronous

BW BW BW BW BW

BW BW BW

a b c d e

f g h

Input-

Synchronous

Input-

Synchronous

ADV/LD Input-

Synchronous

CLK Input-

Clock

Document #: 38-05354 Rev. *D Page 5 of 27

Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BW

controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQP

controls DQ

and DQP

controls DQg and DQP

f, BWg

controls DQa and DQPa, BWb controls DQb and DQPb,

controls DQh and DQPh.

g, BWh

e, BWf

Write Enable Input, active LOW . Sampled on the rising edge of CLK if CEN is active LOW . This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN new address can be loaded into the device for an access. After being deselected, ADV/LD

is asserted LOW) the internal burst counter is advanced. When LOW, a

should

be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN

CLK is only recognized if CEN

is active LOW.

[+] Feedback

CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

Pin Definitions (continued)

Pin Name I/O Type Pin Description

CEN

DQP

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order .

TDO JT AG serial output

TDI JTAG serial input

TMS Test Mode Select

TCK JTAG-Clock Clock input to the JTAG circuitry.

DDQ

NC N/A No connects. This pin is not connected to the die.

NC/72M N/A Not connected to the die. Can be tied to any voltage level.

NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level. NC/576M N/A Not connected to the die. Can be tied to any voltage level.

NC/1G N/A Not connected to the die. Can be tied to any voltage level.

ZZ Input-

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select/deselect the device.

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE3 to select/deselect the device.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE2 to select/deselect the device.

Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.

Input-

Synchronous

I/O-

Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN deselect the device, CEN

can be used to extend the previous cycle when required.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A controlled by OE as outputs. When HIGH, DQ cally tri-stated during the data portion of a write sequence, during the first clock when emerging

during the previous clock rise of the read cycle. The direction of the pins is

and the internal control logic. When OE is asserted LOW, the pins can behave

–DQd are placed in a tri-state condition. The outputs are automati-

from a deselected state, and when the device is deselected, regardless of the state of OE.

I/O-

Synchronous

Bidirectional Data Parity I/O lines . Functionally, these signals are identical to DQ write sequences, DQP BW

, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,

is controlled by BWg, DQPh is controlled by BWh.

DQP

is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by

Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Synchronous

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

Synchronous

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

Synchronous

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground Ground for the device. Should be connected to ground of the system.

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition

Asynchronous

with data integrity preserved. During normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

does not

. During

[31:0]

Document #: 38-05354 Rev. *D Page 6 of 27

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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

Functional Overview

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN

). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t

) is 2.6 ns (250-MHz device).

Accesses can be initiated by asserting all three Chip Enables (CE

, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN

) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE conduct byte write operations.

Write operations are qualified by the Write Enable (WE

). BW

can be used to

[x]

). All writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE

, CE2, CE3) and an

) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN and CE signal WE

are ALL asserted active, (3) the Write Enable input

is deasserted HIGH, and (4) ADV/LD is asserted

is asserted LOW, (2) CE1, CE2,

LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.6 ns (200-MHz device) provided OE

is active LOW. After the first clock of the read access the output buffers are controlled by OE

and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.

Burst Read Accesses

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD

will increment

the internal burst counter regardless of the state of chip enables inputs or WE

. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN and CE is asserted LOW. The address presented to the address inputs

are ALL asserted active, and (3) the write signal WE

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE allows the external logic to present the data on DQ (DQ

a,b,c,d,e,f,g,h

a,b,c,d

for CY7C1462AV25). In addition, the address for the subse-

/DQP

a,b,c,d,e,f,g,h

for CY7C1460AV25 and DQ

a,b,c,d

for CY7C1464AV25,

input signal. This

and DQP

/DQP

a,b

quent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ

/DQP

a,b,c,d,e,f,g,h

for CY7C1460AV25 and DQ

a,b,c,d

(DQ

a,b,c,d,e,f,g,h

a,b,c,d

for CY7C1462AV25) (or a subset for byte write operations, see

for CY7C1464AV25,

and DQP

/DQP

a,b

Write Cycle Description table for details) inputs is latched into the device and the write is complete.

The data written during the Write operation is controlled by BW (BW

a,b,c,d,e,f,g,h

CY7C1460AV25 and BW CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 provides

for CY7C1464AV25, BW

for CY7C1462AV25) signals. The

a,b

a,b,c,d

for

byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE the selected Byte Write Select (BW

) input will selectively write

) with

to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE can be deasserted HIGH before presenting data to the DQ DQP (DQ DQ for CY7C1462AV25) inputs. Doing so will three-state the

a,b,c,d

a,b,c,d,e,f,g,h

/DQP

a,b,c,d,e,f,g,h

for CY7C1460AV25 and DQ

a,b,c,d

output drivers. As a safety precaution, DQ (DQ

a,b,c,d,e,f,g,h

a,b,c,d

for CY7C1462AV25) are automatically three-stated during the

/DQP

a,b,c,d,e,f,g,h

for CY7C1460AV25 and DQ

a,b,c,d

for CY7C1464AV25,

data portion of a write cycle, regardless of the state of OE

and

/DQP

a,b

and DQP

/DQP

a,b

Burst Write Accesses

The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD

must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD

is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW

(BW

a,b,c,d,e,f,g,h

for

)

Document #: 38-05354 Rev. *D Page 7 of 27

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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

CY7C1460AV25, BW CY7C1462AV25) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to e ntering the “sleep” mode. CE for the duration of t

for CY7C1460AV25 and BW

a,b,c,d

, CE2, and CE3, must remain inactive

after the ZZ input returns LOW.

ZZREC

a,b

for

Interleaved Burst Address Table (MODE = Floating or V

First

Address

Second

Address

)

Third

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

Second

Address

Third

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description T est Conditi ons Min. Max. Unit

DDZZ

ZZS

ZZREC

ZZI

RZZI

Truth Table

Sleep mode standby current ZZ > VDD − 0.2V 100 mA Device operation to ZZ ZZ > VDD − 0.2V 2t ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to sleep current This parameter is sampled 2t ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[1, 2, 3, 4, 5, 6, 7]

CYC

Fourth

Address

Fourth

Address

ns ns ns

Address

Operation

Used CE ZZ ADV/LD

BWxOE CEN CLK DQ

Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H – Sleep MODE None X H X X X X X X Tri-State

Notes:

1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE signifies that the desired byte write selects are asserted, see Write Cycle Descript i on table for details.

2. Write is defined by WE

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE

= H inserts wait states.

5. CEN

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when

7. OE OE

is inactive or when the device is deselected, and DQs=data when OE is active.

and BWX. See Write Cycle Description table for details.

stands for ALL Chip Enables active. BWx = L signifies at least one Byte Wri te Select is active, BW x = V a lid

signal.

Document #: 38-05354 Rev. *D Page 8 of 27

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CY7C1460AV25 CY7C1462AV25 CY7C1464AV25

Partial Write Cycle Description

Function (CY7C1460AV25) WE BW

[1, 2, 3, 8]

Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQ Write Byte b – (DQ

and DQPa) LHHHL

and DQPb)LHHLH

Write Bytes b, a L H H L L Write Byte c – (DQ

and DQPc)LHLHH

Write Bytes c, a L H L H L Write Bytes c, b L H LL L H Write Bytes c, b, a L H L L L Write Byte d – (DQ

and DQPd)LLHHH

Write Bytes d, a L L H H L Write Bytes d, b LLHLH Write Bytes d, b, a L L H L L Write Bytes d, c L L L H H Write Bytes d, c, a L L L H L Write Bytes d, c, b L L L L H Write All Bytes L L L L L

Function (CY7C1462AV25) WE BW

Read H X X Write – No Bytes Written L H H Write Byte a – (DQ Write Byte b – (DQ

and DQPa)LHL

and DQPb)LLH

Write Both Bytes L L L

Function (CY7C1464AV25) WE

Read HX Write – No Bytes Written L H Write Byte X − (DQ

and DQP

Write All Bytes LAll BW

Note:

8. Table only lists a partial listing of the byte write combi nations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

= L

Document #: 38-05354 Rev. *D Page 9 of 27

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