Cypress CY7C1446AV33, CY7C1440AV33, CY7C1442AV33 User Manual

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1440AV33, CY7C1442AV33 available in lead-free
100-pin TQFP package, lead-free and non-lead-free
165-ball FBGA package. CY7C1446AV33 available in
lead-free and non-lead-free 209-ball FBGA package

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

®

interleaved or linear burst sequences

®

Functional Description

The CY7C1440AV33/CY7C1442AV33/CY7C1446A V33 SRAM
integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE3), Burst

1

Control inputs (ADSC
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active

causes all bytes to be written.

LOW
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33

operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.

, ADSP, and ADV), Write Enables (BW

[1]

) and the ZZ pin.

) or

) are active. Subsequent

X

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.2 3.4 ns
Maximum Operating Current 475 425 375 mA
Maximum CMOS Standby Current 120 120 120 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05383 Rev. *E Revised June 23, 2006

[+] Feedback

Logic Block Diagram – CY7C1440AV33 (1M x 36)

A

A

A
B

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

BW

BW

BWE

GW

CE
CE
CE

OE

C

B

A

1
2
3

ADDRESS
REGISTER

D ,

DQPD

DQ

BYTE

WRITE REGISTER

C ,

DQPC

DQ

BYTE

WRITE REGISTER

B ,

DQPB

DQ

BYTE

WRITE REGISTER

DQ

A ,

DQPA

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D

DQ

BYTE

WRITE DRIVER

C ,

DQ

BYTE

WRITE DRIVER

B ,

DQ

BYTE

WRITE DRIVER

DQ

BYTE

WRITE DRIVER

,DQP

DQPC

DQPB

A ,

DQPA

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

D

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP

A
B
C
D

ZZ

SLEEP

CONTROL

Logic Block Diagram – CY7C1442AV33 (2M x 18)

0, A1, A

MODE

ADV

CLK

ADSC

ADSP

BW

BW

B

A

BWE

GW

CE

1

CE2
CE3

OE

ADDRESS
REGISTER

COUNTER AND

CLR

DQB,DQP

B

WRITE REGISTER

DQA,DQP

A

WRITE REGISTER

ENABLE

REGISTER

2

BURST
LOGIC

PIPELINED

ENABLE

A[1:0]

Q1

Q0

DQB,DQP

B

WRITE DRIVER

DQA,DQP

A

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

DQs
DQP
DQP

INPUT

REGISTERS

ZZ

SLEEP

CONTROL

Document #: 38-05383 Rev. *E Page 2 of 31

[+] Feedback

A

A
B
C
D
E
F
G
H

Logic Block Diagram – CY7C1446AV33 (512K x 72)

DQH, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQE, DQP

WRITE DRIVER

DQD, DQP

WRITE DRIVER

DQC, DQP

WRITE DRIVER

DQB, DQP

WRITE DRIVER

DQA, DQP

WRITE DRIVER

ENABLE

REGISTER

ADDRESS
REGISTER

H

F

F

E

D

C

B

A

BINARY

COUNTER

CLR

PIPELINED

ENABLE

A[1:0]

Q1

Q0

DQH, DQP

WRITE DRIVER

DQG, DQP

WRITE DRIVER

DQF, DQP

WRITE DRIVER

DQE, DQP

BYTE

“a”

WRITE DRIVER

WRITE DRIVER

DQD, DQP

WRITE DRIVER

DQC, DQP

WRITE DRIVER

DQB, DQP

WRITE DRIVER

DQA, DQP

WRITE DRIVER

0, A1,A

MODE

ADV

CLK

ADSC
ADSP

BW

BW

BW

BW

BW

BW

BW

BW

BWE

GW
CE1
CE2
CE3

H

G

F

E

D

C

B

A

OE

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

H

G

F

E

MEMORY

ARRAY

D

C

SENSE

B

A

AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP
DQP
DQP
DQP
DQP

ZZ

SLEEP

CONTROL

Document #: 38-05383 Rev. *E Page 3 of 31

[+] Feedback

Pin Configurations

1CE2

A

A

BWD

CE

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

100-pin TQFP Pinout

BWA

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

ADV

A

A

BWC

BWB

1CE2

A

A

NCNCBWBBWA

CE

CE3VDDV

SS

CLKGWBWEOEADSC

ADSP

ADV

A

A

DQP
DQC
DQc

V

DDQ

V

SSQ

DQC
DQC
DQC
DQC

V

SSQ

V

DDQ

DQC
DQC

NC

V

NC

V
DQD
DQD

V

DDQ

V

SSQ

DQD
DQD
DQD
DQD

V

SSQ

V

DDQ

DQD
DQD

DQPD

100999897969594939291908988878685848382

C

1
2
3
4
5
6
7
8
9
10
11
12
13
14

DD

15
16

SS

17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1440AV33

(1M x 36)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

A

NC/72M

A

A

DD

V

AAAAA

SS

V

81

DQPB

80

DQB

79

DQB

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

DQB
DQB
DQB
DQB
V

SSQ

V

DDQ

DQB
DQB
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SSQ

DQA
DQA
DQA
DQA
V

SSQ

V

DDQ

DQA
DQA
DQPA

A

NC
NC
NC

V

DDQ

V

SSQ

NC

NC
DQ
DQB

V

SSQ

V

DDQ

DQB
DQB

NC

V

NC

V
DQB
DQB

V

DDQ

V

SSQ

DQB
DQB

DQPB

NC

V

SSQ

V

DDQ

NC
NC
NC

B

DD

SS

50

A

A

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1442AV33

(2M x 18)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

A

NC/72M

A

A

DD

V

AAAAA

SS

V

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQA
DQA
V

SSQ

V

DDQ

DQA
DQA
V

SS

NC
V

DD

ZZ
DQ
DQA
V

DDQ

V

SSQ

DQA
DQA
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

50

A

A

Document #: 38-05383 Rev. *E Page 4 of 31

[+] Feedback

Pin Configurations (continued)

2345671

NC/288M

A
B
C

D
E
F
G

H

J
K
L

M

N
P

R

NC/144M

DQP

C

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

DQP

D

NC

MODE

A

A

NC

DQ
DQ
DQ

DQ

NC
DQ
DQ
DQ

DQ

NC

NC/72M

A

CE
CE2

V

DDQ

V

C
C
C
C

V
V
V

DDQ
DDQ
DDQ

DDQ

NC

V
V
V
V
V

DDQ
DDQ
DDQ
DDQ
DDQ

D
D
D
D

A
A

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1440AV33 (1M x 36)

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

BW

V
V

V
V
V

V
V

V
V
V

B

SS
SS

SS
SS
SS

SS
SS

SS
SS
SS

C
D

NC

TDI

TMS

CE

CLK

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

A0

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO
TCK

ADSC

V
V

V
V
V

V
V
V
V

V
V

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

891011

ADV

OE ADSP

V
V

V
V
V

V
V
V
V
V

DDQ
DDQ

DDQ
DDQ
DDQ

NC

DDQ
DDQ
DDQ
DDQ
DDQ

A

A

SS

DD
DD
DD
DD

DD
DD
DD
DD

DD
SS

A

A

A
A

NC/1G DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

NC

NC/576M

B

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

A
AA

A
B
C

D
E

F
G
H

J
K

L

M

N
P

R

CY7C1442AV33 (2M x 18)

2345671

NC/288M
NC/144M

NC
NC

NC V
NC
NC

NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

A
A

NC

DQ

B

DQ

B

DQ

B

DQ

B

NC
NC
NC
NC

NC
NC

NC/72M

A

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

BW

1

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A
A

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

891011

CE
CLK

A

V

SS

V

SS
SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD
DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A
A

NC/1G DQP

NC
NC
NC
NC

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

A

NC/576M

DQ

A

DQ

A

DQ

A

DQ

A

ZZ
NCV
NC
NC

NC
NC

A
AA

A

Document #: 38-05383 Rev. *E Page 5 of 31

[+] Feedback

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Pin Configurations

123456789 1110

A

DQ
DQ

B

DQ

C
D

DQ

E

DQP

DQ

F
G

DQ

H
J
K
L
M
N
P
R
T
U
V
W

DQ

DQ

NC

DQ
DQ

DQ
DQ

DQP

DQ
DQ

DQ
DQ

(continued)

DQ

G

G
G

G

C

C

C

H
H

H

H

D

D
D

D

G

DQ

G

DQ

G

DQ

G

DQP

G

DQ

DQ

C

DQ

DQ

NC

DQ
DQ
DQ

DQ
DQP

D

DQ

DQ
DQ
DQ

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1446AV33 (512K × 72)

A

BWS

BWS

V

SS

V

C

DDQ

V

C

SS

V

DDQ

C

V

SS

C

V

C

DDQ

CLK

V

DDQ

H

V

SS

H

V

DDQ

H

V

SS

H

V

DDQ

H

V

D

SS

NC/72M

D

AA

D

TMS

D

CE

BWS

C

BWS

H

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC MODE

A

TDI TDO TCK

ADSP

2

NC/288M

G

NC/144M

D

NC/1G

V

DD

V
V
V

V
V
V
V

V

V

V

NC

AA A

AA

A

SS

DD

SS

DD

SS

DD

SS

DD

SS

DD

ADSC

BW
CE

1

OE

V

DD

NC

NC
NC
NC

V

SS

NC
NC

NC

ZZ

V

DD

ADV
A

NC/576M

GW

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

V

SS

V

DD

NC

AA

A1

A

A0

CE

BWS

BWS

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

NC

A

3

BWS

B

E

BWS

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

F

A

NC

V

DDQ

V

SS

V

DDQ

V

SS

V

DDQ

V

SS

AA

DQ

DQ

DQ
DQ
DQP

DQ
DQ

DQ

DQ

NC

DQ
DQ

DQ
DQ

DQP

DQ
DQ

DQ
DQ

DQ

B

B
B

B

F

F

F

F

F

DQ

DQ
DQ

DQP
DQ

DQ
DQ

DQ

B

B

B

B

B

F

F

F

F

NC

DQ

A
A

A

A

A
E

E
E

E

DQ
DQ
DQ
DQP
DQ

DQ
DQ
DQ

A

A
A
A

E

E

E
E
E

Pin Definitions

Name I/O Description

, A1, A Input-

A

0

BWA, BWB,
BW

, BWD,

C

, BWF,

BW

E

BW

, BW

G

GW

H

Synchronous

Input-

Synchronous

Input-

Synchronous

BWE

Input-

Synchronous

CLK Input-

Clock

CE

1

Input-

Synchronous

Document #: 38-05383 Rev. *E Page 6 of 31

Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP

or ADSC is active LOW, and CE1, CE2, and CE

A1: A0 are fed to the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE

[2]

are sampled active.

3

to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are written, regardless of the values on BW
BWE

).

and

X

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV

is asserted LOW, during a burst operation.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.

and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is

2

[+] Feedback

Pin Definitions (continued)

Name I/O Description

CE

2

CE

3

OE

ADV Input-

ADSP

ADSC

ZZ Input-

DQs, DQP

V

DD

V

SS

V

SSQ

V

DDQ

X

MODE Input-

TDO JTAG serial

TDI JT AG serial input

TMS JT AG serial input

TCK JTAG-

NC – No Connects. Not internally connected to the die
NC/72M,

NC/144M,
NC/288M,
NC/576M,
NC/1G

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.

and CE3 to select/deselect the device. CE2 is sampled only when a new external

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
connected for BGA. Where referenced, CE
for BGA. CE

and CE2 to select/deselect the device. Not available for AJ package version. Not

1

is sampled only when a new external address is loaded.

3

is assumed active throughout this document

3

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,

Synchronous

Input-

Synchronous

it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both

Input-

Synchronous

asserted, only ADSP
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

is recognized. ASDP is ignored when CE1 is deasserted HIGH.

registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP

is recognized.

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a

Asynchronous

non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
read cycle. The direction of the pins is controlled by OE
pins behave as outputs. When HIGH, DQs and DQP

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Ground Ground for the I/O circuitry.

I/O Power Supply Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

Static

or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

output

Synchronous

JT AG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.

Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature

Synchronous

is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.

Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature

Synchronous

is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

Clock

be connected to V

. This pin is not available on TQFP packages.

SS

– No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M

and NC/1G are address expansion pins are not internally connected to the die.

CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

clock rise of the

. When OE is asserted LOW, the

are placed in a tri-state cond i ti on .

X

. This pin is not

DD

. This pin is not

DD

DD

Document #: 38-05383 Rev. *E Page 7 of 31

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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
supports secondary cache in systems utilizing either a linear
or interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is deter­mined by sampling the MODE input. Accesses can be initiated
with either the Processor Address Strobe (ADSP
Controller Address Strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2) CE
signals (GW

is HIGH. The address presented to the address inputs (A)

CE

1

is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP
ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW

inputs are ignored during this first cycle.

ADV
ADSP-triggered Write accesses require two clock cycles to

complete. If GW
data presented to the DQs inputs is written into the corre­sponding address location in the memory array. If GW

Document #: 38-05383 Rev. *E Page 8 of 31

) overrides all Byte Write inputs and writes data to

, CE2, CE3 are all asserted active, and (3) the Write

1

, BWE) are all deserted HIGH. ADSP is ignored if

or ADSC signals, its output will tri-state immedi-

, CE2, CE3 are all asserted active. The address

1

is asserted LOW on the second clock rise, the

). Address advancement

, CE2, CE3) and an

1

) provide for easy bank

or ADSC is asserted LOW,

is asserted LOW, and

, BWE, and BWX) and

) is 2.6ns

CO

) or the

input. A

is ignored if CE

is active

is HIGH,

then the Write operation is controlled by BWE
signals.

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides Byte Write capability that is described in the Write
Cycle Descriptions table. Asserting the Byte Write Enable
input (BWE
selectively write to only the desired bytes. Bytes not selected
during a Byte Write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided
to simplify the Write operations.

Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the Output Enable (OE
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW
and BW
byte(s). ADSC
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV
during this cycle. If a global Write is conducted, the data

1

presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.

Because CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
provides a two-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input. Asserting ADV
cally increment the burst counter to the next address in the
burst sequence. Both Read and Write burst operations are
supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering

the

“sleep” mode. CE
remain inactive for the duration of t
returns LOW.

) with the selected Byte Write (BWX) input, will

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active, and

1

) are asserted active to conduct a Write to the desired

X

-triggered Write accesses require a single clock

LOW at clock rise will automati-

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

and BW

) must be

.

, BWE,

input is ignored

.

X

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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A1: A0

Second

Address

A1: A0

DD

)

Third

Address

A1: A0

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Fourth

Address

A1: A0

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter Description T est Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-St a te
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Sleep mode standby current ZZ > VDD – 0.2V 100 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit sleep current This parameter is sampled 0 ns

[2, 3, 4, 5, 6, 7]

ns
ns
ns

Notes:

2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

3. WRITE

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. CE

6. The SRAM always initiates a read cycle when ADSP

7. OE

= L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.

, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

1

after the ADSP
don't care for the remainder of the write cycle.

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a re ad cycle all dat a bit s a re Tri-State when OE is

inactive or when the device is deselected, and all data bits behave as output when OE

or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

is active (LOW).

Document #: 38-05383 Rev. *E Page 9 of 31

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CY7C1442AV33
CY7C1446AV33

Truth Table (continued)

[2, 3, 4, 5, 6, 7]

Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

Truth Table for Read/Write

Function (CY7C1440AV33) GW BWE BW

[4,8,9]

D

BW

C

BW

B

BW

A

Read HHXXXX
Read HLHHHH
Write Byte A – (DQ
Write Byte B – (DQ

and DQPA) HLHHHL

A

and DQPB)HLHHLH

B

Write Bytes B, A H L H H L L
Write Byte C – (DQ

and DQPC) HLHLHH

C

Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – (DQ

and DQPD) HL LHHH

D

Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX

Truth Table for Read/Write

Function (CY7C1442AV33) GW BWE BW

[4, 8, 9]

B

BW

A

Read H H X X
Read H L H H
Write Byte A – (DQ
Write Byte B – (DQ

and DQPA)HLHL

A

and DQPB)HLLH

B

Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X

Notes:

represents any byte write signal. To enable any byte write BWx, a Logic LOW signal should be applied at clock rise.Any number of bye writes can be enabled

8. BW

x

at the same time for any given write.

9. Table only lists a partial listing of the byte wr ite combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

X

Document #: 38-05383 Rev. *E Page 10 of 31

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