Cypress CY7C1443AV33, CY7C1441AV33, CY7C1447AV33 User Manual
36-Mbit (1M x 36/2M x 18/512K x 72)
Flow-Through SRAM
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Features
■ Supports 133-MHz bus operations
■ 1M x 36/2M x 18/512K x 72 common IO
■ 3.3V core power supply
■ 2.5V or 3.3V IO power supply
■ Fast clock-to-output times
❐ 6.5 ns (133-MHz version)
■ Provide high-performance 2-1-1-1 access rate
■ User-selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ CY7C1441AV33, CY7C1443AV33 available in
JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and
non-lead-free 165-ball FBGA package. CY7C1447AV33
available in Pb-free and non-lead-free 209-ball FBGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ “ZZ” Sleep Mode option
Selection Guide
Functional Description
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
3.3V, 1M x 36/2M x 18/512K x 72 Synchronous Flow-through
SRAMs, respectively designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133-MHz version). A 2-bi t on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
Chip Enable (CE
CE
), Burst Control inputs (ADSC, ADSP, and ADV), Write
3
Enables (BW
Asynchronous inputs include the Output Enable (OE
pin.
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 allows
either interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst sequence,
while a LOW selects a linear burst sequence. Burst accesses
can be initiated with the Processor Address Strobe (ADSP
cache Controller Address Strobe (ADSC
advancement is controlled by the Address Advancement (ADV
input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (A DSP
Strobe Controller (ADSC
addresses can be internally generated as controlled by the
Advance pin (ADV
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
operates from a +3.3V core power supply while all outputs may
operate with either a +2.5 or +3.3V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
), depth-expansion Chip Enables (CE2 and
1
, and BWE), and Global Write (GW).
x
) inputs. Address
) are active. Subsequent burst
).
[1]
are
) and the ZZ
) or the
) or Address
)
Description 133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 310 290 mA
Maximum CMOS Standby Current 120 120 mA
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05357 Rev. *G Revised May 09, 2008
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Logic Block Diagram – CY7C1441AV33 (1M x 36)
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
MEMORY
ARRAY
MODE
A
[1:0]
ZZ
DQ s
DQP
A
DQP
B
DQP
C
DQP
D
A0, A1, A
ADV
CLK
ADSP
ADSC
BW
D
BW
C
BW
B
BW
A
BWE
CE1
CE2
CE3
OE
GW
SLEEP
CONTROL
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
CE
1
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
OUTPUT
BUFFERS
INPUT
REGISTERS
MODE
CE
2
CE
3
GW
BWE
A
0,A1,A
BW
B
BW
A
DQB,DQP
B
WRITE REGISTER
DQ
A
,DQP
A
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
DQs
DQP
A
DQP
B
DQB,DQP
B
WRITE DRIVER
DQ
A
,DQP
A
WRITE DRIVER
SLEEP
CONTROL
ZZ
Logic Block Diagram – CY7C1443AV33 (2Mx 18)
Document #: 38-05357 Rev. *G Page 2 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Logic Block Diagram – CY7C1447AV33 (512K x 72)
BW
D
BW
C
BW
B
BW
A
BWE
GW
CE1
CE2
CE3
OE
ENABLE
REGISTER
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
A0, A1,A
A[1:0]
BW
F
BW
E
BW
H
BW
G
OUTPUT
BUFFERS
DQA, DQP
A
WRITE DRIVER
DQB, DQP
B
WRITE DRIVER
DQC, DQP
C
WRITE DRIVER
DQD, DQP
D
WRITE DRIVER
BYTE
“a”
WRITE DRIVER
DQE, DQP
E
WRITE DRIVER
DQF, DQP
F
WRITE DRIVER
DQG, DQP
G
WRITE DRIVER
DQH, DQP
H
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
SLEEP
CONTROL
ZZ
INPUT
REGISTERS
DQs
DQP
A
DQP
B
DQP
C
DQP
D
DQP
E
DQP
F
DQP
G
DQP
H
DQA, DQP
A
WRITE REGISTER
DQB, DQP
B
WRITE REGISTER
DQC, DQP
C
WRITE REGISTER
DQD, DQP
D
WRITE REGISTER
DQE, DQP
E
WRITE REGISTER
DQF, DQP
F
WRITE REGISTER
DQF, DQP
F
WRITE REGISTER
DQH, DQP
H
WRITE REGISTER
Document #: 38-05357 Rev. *G Page 3 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
AAA
A
A
1A0
NC/72M
A
V
SS
V
DD
A
AAAAA
A
A
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
A
A
CE
1CE2
BWD
BWC
BWB
BWA
CE3VDDV
SS
CLKGWBWEOEADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
MODE
CY7C1441AV33
(1Mx 36)
NC
AAA
A
A
1A0
NC/72M
A
V
SS
V
DD
A
AAAAA
A
A
A
NC
NC
V
DDQ
V
SSQ
NC
DQP
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
CE
1CE2
NCNCBWBBWA
CE3VDDV
SS
CLKGWBWEOEADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100999897969594939291908988878685848382
81
MODE
CY7C1443AV33
(2M x 18)
NC
A
A
Pin Configurations
Figure 1. 100-Pin TQFP Pinout
Document #: 38-05357 Rev. *G Page 4 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Configurations (continued)
165-ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1441AV33 (1M x 36)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
DQP
C
DQ
C
DQP
D
NC
DQ
D
CE
1
BW
B
CE
3
BW
C
BWE
A
CE
2
DQ
C
DQ
D
DQ
D
MODE
NC
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
A
NC/72M
V
DDQ
BW
D
BW
A
CLK
GW
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCK
V
SS
TDI
A
A
DQ
C
V
SS
DQ
C
V
SS
DQ
C
DQ
C
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
D
DQ
D
NC
NC
V
DDQ
V
SS
TMS
891011
A
ADV
AADSC
NC
OE ADSP
A
NC/576M
V
SS
V
DDQ
NC/1G DQP
B
V
DDQ
V
DD
DQ
B
DQ
B
DQ
B
NC
DQ
B
NC
DQ
A
DQ
A
V
DD
V
DDQ
V
DD
V
DDQ
DQ
B
V
DD
NC
V
DD
DQ
A
V
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DDQ
AA
V
SS
A
A
A
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQP
A
DQ
A
A
V
DDQ
A
CY7C1443AV33 (2M x 18)
A0
A
V
SS
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
NC
NC
DQP
B
NC
DQ
B
ACE
1
NC
CE
3
BW
B
BWE
A
CE
2
NC
DQ
B
DQ
B
MODE
NC
DQ
B
DQ
B
NC
NC
NC
A
NC/72M
V
DDQ
NC BW
A
CLK
GW
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCKA0
V
SS
TDI
A
A
DQ
B
V
SS
NC V
SS
DQ
B
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
B
NC
NC
NC
V
DDQ
V
SS
TMS
891011
A
ADV
AADSC
A
OE ADSP
A
NC/576M
V
SS
V
DDQ
NC/1G DQP
A
V
DDQ
V
DD
NC
DQ
A
DQ
A
NC
NC
NC
DQ
A
NC
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DD
NC
V
DD
NC
V
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
NC
V
DDQ
AA
V
SS
A
A
A
DQ
A
NC
NC
ZZ
DQ
A
NC
NC
DQ
A
A
V
DDQ
A
A
A
Document #: 38-05357 Rev. *G Page 5 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Configurations (continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
123456789 1110
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
G
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQP
G
DQ
H
DQ
H
DQ
H
DQ
H
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
H
DQ
H
DQ
H
DQ
H
DQP
H
DQ
D
DQ
D
DQ
D
DQ
D
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
F
DQ
F
DQ
F
DQ
F
NC
DQP
F
DQ
A
DQ
A
DQ
A
DQ
A
DQ
E
DQ
E
DQ
E
DQ
E
DQP
A
DQP
B
DQ
F
DQ
F
DQ
F
DQ
F
NC
DQ
A
DQ
A
DQ
A
DQ
A
DQP
E
DQ
E
DQ
E
DQ
E
DQ
E
A
ADSP
ADV
A
NC
NC
NC/72M
AA A
A
AA
AA
A
A1
A0
A
AA
AA
A
NC/144M
NC288M
NC/576M
GW
NC
NC
BWS
B
BWS
F
BWS
E
BWS
A
BWS
C
BWS
G
BWS
D
BWS
H
TMS
TDI TDO TCK
NC
NC MODE
NC
V
SS
V
SS
NC
CLK
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/1G
V
DD
NC
OE
CE
3
CE
1
CE
2
ADSC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
V
SS
NC
V
DDQ
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
209-ball FBGA (14 x 22 x 1.76 mm) Pinout
CY7C1447AV33 (512K × 72)
Document #: 38-05357 Rev. *G Page 6 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Definitions
Name IO Description
, A1, A Input-
A
0
, BW
BW
A
, BWF,
E
, BW
G
B
H
BWC, BWD,
BW
BW
GW Input-
CLK Input-
CE
1
CE
2
CE
3
OE Input-
ADV Input-
ADSP
ADSC
BWE
ZZ Input-
Synchronous
Input-
Synchronous
Synchronous
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Asynchronous
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Asynchronous
Address Inputs Used to Select One of the Address Locations. Sampled
at the rising edge of the CLK if ADSP
and
are sampled active. A
CE3
or ADSC is active LOW, and CE1, CE2,
feed the 2-bit counter.
[1:0]
Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte
writes to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW. When asserted LOW on the rising
edge of CLK, a global write is conducted (ALL bytes are written, regardless
of the values on BWX and BWE).
Clock Input. Used to capture all synchronous inputs to the device. Also used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
ignored if CE
loaded.
is HIGH. CE1 is sampled only when a new external address is
1
and CE3 to select/deselect the device. ADSP is
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used
in conjunction with CE
only when a new external address is loaded.
and CE3 to select/deselect the device. CE2 is sampled
1
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used
in conjunction with CE
assumed active throughout this document for BGA. CE
a new external address is loaded.
and CE2 to select/deselect the device. CE3 is
1
is sampled only when
3
Output Enable, Asynchronous Input, Active LOW. Controls the direction
of the IO pins. When LOW, the IO pins behave as outputs. When deasserted
HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during
the first clock of a read cycle when emerging from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK,
Active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A
When ADSP
is ignored when
and ADSC are both asserted, only ADSP is recognized. ASDP
CE
is deasserted HIGH
1
are also loaded into the burst counter.
[1:0]
Address Strobe from Controller, Sampled on the Rising Edge of CLK,
Active LOW. When asserted LOW, addresses presented to the device are
captured in the address registers. A
When ADSP
and ADSC are both asserted, only ADSP is recognized
are also loaded into the burst counter.
[1:0]
.
Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK.
This signal must be asserted LOW to conduct a byte write.
ZZ “sleep” Input, Active HIGH. When asserted HIGH places the device in
a non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin must be LOW or left floating. ZZ pin has an internal pull
down.
Document #: 38-05357 Rev. *G Page 7 of 31
[+] Feedback
CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Pin Definitions (continued)
Name IO Description
DQ
DQP
s
X
IO-
Synchronous
IO-
Synchronous
MODE Input-Static Selects Burst Order. When tied to GND selects linear burst sequence. When
V
V
V
V
DD
DDQ
SS
SSQ
Power Supply Power Supply Inputs to the Core of the Device.
IO Power Supply Power Supply for the IO Circuitry.
Ground Ground for the Core of the Device.
IO Ground Ground for the IO Circuitry.
TDO JTAG serial output
Synchronous
TDI JTAG serial
input
Synchronous
TMS JTAG serial
input
Synchronous
TCK JTAG-Clock Clock Input to the JT AG Ci rcuitry. If the JTAG feature is not being utilized,
NC - No Conn ect s. Not internally connected to the die. 72M, 144M and 288M are
NC/72M, NC/144M,
- No Connects. Not internally connected to the die. NC/72M, NC/144M,
NC/288M, NC/576M
NC/1G
Bidirectional Data IO lines . As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the addresses presented during
the previous clock rise of the read cycle. The direction of the pins is controlled
by OE
. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ
and DQPX are placed in a tri-state condition.The outputs are automati-
s
cally tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE
.
Bidirectional Data Parity IO Lines. Functionally, these signals are identical
to DQ
ingly.
tied to V
pin and should remain static during device operation. Mode Pin has an internal
During write sequences, DQPx is controlled by BW
s.
or left floating selects interleaved burst sequence. This is a strap
DD
correspond-
[A:H]
pull up.
Serial Data-Out to the JTAG Circuit. Delivers data on the negative edge of
TCK. If the JTAG feature is not being utilized, this pin should be left unconnected. This pin is not available on TQFP packages.
Serial Data-In to the JT AG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be left floating or connected
to V
through a pull up resistor. This pin is not available on TQFP packages.
DD
Serial Data-In to the JT AG Circuit. Sampled on the rising edge of TCK. If
the JTAG feature is not being utilized, this pin can be disconnected or
connected to V
. This pin is not available on TQFP packages.
DD
this pin must be connected to VSS. This pin is not available on TQFP
packages.
address expansion pins are not internally connected to the die.
NC/288M, NC/576M and NC/1G are address expansion pins are not internally
connected to the die.
Document #: 38-05357 Rev. *G Page 8 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
supports secondary cache in systems utilizing either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Processor Address Strobe (ADSP
Address Strobe (ADSC
burst sequence is controlled by the ADV
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BWx) inputs. A Global Write
Enable (GW
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
HIGH.
Single Read Accesses
A single read access is initiated when the following condition s
are satisfied at clock rise: (1) CE
active, and (2) ADSP
initiated by ADSC
this first cycle). The address presented to the address i nputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE
asserted LOW, the requested data is available at the data
outputs a maximum to t
CE
is HIGH.
1
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
and (2) ADSP
loaded into the address register and the burst inputs (GW
and BW
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. All IOs are tri-stated during a byte write.Since
this is a common IO device, the asynchronous OE
must be deasserted and the IOs must be tri-stated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tri-stated once a write cycle is detected, regardless of
the state of OE
) is 6.5 ns (133-MHz device).
CDV
) or the Controller
). Address advancement through the
input. A two-bit on-chip
) overrides all byte write inputs and writes data to all
, CE2, CE3) and an
1
) provide for easy bank
is ignored if CE1 is
, CE2, and CE3 are all asserted
or ADSC is asserted LOW (if the access is
, the write inputs must be deasserted during
CDV
is asserted LOW. The addresses presented are
)are ignored during this first clock cycle. If the write
X
.
1
input is
after clock rise. ADSP is ignored if
, CE2, CE3 are all asserted active,
1
, BWE,
input signal
Single Write Accesse s Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, (2) ADSC
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ
specified address location. Byte writes are allowed. All IOs are
tri-stated when a write is detected, even a byte write. Since this
is a common IO device, the asynchronous OE
be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
of OE
.
is asserted LOW, (3) ADSP is deasserted
, CE2, and CE3 are all asserted
1
, BWE, and BWX)
is ignored if ADSP is active LOW.
is written into the
S
input signal must
Burst Sequences
The CY7C1441AV33/CY7C1443AV33/CY7C1447AV33
provides an on-chip two-bit wraparound burst counter inside the
SRAM. The burst counter is fed by A
linear or interleaved burst order. The burst order is determined
by the state of the MODE in put. A LOW on MODE selects a linear
burst sequence. A HIGH on MODE selects an interleaved burst
order. Leaving MODE unconnected causes the device to default
to a interleaved burst sequence.
, and can follow either a
[1:0]
Interleaved Burst Address Table (MODE = Floating or VDD)
First
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE
CE
, ADSP, and ADSC must remain inactive for the duration of
3
after the ZZ input returns LOW.
t
ZZREC
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
, CE2,
1
Document #: 38-05357 Rev. *G Page 9 of 31
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CY7C1441AV33
CY7C1443AV33,CY7C1447AV33
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD – 0.2V 100 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled
2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Truth Table
tThe truth table for CY7C1441AV33/CY7C1443AV33/CY7C1447AV33 follows.
[2, 3, 4, 5, 6]
ns
ns
ns
Cycle Description
ADDRESS
Used
CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power down None H X X L X L X X X L-H Tri-State
Deselected Cycle, Power down None L L X L L X X X X L-H Tri-State
Deselected Cycle, Power down None L X H L L X X X X L-H Tri-State
Deselected Cycle, Power down None L L X L H L X X X L-H Tri-State
Deselected Cycle, Power down None X X X L H L X X X L-H Tri-State
Sleep Mode, Power down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H
Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H
Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H
Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE
4. The DQ pins are controlled by the current cycle and the OE
5. The SRAM always initiates a read cycle when ADSP
6. OE
= L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
the ADSP
for the remainder of the write cycle.
or when the device is deselected, and all data bits behave as output when OE
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
signal. OE is asynchronous and is not sampled with the clock.
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
is active (LOW).
Document #: 38-05357 Rev. *G Page 10 of 31
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