Cypress CY7C144, CY7C145 User Manual
CY7C145, CY7C144
8K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
R/W
L
CE
L
OE
L
A
12L
A
0L
A
0R
A
12R
R/W
R
CE
R
OE
R
CE
R
OE
R
CE
L
OE
L
R/W
L
R/W
R
I/O7L
I/O
0L
I/ O 7R
I/ O
0R
INTERRUPT
SEMAPHORE
ARB I T RAT IO N
CONTROL
I/ O
CONTROL
I/O
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
SE M
L
SE M
R
BUSY
L BUS Y
R
INT
L
INT
R
M/S
(7C145) I/O
8L
I/ O
8R
)
[1, 2]
[2]
[1, 2]
[2]
Logic Block Diagram
CY7C144 CY7C1458K x 8/9 Dual-Port Static RAM
with SEM, INT, BUSY
Features
■ True Dual-Ported memory cells that enable simultaneous
reads of the same memory location
■ 8K x 8 organization (CY7C144)
■ 8K x 9 organization (CY7C145)
■ 0.65-micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: I
■ Fully asynchronous operation
■ Automatic power down
■ TTL compatible
■ Master/Slave select pin enables bus width expansion to
16/18 bits or more
■ Busy arbitration scheme provided
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Available in 68-pin PLCC, 64-pin and 80-pin TQFP
■ Pb-free packages available
= 160 mA (max.)
CC
Functional Description
The CY7C144 and CY7C145 are high speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
are included on the CY7C144/5 to handle situations when
multiple processors access the same piece of data. Two ports
are provided permitting independent, asynchronous access
for reads and writes to any location in memory. The
CY7C144/5 can be used as a standalone 64/72-Kbit dual-port
static RAM or multiple devices can be combined in order to
function as a 16/18-bit or wider master/slave dual-port static
RAM. An M/S
wider memory applications without the need for separate
master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs,
communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE
read or write enable (R/W
and INT, are provided on each port. BUSY signals that
BUSY
the port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from
one port to the other to indicate that a shared resource is in
use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared
resource is in use. An automatic power down feature is
controlled independently on each port by a chip enable (CE
pin or SEM
pin is provided for implementing 16/18-bit or
), and output enable (OE). Two flags,
) permits
pin.
),
)
Notes
1. BUSY
is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06034 Rev. *D Revised December 10, 2008
(7 C 1 4 5
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CY7C145, CY7C144
Pin Configurations
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 3334353637383940414243
5 4 3 2 168 666564636261
A
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
A
2728 29 30
98 7 6
47
46
45
44
A
1R
A
2R
A
3R
A
4R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
25
26
6L
7LA8LA9L
A
A
10L
11L
V
CC
NC
NC
CE
L
SEM
L
R/WLOE
L
NC
I/O
I/O
1L
0L
A
A
6R
7RA8RA9R
A
10R
NC
NC
CE
R
SEM
R
R/W
R
OE
R
I/O
7R
GND
A
11R
A
5R
A
5L
NC
A
12L
A
12R
CY7C144/5
[3]
[4]
Notes
3. I/O
8R
on the CY7C145.
4. I/O
8L
on the CY7C145.
Figure 1. 68-Pin PLCC (Top View)
Figure 2. 64-Pin PLCC (Top View)
Document #: 38-06034 Rev. *D Page 2 of 21
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CY7C145, CY7C144
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
16
18
19
20
2122232425262728293031323334353736
383940
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
45
43
42
41
8079787776757473727170696867666465
636261
2L
3L
4L
5L
6L
7L
V
CC
0R
1R
2R
3R
4R
5R
CC
V
CC
OE
L
I/O0LI/O
8L
A
5L
A
12LA11LA10LA9LA8LA7LA6L
CELSEMLR/W
L
A
4L
A
3L
A
2L
A
1L
A
0L
GND
BUSY
L
M/S
A
0R
A
1R
A
2R
A
3R
A
4R
INT
L
GND
OE
R
6R
A
12RA11RA10R
A9RA8RA7RA
6R
NC
CE
R
SEM
R
R/W
R
CY7C145
BUSY
R
INT
R
I/O
8R
NCNCNC
NC
NC
NCNCNC
NC
NC
NC
NC
NC
A
5R
I/O
7R
NC
O
NC
I/O
1L
Figure 3. 80-Pin TQFP
Table 1. Pin Definitions
Left Port Right Port Description
I/O
0L−7L(8L)
A
0L−12L
CE
L
OE
L
R/W
L
SEM
INT
L
BUSY
M/S
V
CC
GND Ground
Table 2. Selection Guide
Maximum Access Time 15 25 35 55 ns
Maximum Operating Current 220 180 160 160 mA
Maximum Standby Current for I
Document #: 38-06034 Rev. *D Page 3 of 21
I/O
A
CE
OE
R/W
SEM
L
INT
BUSY
L
Description
0R−7R(8R)
0R−12R
R
R
R
R
R
Data bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least significant bits of the address lines will determine which semaphore to write or read. The I/O
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
Interrupt Flag. INTL is set when right port writes location 1FFE and is cleared when left port reads
location 1FFE. INT
location 1FFF.
Busy Flag
R
Master or Slave Select
Power
SB1
is set when left port writes location 1FFF and is cleared when right port reads
R
7C144-15
7C145-15
60 40 30 30 mA
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
pin is used
0
Unit
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CY7C145, CY7C144
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage
[6]
..............................................−0.5V to +7.0V
[5]
Electrical Characteristics Over the Operating Range
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial −40°C to +85°C 5V ± 10%
Ambient
Tem per atur e V
CC
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
SB3
SB4
Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current Outputs Disabled, GND < VO < V
Operating Current VCC = Max., I
Outputs Disabled
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
CEL and CER > VIH,
f = f
CEL or CER > VIH,
f = f
MAX
MAX
[7]
[7]
Both Ports
and CER > VCC – 0.2V,
CE
V
> VCC – 0.2V
IN
or V
< 0.2V, f = 0
IN
One Port
or CER > VCC – 0.2V,
CE
L
V
> VCC – 0.2V or
IN
V
< 0.2V, Active
IN
Port Outputs, f = f
OUT
= 0 mA
[7]
[7]
MAX
7C144-15
7C145-15
7C144-25
7C145-25
Unit
Min Max Min Max
−10 +10 −10 +10 μA
CC
−10 +10 −10 +10 μA
Commercial 220 180 mA
Industrial 190
Commercial 60 40 mA
Industrial 50
Commercial 130 110 mA
Industrial 120
Commercial 15 15 mA
Industrial 30
Commercial 125 100 mA
Industrial 115
Notes
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby
7. f
MAX
I
.
SB3
Document #: 38-06034 Rev. *D Page 4 of 21
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CY7C145, CY7C144
Electrical Characteristics Over the Operating Range (continued)
Note:
8. Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
SB3
SB4
Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current Outputs Disabled, GND < VO < V
Operating Current VCC = Max., I
Outputs Disabled
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
CEL and CER > VIH,
f = f
CEL or CER > VIH,
f = f
MAX
MAX
[7]
[7]
Both Ports
and CER > VCC – 0.2V,
CE
V
> VCC – 0.2V
IN
or V
< 0.2V, f = 0
IN
One Port
CE
or CER > VCC – 0.2V,
L
> VCC – 0.2V or
V
IN
V
< 0.2V, Active
IN
Port Outputs, f = f
OUT
= 0 mA
[7]
[7]
MAX
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Min Max Min Max
−10 +10 −10 +10 μA
CC
−10 +10 −10 +10 μA
Commercial 160 160 mA
Industrial 180 180
Commercial 30 30 mA
Industrial 40 40
Commercial 100 100 mA
Industrial 110 110
Commercial 15 15 mA
Industrial 30 30
Commercial 90 90 mA
Industrial 100 100
Capacitance
Parameter
C
IN
C
OUT
Document #: 38-06034 Rev. *D Page 5 of 21
[8]
Description Test Conditions Max. Unit
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
Output Capacitance 15 pF
CC
10 pF
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CY7C145, CY7C144
Figure 4. AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
≤ 3ns
≤ 3 ns
10%
ALL INPUT PULSES
(a) Normal Load (Load1)
5V
OUTPUT
C= 30
pF
V
TH
= 1.4V
OUTPUT
C = 30pF
(b) Th évenin Equivalent (Load 1)
(c) Three-State Delay (Load 3)
C= 30pF
OUTPUT
Load (Load 2)
5V
OUTPUT
C= 5pF
R1 = 893Ω
R2 = 347Ω
R
TH
= 250Ω
R1 = 893Ω
R = 347Ω
Switching Characteristics Over the Operating Range
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
[12]
t
PU
[12]
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI/IOH
10. At any given temperature and voltage condition for any given device, t
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
Document #: 38-06034 Rev. *D Page 6 of 21
Read Cycle Time 15 25 35 55 ns
Address to Data Valid 15 25 35 55 ns
Output Hold From Address
Change
CE LOW to Data Valid 15 25 35 55 ns
OE LOW to Data Valid 10 15 20 25 ns
[10, 11,12]
[10, 11,12]
[10, 11,12]
[10, 11,12]
OE Low to Low Z 3 3 3 3 ns
OE HIGH to High Z 10 15 20 25 ns
CE LOW to Low Z 3 3 3 3 ns
CE HIGH to High Z 10 15 20 25 ns
CE LOW to Power-Up 0 0 0 0 ns
CE HIGH to Power-Down 15 25 35 55 ns
Write Cycle Time 15 25 35 55 ns
CE LOW to Write End 12 20 30 45 ns
Address Set-Up to Write End 12 20 30 45 ns
Address Hold From Write End 2 2 2 2 ns
Address Set-Up to Write Start 0 0 0 0 ns
Write Pulse Width 12 20 25 40 ns
and 30-pF load capacitance.
7C144-15
7C145-15
Min Max Min Max Min Max Min Max
3333ns
HZCE
[9]
7C144-25
7C145-25
is less than t
LZCE
7C144-35
7C145-35
and t
is less than t
HZOE
LZOE
.
7C144-55
7C145-55
Unit
[+] Feedback
CY7C145, CY7C144
Switching Characteristics Over the Operating Range
7C144-15
Parameter Description
t
SD
t
HD
[11,12]
t
HZWE
[11,12]
t
LZWE
[13]
t
WDD
[13]
t
DDD
BUSY TIMING
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
INTERRUPT TIMING
t
INS
t
INR
Data Set-Up to Write End 10 15 15 25 ns
Data Hold From Write End 0 0 0 0 ns
R/W LOW to High Z 10 15 20 25 ns
R/W HIGH to Low Z 3 3 3 3 ns
Write Pulse to Data Delay 30 50 60 70 ns
Write Data Valid to Read Data
Valid
[14]
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW 15202030ns
BUSY HIGH from CE HIGH 15 20 20 30 ns
Port Set-Up for Priority 5 5 5 5 ns
R/W LOW after BUSY LOW 0 0 0 0 ns
R/W HIGH after BUSY HIGH 13 20 30 30 ns
BUSY HIGH to Data Valid 15 25 35 55 ns
[14]
INT Set Time 15 25 25 35 ns
INT Reset Time 15 25 25 35 ns
SEMAPHORE TIMING
t
SOP
t
SWRD
t
SPS
SEM Flag Update Pulse (OE
or SEM
)
SEM Flag Write to Read Time 5 5 5 5 ns
SEM Flag Contention
Window
7C145-15
Min Max Min Max Min Max Min Max
25 30 35 40 ns
15 20 20 30 ns
15 20 20 30 ns
10 10 15 20 ns
5555ns
[9]
(continued)
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Notes
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
Document #: 38-06034 Rev. *D Page 7 of 21
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