Cypress CY7C1427AV18, CY7C1420AV18, CY7C1416AV18, CY7C1418AV18 User Manual

36-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Features

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600MHz) at 300 MHz for DDR-II

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

)

Configurations

CY7C1416AV18 – 4M x 8 CY7C1427AV18 – 4M x 9 CY7C1418AV18 – 2M x 18 CY7C1420AV18 – 1M x 36

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K driven on the rising edges of C and C edge of K and K is associated with two 8-bit words in the case of CY7C1416AV18 and two 9-bit words in the case of CY7C1427AV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1416AV18 and CY7C1427AV18. On CY7C1418AV18 and CY7C1420AV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1418AV18 and two 36-bit words in the case of CY7C1420AV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

if C/C are not provided. Each address location

, eliminating the need for separately

input clocks. All data outputs pass through output

if provided, or on the rising

(or K or K in a single clock

. Read data is

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz Maximum Operating Current x8 845 795 725 600 500 mA

x9 850 800 725 600 500 x18 900 835 760 620 525 x36 990 910 825 675 570

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05616 Rev. *F Revised January 29, 2009

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Logic Block Diagram (CY7C1416AV18)

Write Reg

CLK

(20:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

NWS

[1:0]

REF

Write Add. Decode

Control

R/W

DOFF

2M x 8 Array

[7:0]

CQ CQ

Write Reg

CLK

(20:0)

Gen.

Control

Logic

Address Register

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[0]

REF

Write Add. Decode

Control

R/W

DOFF

2M x 9 Array

[8:0]

CQ CQ

Logic Block Diagram (CY7C1427AV18)

Document Number: 38-05616 Rev. *F Page 2 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Logic Block Diagram (CY7C1418AV18)

Write Reg

CLK

(20:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[1:0]

REF

Write Add. Decode

Control

Burst Logic

(20:1)

R/W

DOFF

1M x 18 Array

[17:0]

CQ CQ

Write Reg

CLK

(19:0)

Gen.

Control

Logic

Address

Read Add. Decode

Read Data Reg.

R/W

Output

Logic

Reg.

BWS

[3:0]

REF

Write Add. Decode

Control

Burst Logic

(19:1)

R/W

DOFF

512K x 36 Array

[35:0]

CQ CQ

Logic Block Diagram (CY7C1420AV18)

Document Number: 38-05616 Rev. *F Page 3 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Pin Configuration

Note

1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1416AV18 (4M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NWS

B NC NC NC A NC/288M K NWS C NC NC NC V D NC NC NC V E NC NC DQ4 V F NC NC NC V G NC NC DQ5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC DQ6 NC V M NC NC NC V N NC NC NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC NC

P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A C AAATMSTDI

K NC/144M LD AACQ

ANCNCDQ3

DDQ

[1]

NC NC NC NC NC DQ2 NC NC NC NC NC NC

DDQ

REF

NC DQ1 NC NC NC NC NC NC DQ0 NC NC NC

CY7C1427AV18 (4M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NC K NC/144M LD AACQ B NC NC NC A NC/288M K BWS C NC NC NC V D NC NC NC V E NC NC DQ4 V F NC NC NC V G NC NC DQ5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC DQ6 NC V M NC NC NC V N NC NC NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC NC

ANCNCDQ3

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC NC NC NC DQ2 NC NC NC NC NC NC

DDQ

REF

NC DQ1 NC NC NC NC NC NC DQ0 NC NC NC

P NC NC DQ7 A A C A A NC NC DQ8 R TDO TCK A A A C AAATMSTDI

Document Number: 38-05616 Rev. *F Page 4 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Pin Configuration (continued)

The pin configuration for CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1418AV18 (2M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W BWS

B NC DQ9 NC A NC/288M K BWS C NC NC NC V D NC NC DQ10 V E NC NC DQ11 V F NC DQ12 NC V G NC NC DQ13 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC DQ14 V L NC DQ15 NC V M NC NC NC V N NC NC DQ16 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AA0AVSSNC DQ7 NC

AAAVSSNC NC NC

P NC NC DQ17 A A C A A NC NC DQ0 R TDO TCK A A A C AAATMSTDI

K NC/144M LD AACQ

ANCNCDQ8

DDQ

[1]

NC NC NC NC NC DQ6 NC NC DQ5 NC NC NC

DDQ

REF

NC DQ4 NC NC NC DQ3 NC NC DQ2 NC DQ1 NC

CY7C1420AV18 (1M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A R/W BWS B NC DQ27 DQ18 A BWS C NC NC DQ28 V D NC DQ29 DQ19 V E NC NC DQ20 V F NC DQ30 DQ21 V G NC DQ31 DQ22 V H DOFF V

REF

DDQ

J NC NC DQ32 V K NC NC DQ23 V L NC DQ33 DQ24 V M NC NC DQ34 V N NC DQ35 DQ25 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AA0AVSSNC DQ17 DQ7

AAAVSSNC NC DQ10

2 3

K BWS

LD A NC/72M CQ

KBWS0ANCNCDQ8

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC DQ16 NC DQ15 DQ6 NC NC DQ5 NC NC DQ14

DDQ

REF

ZQ NC DQ13 DQ4 NC DQ12 DQ3 NC NC DQ2 NC DQ11 DQ1

P NC NC DQ26 A A C A A NC DQ9 DQ0 R TDO TCK A A A C AAATMSTDI

Document Number: 38-05616 Rev. *F Page 5 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Pin Definitions

Pin Name IO Pin Description

[x:0]

Input OutputSynchronous

LD Input-

Synchronous

NWS NWS

0 1

Input-

Synchronous

Data Input Output Signals. Inputs are sampled on the rising edge of K and K operations. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode. When read access is deselected, Q CY7C1416AV18 − DQ CY7C1427AV18 − DQ CY7C1418AV18 − DQ CY7C1420AV18 − DQ

[7:0] [8:0] [17:0] [35:0]

are automatically tri-stated.

[x:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD the setup and hold times around edge of K.

Nibble Write Select 0, 1 − Active LOW (CY7C1416AV18 only). Sampled on the rising edge of the K

clocks during write operations. Used to select which nibble is written into the device during the

and K current portion of the write operations. Nibbles not written remain unaltered. NWS

controls D

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

and NWS1 controls D

[3:0]

[7:4]

ignores the corresponding nibble of data and it is not written into the device.

BWS BWS BWS BWS

2 3

Input-

Synchronous

Byte Write Select 0, 1, 2, and 3 − Active LOW . Sampled on the rising edge of the K and K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1427AV18 − BWS CY7C1418AV18 − BWS0 controls D CY7C1420AV18 − BWS0 controls D

[35:27]

All the Byte Write Selects are sampled on the same edge as the data.

controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9].

, BWS2 controls D

[17:9]

Deselecting a Byte Write Select

ignores the corresponding byte of data and it is not written into the device

A, A0 Input-

Synchronous

Address Inputs. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1416AV18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1427AV18, 2Mx 18 (2 arrays each of 1M x 18) for CY7C1418AV18, and 1M x 36 (2 arrays each of 512K x 36) for CY7C1420AV18. CY7C1416AV18 – Since the least significant bit of the address internally is a “0,” only 21 external address inputs are needed to access the entire memory array. CY7C1427AV18 – Since the least significant bit of the address internally is a “0,” only 21 external address inputs are needed to access the entire memory array. CY7C1418AV18 – A0 is the input to the burst counter . These are incremented in a linear fashion internally. 21 address inputs are needed to access the entire memory array. CY7C1420AV18 – A0 is the input to the burst counter . These are incremented in a linear fashion internally. 20 address inputs are needed to access the entire memory array. All the address inputs are ignored when the appropriate port is deselected.

R/W

Input-

Synchronous

Synchronous Read or Write In put. When LD is LOW , this input designates the access type (read when R/W

is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

the device. Use the C and C

together to deskew the flight times of various devices on the board back to

the controller. See Application Example on page 9 for further details.

Input Clock

Negative

the device. Use the C and C

Input Clock for Output Data. C is used in conjunction with C to clock out the read data from

together to deskew the flight times of various devices on the board back to

the controller. See Application Example on page 9 for further details.

K Input Clock Positive Input Clock In put. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q edge of K.

Input Clock Negative Input Clock Input. K is used to capture synchronous data being presented to the device and

to drive out data through Q

[x:0]

when in single clock mode. All accesses are initiated on the rising

[x:0]

when in single clock mode.

clocks during valid write

must meet

and BWS3 controls

[26:18],

to clock out the read data from

Document Number: 38-05616 Rev. *F Page 6 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Pin Definitions (continued)

Pin Name IO Pin Description

CQ Output Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

ZQ Input Output Impedance Matching Inpu t. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Tie to any voltage level. NC/72M N/A Not Connected to the Die. Tie to any voltage level. NC/144M N/A Not Connected to the Die. Tie to any voltage level. NC/288M N/A Not Connected to the Die. Tie to any voltage level. V

REF

DDQ

Output Clock

Input DLL Turn Off − Active LOW . Connecting this pin to ground turns off the DLL inside the device. The timing

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 23.

Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C for the echo clocks is shown in the Switching Characteristics on page 23.

impedance. CQ, CQ between ZQ and ground. Alternatively, connect this pin directly to V impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the DLL turned off operation differs from those listed in this data sheet.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing

, and Q

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the minimum

DDQ

Document Number: 38-05616 Rev. *F Page 7 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Functional Overview

The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface.

Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K referenced to the rising edge of the output clocks (C/C when in single clock mode).

All synchronous data inputs (D

[x:0]

controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q

[x:0]

controlled by the rising edge of the output clocks (C/C or K/K when in single clock mode).

All synchronous control (R/W

, LD, BWS

input registers controlled by the rising edge of the input clock (K). CY7C1418AV18 is described in the following sections. The same

basic descriptions apply to CY7C1416AV18, CY7C1427AV18 and CY7C1420AV18.

Read Operations for DDR-II

The CY7C1418AV18 is organized internally as two arrays of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in th e read address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. Following the next K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q

using C as the output timing reference.

[17:0]

On the subsequent rising edge of C the next 18-bit data word from the address location generated by the burst counter is driven onto the Q

. The requested data is valid 0.45 ns from

[17:0]

the rising edge of the output clock (C or C , or K and K when in single clock mode, 200 MHz and 250 MHz device). To maintain the internal logic, each read access must be allowed to complete. Initiate read accesses on every rising edge of the positive input clock (K).

On deselecting the read access, the CY7C1418AV18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the output following the next rising edge of the positive output clock (C). This enables for a transition between the devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register and the least significant bit of the address is presented to the burst counter. The burst counter increments the address in a linear fashion. On the following K clock rise the data

) and all output timing is

or K/K

) pass through input registers

) pass through output registers

) inputs pass through

[0:X]

presented to D data register, provided BWS

is latched and stored into the 18-bit write

[17:0]

are both asserted active. On the

[1:0]

subsequent rising edge of the negative input clock (K) the information presented to D register , provided BWS

is also stored into the write data

[17:0]

are both asserted active. The 36 bits

[1:0]

of data are then written into the memory array at the specified location. Initiate write accesses on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data transfers into the device on every rising edge of the input clocks (K and K

When write access is deselected, the device ignores all inputs after the pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C1418AV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS

and

BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. Use this feature to simplify read, modify, or write operations to a byte write operation.

Single Clock Mode

Use the CY7C1418AV18 with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K

and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C

HIGH at power on. This function is a strap option and not alterable during device operation.

DDR Operation

The CY7C1418AV18 enables high performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. The CY7C1418AV18 requires a single No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications may require a second NOP cycle to avoid contention.

If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write.

If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.

Document Number: 38-05616 Rev. *F Page 8 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Depth Expansion

Vterm = 0.75V

R = 50ohms

R = 250ohms

LD# C C#R/W#

DQ A

LD# C C#R/W#

DQ A

SRAM#1

SRAM#2

R = 250ohms

BUS

MASTER

(CPU

ASIC)

Addresses

Cycle Start#

R/W# Return CLK Source CLK

Return CLK#

Source CLK# Echo Clock1/Echo Clock#1 Echo Clock2/Echo Clock#2

CQ/CQ#

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be commo n between banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ± 15% is between 175Ω and 350Ω

, with V

=1.5V. The

DDQ

output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the

Application Example

Figure 1 shows two DDR-II used in an application.

Figure 1. Application Example

DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K, and CQ

is generated with respect to K. The timings for the echo clocks is shown in the AC Timing Table.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF refer to the application note AN5062, DLL Considerations in

QDRII/DDRII/QDRII+/DDRII+.

is tied HIGH, the

pin. For information

Document Number: 38-05616 Rev. *F Page 9 of 31

[+] Feedback

CY7C1416AV18, CY7C1427AV18 CY7C1418AV18, CY7C1420AV18

Truth Table

Notes

2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑

represents rising edge.

3. Device powers up deselected with the outputs in a tri-state condition.

4. On CY7C1418AV18 and CY7C1420AV18, “A1” represents address location latched by the devices when transaction was init iated and “A2” represents the addresses sequence in the burst. On CY7C1416AV18 and CY7C1427AV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.

5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging

symmetrically.

8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS

, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on

different portions of a write cycle, as long as the setup and hold requirements are achieved.

The truth table for the CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 follows.

Operation K LD R/W DQ DQ

Write Cycle:

L-H L L D(A1) at K(t + 1) ↑ D(A2) at K Load address; wait one cycle; input write data on consecutive K and K

Read Cycle:

rising edges.

L-H L H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑ Load address; wait one and a half cycle; read data on consecutive C and C rising edges.

NOP: No Operation L-H H X High-Z High-Z Standby: Clock Stopped Stopped X X Previous State Previous State

[2, 3, 4, 5, 6, 7]

(t + 1) ↑

Burst Address Table

(CY7C1418AV18, CY7C1420AV18)

First Address (External) Second Address (Internal)

X..X0 X..X1 X..X1 X..X0

Write Cycle Descriptions

The write cycle description table for CY7C1416AV18 and CY7C1418AV18 follows.

BWS0/

NWS

BWS1/

NWS

L L L–H – During the data portion of a write sequence:

CY7C1416AV18 − both nibbles (D CY7C1418AV18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L L – L-H During the data portion of a write sequence:

CY7C1416AV18 − both nibbles (D CY7C1418AV18 − both bytes (D

) are written into the device.

[7:0]

) are written into the device.

[17:0]

L H L–H – During the data portion of a write sequence:

CY7C1416AV18 − only the lower nibble (D CY7C1418AV18 − only the lower byte (D

[3:0]

[8:0]

L H – L–H During the data portion of a write sequence:

CY7C1416AV18 − only the lower nibble (D CY7C1418AV18 − only the lower byte (D

[3:0]

[8:0]

H L L–H – During the data portion of a write sequence:

CY7C1416AV18 − only the upper nibble (D CY7C1418AV18 − only the upper byte (D

[7:4]

[17:9]

H L – L–H During the data portion of a write sequence:

CY7C1416AV18 − only the upper nibble (D CY7C1418AV18 − only the upper byte (D

[7:4]

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation.

[2, 8]

Comments

) is written into the device, D

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[7:4]

remains unaltered.

[17:9]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

remains unaltered.

[3:0]

remains unaltered.

[8:0]

Document Number: 38-05616 Rev. *F Page 10 of 31

[+] Feedback

+ 21 hidden pages

Cypress CY7C1427AV18, CY7C1420AV18, CY7C1416AV18, CY7C1418AV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Configurations

Selection Guide

Logic Block Diagram (CY7C1416AV18)

Logic Block Diagram (CY7C1427AV18)

Logic Block Diagram (CY7C1418AV18)

Logic Block Diagram (CY7C1420AV18)

Pin Configuration

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

Pin Definitions

Functional Overview

Read Operations for DDR-II

Write Operations

Byte Write Operations

Single Clock Mode

DDR Operation

Depth Expansion

Programmable Impedance

Echo Clocks

Application Example

Truth Table

Write Cycle Descriptions