Cypress CY7C1422BV18, CY7C1423BV18, CY7C1429BV18, CY7C1424BV18 User Manual

36-Mbit DDR-II SIO SRAM 2-Word

Burst Architecture

CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Features

Functional Description

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when the DLL is

enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

)

Configurations

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with Double Data Rate Separate IO (DDR-II SIO) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K is driven on the rising edges of C and C if provided, or on the rising edge of K and K location is associated with two 8-bit words in the case of CY7C1422BV18, two 9-bit words in the case of CY7C1429BV18, two 18-bit words in the case of CY7C1423BV18, and two 36-bit words in the case of CY7C1424BV18 that burst sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the two output echo clocks CQ/CQ data separately from each individual DDR-II SIO SRAM in the system design. Output data clocks (C/C system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

if C/C are not provided. Each address

, eliminating the need to capture

) enable maximum

(or K or K in a single clock

. Read data

CY7C1422BV18 – 4M x 8 CY7C1429BV18 – 4M x 9 CY7C1423BV18 – 2M x 18 CY7C1424BV18 – 1M x 36

Selection Guide

Description 300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz Maximum Operating Current x8 825 775 700 600 500 mA

x9 845 775 700 600 500 x18 880 815 740 600 500 x36 980 890 800 665 560

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 001-07035 Rev. *D Revised June 16, 2008

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Logic Block Diagram (CY7C1422BV18)

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

[7:0]

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

2M x 8 Array

Write Data Reg

Control

Logic

2M x 9 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[8:0]

Read Add. Decode

Read Data Reg.

[8:0]

Reg.

BWS

[0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

2M x 9 Array

Write Data Reg

Control

Logic

Logic Block Diagram (CY7C1429BV18)

Document #: 001-07035 Rev. *D Page 2 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Logic Block Diagram (CY7C1423BV18)

1M x 18 Array

CLK

(19:0)

Gen.

Control

Logic

Address Register

[17:0]

Read Add. Decode

Read Data Reg.

[17:0]

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

1M x 18 Array

Write Data Reg

Control

Logic

512K x 36 Array

CLK

(18:0)

Gen.

Control

Logic

Address Register

[35:0]

Read Add. Decode

Read Data Reg.

[35:0]

Reg.

BWS

[3:0]

REF

Write Add. Decode

Write Data Reg

R/W

LD R/W

DOFF

512K x 36 Array

Write Data Reg

Control

Logic

Logic Block Diagram (CY7C1424BV18)

Document #: 001-07035 Rev. *D Page 3 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Configuration

Note

1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1422BV18 (4M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NWS

B NC NC NC A NC/288M K NWS C NC NC NC V D NC D4 NC V E NC NC Q4 V F NC NC NC V G NC D5 Q5 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q6 D6 V M NC NC NC V N NC D7 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC D3

AAAVSSNC NC NC

P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C AAATMSTDI

K NC/144M LD AACQ

ANCNCQ3

DDQ

[1]

NC NC NC NC D2 Q2 NC NC NC NC NC NC

DDQ

REF

NC Q1 D1 NC NC NC NC NC Q0 NC NC D0

CY7C1429BV18 (4M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A R/W NC K NC/144M LD AACQ B NC NC NC A NC/288M K BWS C NC NC NC V D NC D5 NC V E NC NC Q5 V F NC NC NC V G NC D6 Q6 V H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q7 D7 V M NC NC NC V N NC D8 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC D4

AAAVSSNC NC NC

ANCNCQ4

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC NC NC D3 Q3 NC NC NC NC NC NC

DDQ

REF

NC Q2 D2 NC NC NC NC NC Q1 NC NC D1

P NC NC Q8 A A C A A NC D0 Q0 R TDO TCK A A A C AAATMSTDI

Document #: 001-07035 Rev. *D Page 4 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Configuration (continued)

The pin configuration for CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1423BV18 (2M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A R/W BWS

B NC Q9 D9 A NC K BWS C NC NC D10 V D NC D11 Q10 V E NC NC Q11 V F NC Q12 D12 V G NC D13 Q13 V H DOFF V

REF

DDQ

J NC NC D14 V K NC NC Q14 V L NC Q15 D15 V M NC NC D16 V N NC D17 Q16 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC Q7 D8

AAAVSSNC NC D1

P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C AAATMSTDI

K NC/288M LD A NC/72M CQ

ANCNCQ8

DDQ

[1]

NC NC D7 NC D6 Q6 NC NC Q5 NC NC D5

DDQ

REF

NC Q4 D4 NC D3 Q3 NC NC Q2 NC Q1 D2

CY7C1424BV18 (1M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/288M NC/72M R/W BWS B Q27 Q18 D18 A BWS C D27 Q28 D19 V D D28 D20 Q19 V E Q29 D29 Q20 V F Q30 Q21 D21 V G D30 D22 Q22 V H DOFF V

REF

DDQ

J D31 Q31 D23 V K Q32 D32 Q23 V L Q33 Q24 D24 V M D33 Q34 D25 V N D34 D26 Q25 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSD16 Q7 D8

AAAVSSQ10 D9 D1

2 3

K BWS

LD A NC/144M CQ

KBWS0AD17Q17Q8

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

Q16 D15 D7 Q15 D6 Q6 D14 Q14 Q5 Q13 D13 D5

DDQ

REF

D12 Q4 D4 Q12 D3 Q3 D11 Q11 Q2 D10 Q1 D2

P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A C AAATMSTDI

Document #: 001-07035 Rev. *D Page 5 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Pin Definitions

Pin Name IO Pin Description

[x:0]

LD Input-

NWS0, NWS

BWS0, BWS

BWS2, BWS

A Input-

[x:0]

R/W Input-

C Input Clock Positive Input Clock for Output Data. C is used in conjunction with C

Input-

Synchronous

Input-

Synchronous

Outputs-

Synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1422BV18 - D CY7C1429BV18 - D CY7C1423BV18 - D CY7C1424BV18 - D

[7:0] [8:0] [17:0] [35:0]

Synchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus activity).

Nibble Write Select 0, 1 − Active LOW (CY7C1422BV18 Only). Sampled on the rising edge of the K and K

clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

and NWS1 controls D

[3:0]

[7:4]

ignores the corresponding nibble of data and it is not written into the device. Byte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1429BV18 − BWS CY7C1423BV18 − BWS CY7C1424BV18 − BWS D

[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

controls D

[8:0]

, BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9]

,BWS2 controls D

[17:9]

ignores the corresponding byte of data and it is not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1422BV18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1429BV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1423BV18 and 1M x 36 (2 arrays each of 512K x 36) for CY7C1424BV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1422BV18 and CY7C1429BV18, 20 address inputs for CY7C1423BV18 and 19 address inputs for CY7C1424BV18. These inputs are ignored when the appropriate port is deselected.

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clock mode. When the read port is deselected, Q CY7C1422BV18 − Q CY7C1429BV18 − Q CY7C1423BV18 − Q CY7C1424BV18 − Q

[7:0] [8:0] [17:0] [35:0]

clocks during read operations, or K and K when in single

are automatically tri-stated.

[x:0]

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read when R/W

is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times

around the edge of K.

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for further details.

and BWS3 controls

[26:18]

to clock out the read data from

Input Clock Negative Input Clock for Output data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for further details.

K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q edge of K.

Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q

[x:0]

when in single clock mode. All accesses are initiated on the rising

[x:0]

when in single clock mode.

Document #: 001-07035 Rev. *D Page 6 of 30

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Pin Definitions (continued)

Pin Name IO Pin Description

CQ Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is shown in the Switching Characteristics on page 23.

ZQ Input Output Impedance Matching Inpu t. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. V

REF

DDQ

Echo Clock CQ Referenced with Respect to C. This is a free-running clock and is synchronized to the input clock

Input DLL Turn Off − Active LOW . Connecting this pin to ground turns off the DLL inside the device. The timing

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C for the echo clocks is shown in the Switching Characteristics on page 23.

impedance. CQ, CQ, and Q between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR-I timing.

Reference Voltage In put . Static input used to set the reference level for HSTL inputs, Outputs, and AC measurement points.

) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timings

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document #: 001-07035 Rev. *D Page 7 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Functional Overview

The CY7C1422BV18, CY7C1429BV18, CY7C1423BV18, and CY7C1424BV18 are synchronous pipelined Burst SRAMs equipped with a DDR-II Seperate IO interface, which operates with a read latency of one and half cycles when DOFF HIGH. When DOFF

pin is set LOW or connected to VSS the device behaves in DDR-I mode with a read latency of one clock cycle.

Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K

) and all output timing is referenced to the rising edge of the output clocks (C/C when in single clock mode).

All synchronous data inputs (D controlled by the rising edge of the input clocks (K and K synchronous data outputs (Q controlled by the rising edge of the output clocks (C/C

) pass through input registers

[x:0]

) pass through output registers

[x:0]

when in single-clock mode). All synchronous control (R/W

input registers controlled by the rising edge of the input clock (K).

, LD, BWS

) inputs pass through

[0:X]

CY7C1423BV18 is described in the following sections. The same basic descriptions apply to CY7C1422BV18, CY7C1429BV18, and CY7C1424BV18.

Read Operations

The CY7C1423BV18 is organized internally as two arrays of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in th e read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q

using C as the output timing reference. On the subse-

[17:0]

quent rising edge of C, the next 18-bit data word is driven onto the Q edge of the output clock (C or C

. The requested data is valid 0.45 ns from the rising

[17:0]

, or K and K when in single clock mode, for 200 MHz and 250 MHz device). Read accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that data is transferred out of the device on every rising edge of the output clocks, C/C when in single clock mode).

The CY7C1423BV18 first completes the pending read transactions, when read access is deselected. Synchronous internal circuitry automatically tri-states the output following the next rising edge of the positive output clock (C).

Write Operations

Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise the data presented to D provided BWS rising edge of the negative input clock (K presented to D provided BWS

is latched and stored into the 18-bit write data register,

[17:0]

are both asserted active. On the subsequent

[1:0]

is also stored into the write data register,

[17:0]

are both asserted active. The 36 bits of data

[1:0]

) the information

pin is tied

, or K/K

). All

, or K/K

(or K/K

are then written into the memory array at the specified l ocation. Write accesses can be initiated on every rising edge of the positive input clock (K). This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When Write access is deselected, the device ignores all inputs after the pending write operations are completed.

Byte Write Operations

Byte write operations are supported by the CY7C1423BV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS

, which are sampled with each set of 18-bit data words.

Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read/modify/write operations to a byte write operation.

Single Clock Mode

The CY7C1423BV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K

and C/C clocks. All timing parameters remain the same

in this mode. T o use this mode of operation, tie C and C

HIGH at power on. This function is a strap option and not alterable during device operation.

DDR Operation

The CY7C1423BV18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation.

If a read occurs after a write cycle, address and data for the write are stored in registers. The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a posted write.

Depth Expansion

Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.

to enable the SRAM to adjust its output

, with V

=1.5V. The

DDQ

Document #: 001-07035 Rev. *D Page 8 of 30

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CY7C1422BV18, CY7C1429BV18 CY7C1423BV18, CY7C1424BV18

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C

. These are free-running clocks and are synchronized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ with respect to K

. The timing for the echo clocks is shown in

is generated

Switching Characteristics on page 23.

Application Example

Figure 1 shows four DDR-II SIO used in an application.

Figure 1. Application Example

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K minimum of 30 ns. However, it is not necessary to reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note AN5062, DLL Considerations in

QDRII/DDRII/QDRII+/DDRII+.

for a

BUS

MASTER

(CPU

ASIC)

DATA IN

DATA OUT

Address

LD#

R/W#

BWS#

SRAM 1 Input CQ

SRAM 1 Input CQ#

SRAM 4 Input CQ

SRAM 4 Input CQ#

Source K

Source K#

Delayed K

Delayed K#

SRAM 1

R=50

Ohms

LD#R/W

R/W

Vt = V

S W

REF

CC#

CQ#

R = 250Ohms

LD#R/W

SRAM 4

CC#K

CQ#

R = 250Ohms

Document #: 001-07035 Rev. *D Page 9 of 30

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Cypress CY7C1422BV18, CY7C1423BV18, CY7C1429BV18, CY7C1424BV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Configurations

Selection Guide

Logic Block Diagram (CY7C1422BV18)

Logic Block Diagram (CY7C1429BV18)

Logic Block Diagram (CY7C1423BV18)

Logic Block Diagram (CY7C1424BV18)

Pin Configuration

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

Pin Definitions

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Single Clock Mode

DDR Operation

Depth Expansion

Programmable Impedance

Echo Clocks

Application Example