Cypress CY7C1414AV18, CY7C1412AV18, CY7C1425AV18, CY7C1410AV18 User Manual

36-Mbit QDR™-II SRAM 2-Word

Burst Architecture

CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18

Features

Functional Description

■ Separate independent read and write data ports ❐ Supports concurrent transactions

■ 250 MHz clock for high bandwidth

■ 2-word burst on all accesses

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 500 MHz) at 250 MHz

■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for both read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

= 1.8V (±0.1V); IO V

= 1.4V to V

DDQ

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common IO devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K

clock. Accesses to the QDR-II read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 8-bit words (CY7C1410AV18), 9-bit words (CY7C1425AV18), 18-bit words (CY7C1412AV18), or 36-bit words (CY7C1414AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K

), memory bandwidth is maximized while simplifying

and C

system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with port selects, which

enables each port to operate independently. All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1410AV18 – 4M x 8 CY7C1425AV18 – 4M x 9 CY7C1412AV18 – 2M x 18 CY7C1414AV18 – 1M x 36

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz Maximum Operating Current x8 800 700 620 mA

x9 800 700 620 x18 850 725 650 x36 1000 850 740

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-05615 Rev. *E Revised June 13, 2008

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CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18

Logic Block Diagram (CY7C1410AV18)

2M x 8 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

NWS

[1:0]

REF

Write Add. Decode

Write

Reg

(20:0)

DOFF

[7:0]

Write

Reg

2M x 8 Array

2M x 9 Array

CLK

(20:0)

Gen.

Control

Logic

Address Register

[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[0]

REF

Write Add. Decode

Write

Reg

(20:0)

DOFF

[8:0]

Write

Reg

2M x 9 Array

Logic Block Diagram (CY7C1425AV18)

Document #: 38-05615 Rev. *E Page 2 of 29

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Logic Block Diagram (CY7C1412AV18)

1M x 18 Array

CLK

(19:0)

Gen.

Control

Logic

Address Register

[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[1:0]

REF

Write Add. Decode

Write

Reg

(19:0)

DOFF

[17:0]

Write

Reg

1M x 18 Array

512K x 36 Array

CLK

(18:0)

Gen.

Control

Logic

Address Register

[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address Register

Reg.

BWS

[3:0]

REF

Write Add. Decode

Write

Reg

(18:0)

DOFF

[35:0]

Write

Reg

512K x 36 Array

Logic Block Diagram (CY7C1414AV18)

Document #: 38-05615 Rev. *E Page 3 of 29

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CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18

Pin Configuration

Note

1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

The pin configuration for CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1410AV18 (4M x 8)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A WPS NWS

B NC NC NC A NC/288M K NWS C NC NC NC V D NC D4 NC V E NC NC Q4 V F NC NC NC V

G NC D5 Q5 V

H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q6 D6 V

M NC NC NC V

N NC D7 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC D3

AAAVSSNC NC NC

P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A C AAATMSTDI

K NC/144M RPS AACQ

ANCNCQ3

DDQ

[1]

NC NC NC NC D2 Q2 NC NC NC NC NC NC

DDQ

REF

NC Q1 D1 NC NC NC NC NC Q0 NC NC D0

CY7C1425AV18 (4M x 9)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/72M A WPS NC K NC/144M RPS AACQ B NC NC NC A NC/288M K BWS C NC NC NC V D NC D5 NC V E NC NC Q5 V F NC NC NC V

G NC D6 Q6 V

H DOFF V

REF

DDQ

J NC NC NC V K NC NC NC V L NC Q7 D7 V

M NC NC NC V

N NC D8 NC V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC NC D4

AAAVSSNC NC NC

ANCNCQ4

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

NC NC NC NC D3 Q3 NC NC NC NC NC NC

DDQ

REF

NC Q2 D2 NC NC NC NC NC Q1 NC NC D1

P NC NC Q8 A A C A A NC D0 Q0 R TDO TCK A A A C AAATMSTDI

Document #: 38-05615 Rev. *E Page 4 of 29

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CY7C1410AV18, CY7C1425AV18 CY7C1412AV18, CY7C1414AV18

Pin Configuration (continued)

The pin configuration for CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 follow.

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1412AV18 (2M x 18)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/144M A WPS BWS

B NC Q9 D9 A NC K BWS C NC NC D10 V D NC D11 Q10 V E NC NC Q11 V F NC Q12 D12 V

G NC D13 Q13 V

H DOFF V

REF

DDQ

J NC NC D14 V K NC NC Q14 V L NC Q15 D15 V

M NC NC D16 V

N NC D17 Q16 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSNC Q7 D8

AAAVSSNC NC D1

P NC NC Q17 A A C A A NC D0 Q0 R TDO TCK A A A C AAATMSTDI

K NC/288M RPS A NC/72M CQ

ANCNCQ8

DDQ

[1]

NC NC D7 NC D6 Q6 NC NC Q5 NC NC D5

DDQ

REF

NC Q4 D4 NC D3 Q3 NC NC Q2 NC Q1 D2

CY7C1414AV18 (1M x 36)

1 2 3 4 5 6 7 8 9 10 11

A CQ NC/288M NC/72M WPS BWS B Q27 Q18 D18 A BWS C D27 Q28 D19 V D D28 D20 Q19 V E Q29 D29 Q20 V F Q30 Q21 D21 V

G D30 D22 Q22 V

H DOFF V

REF

DDQ

J D31 Q31 D23 V K Q32 D32 Q23 V L Q33 Q24 D24 V

M D33 Q34 D25 V

N D34 D26 Q25 V

SS DDQ DDQ DDQ DDQ DDQ DDQ DDQ

AAAVSSD16 Q7 D8

AAAVSSQ10 D9 D1

2 3

K BWS

RPS A NC/144M CQ

KBWS0AD17Q17Q8

V V V V V V V

DDQ DDQ DDQ DDQ DDQ DDQ DDQ

Q16 D15 D7 Q15 D6 Q6 D14 Q14 Q5 Q13 D13 D5

DDQ

REF

D12 Q4 D4 Q12 D3 Q3 D11 Q11 Q2 D10 Q1 D2

P Q35 D35 Q26 A A C A A Q9 D0 Q0 R TDO TCK A A A C AAATMSTDI

Document #: 38-05615 Rev. *E Page 5 of 29

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Pin Definitions

Pin Name IO Pin Description

[x:0]

WPS Input-

NWS

BWS0, BWS

BWS2, BWS

A Input-

[x:0]

RPS Input-

C Input Clock Positive Input Clock for Output data. C is used in conjunction with C

Input-

Synchronous

Input-

Synchronous

Outputs-

Synchronous

Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. CY7C1410AV18 - D CY7C1425AV18 - D CY7C1412AV18 - D CY7C1414AV18 - D

[7:0] [8:0] [17:0] [35:0]

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D

Nibble Write Select 0, 1 − Active LOW (CY7C1410AV18 Only). Sampled on the rising edge of the K and K

clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations.Nibbles not written remain unaltered. NWS NWS

controls D

All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

[7:4]

ignores the corresponding nibble of data and it is not written into the device. Byte Write Select 0, 1, 2, and 3 − Active LOW . Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1425AV18 − BWS CY7C1412AV18 − BWS CY7C1414AV18 − BWS D

[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

controls D

[8:0]

, BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

[17:9]

,BWS2 controls D

[17:9]

ignores the corresponding byte of data and it is not written into the device. Address Inputs. Sampled on the rising edge of the K (Read address) and K

active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1410AV18, 4M x 9 (2 arrays each of 2M x 9) for CY7C1425AV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1412AV18 and 1M x 36 (2 arrays each of 512K x 36) for CY7C1414AV18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1410AV18 and CY7C1425AV18, 20 address inputs for CY7C1412AV18 and 19 address inputs for CY7C1414AV18. These inputs are ignored when the appropriate port is deselected.

Data Output Signals. These pins drive out the requested data during a read operation. Valid data is driven out on the rising edge of both the C and C clock mode. When the read port is deselected, Q CY7C1410AV18 − Q CY7C1425AV18 − Q CY7C1412AV18 − Q CY7C1414AV18 − Q

[7:0] [8:0] [17:0] [35:0]

clocks during read operations, or K and K when in single

are automatically tri-stated.

[x:0]

Read Port Select − Active LOW . Sampled on the rising edge of positive input clock (K). When active, a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers.

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for further details.

[x:0]

controls D

and BWS3 controls

[26:18]

[3:0]

and

(Write address) clocks during

to clock out the read data from

Input Clock Negative Input Clock for Output data. C is used in conjunction with C to clock out the read data from

the device. C and C

can be used together to deskew the flight times of various devices on the board back

to the controller. See Application Example on page 9 for further details.

K Input Clock Positive Input Clock In put. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q edge of K.

Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and

to drive out data through Q

[x:0]

when in single clock mode. All accesses are initiated on the rising

[x:0]

when in single clock mode.

Document #: 38-05615 Rev. *E Page 6 of 29

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Pin Definitions (continued)

Pin Name IO Pin Description

CQ Echo Clock CQ Referenced with Respect to C. This is a free - running clock and is synchronized to the Input clock

for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks is shown in the Switching Characteristics on page 23.

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

DOFF

TDO Output TDO for JTAG. TCK Input TCK Pin for JTAG. TDI Input TDI Pin for JTAG. TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/72M N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. V

REF

DDQ

Echo Clock CQ Referenced with Respect to C. This is a free - running clock and is synchronized to the Input clock

Input DLL Turn Off − Active LOW . Connecting this pin to ground turns off the DLL inside the device. The timing

Input-

Reference

Power Supply Power Supply Inputs to the Core of the Device.

Ground Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

for output data (C for the echo clocks is shown in the Switching Characteristics on page 23.

impedance. CQ, CQ, and Q between ZQ and ground. Alternatively, this pin can be connected directly to V minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

in the DLL turned off operation differs from those listed in this data sheet.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points.

) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings

output impedance are set to 0.2 x RQ, where RQ is a resistor connected

[x:0]

, which enables the

DDQ

Document #: 38-05615 Rev. *E Page 7 of 29

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Functional Overview

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 8-bit data transfers in the case of CY7C1410AV18, two 9-bit data transfers in the case of CY7C1425AV18, two 18-bit data transfers in the case of CY7C1412AV18, and two 36-bit data transfers in the case of CY7C1414AV18 in one clock cycle.

Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K all output timing is referenced to the rising edge of the output clocks (C and C,

All synchronous data inputs (D

or K and K when in single clock mode).

) pass through input registers

[x:0]

controlled by the input clocks (K and K). All synchronous data outputs (Q

) pass through output registers controlled by the

[x:0]

rising edge of the output clocks (C and C, or K and K when in single clock mode).

All synchronous control (RPS

, WPS, BWS

) inputs pass

[x:0]

through input registers controlled by the rising edge of the input clocks (K and K

CY7C1412AV18 is described in the following sections. The same basic descriptions apply to CY7C1410AV18, CY7C1425AV18, and CY7C1414AV18.

Read Operations

The CY7C1412AV18 is organized internally as two arrays of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. The address presented to the address inputs is stored in the read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q data is valid 0.45 ns from the rising edge of the output clock (C

or K and K when in single clock mode).

and C Synchronous internal circuitry automatically tri-states the outputs

following the next rising edge of the output clocks (C/C allows for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

using C as the

[17:0]

. The requested

[17:0]

) and

). This

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input cl ock (K). On the same K clock rise, the data presented to D lower 18-bit write data register, provided BWS

is latched and stored into the

[17:0]

[1:0]

are both asserted active. On the subsequent rising edge of the negative input clock (K presented to D BWS

[1:0]

), the address is latched and the information

is stored into the write data register, provided

[17:0]

are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port ignores all inputs after completion of pending write operations.

Byte Write Operations

Byte write operations are supported by the CY7C1412AV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS

and

BWS1, which are sampled with each 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation.

Single Clock Mode

The CY7C1412AV18 can be used with a single clock that controls both the input and output registers. In this mode, the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between

and C/C clocks. All timing parameters remain the same

the K/K in this mode. To use this mode of operation, the user must tie C

HIGH at power on. This function is a strap option and not

and C alterable during device operation.

Concurrent Transactions

The read and write ports on the CY7C1412AV18 operate independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. The user can start reads and writes in the same clock cycle. If the ports access the same location at the same time, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise.

Depth Expansion

The CY7C1412AV18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed prior to the device being deselected.

Document #: 38-05615 Rev. *E Page 8 of 29

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Programmable Impedance

R = 250ohms

Vt = Vddq/2

R = 50ohms

CC#

D A

SRAM #2

R P S #

P S #

S #

CQ/CQ#

CC#

D A

SRAM #1

R P S #

P S #

S #

CQ/CQ#

BUS

MASTER

(CPU

ASIC)

DATA IN

DATA OUT

Address

RPS# WPS# BWS#

Source K

Source K#

Delayed K

Delayed K#

CLKIN/CLKIN#

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω

, with V

=1.5V. The

DDQ

output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ

is referenced

with respect to C. These are free-running clocks and are

Application Example

Figure 1 shows two QDR-II used in an application.

Figure 1. Application Example

synchronized to the output clock (C/C

) of the QDR-II. In single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in the Switching Characteristics on page 23.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the DLL to lock to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF refer to the application note AN5062, DLL Considerations in

QDRII/DDRII/QDRII+/DDRII+.

pin. For information

Document #: 38-05615 Rev. *E Page 9 of 29

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Cypress CY7C1414AV18, CY7C1412AV18, CY7C1425AV18, CY7C1410AV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Functional Description

Configurations

Selection Guide

Logic Block Diagram (CY7C1410AV18)

Logic Block Diagram (CY7C1425AV18)

Logic Block Diagram (CY7C1412AV18)

Logic Block Diagram (CY7C1414AV18)

Pin Configuration

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

Pin Definitions

Functional Overview

Read Operations

Write Operations

Byte Write Operations

Single Clock Mode

Concurrent Transactions

Depth Expansion

Programmable Impedance

Echo Clocks

Application Example