CYPRESS CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, CY7C1415AV18 User Manual

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

36-Mbit QDR™-II SRAM 4-Word Burst

Architecture

Features

• Separate Independent Read and Write data ports — Supports concurrent tra nsactions

• 300-MHz clock for high bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz

• Two input clocks (K and K) for precise DDR timing — SRAM uses rising edg es only

• Two input clocks for output dat a (C and C clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ high-speed systems

• Single multiplexed address input bus latches address inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency providing most current data

•Core V

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

= 1.8 (±0.1V); I/O V

) simplify data capture in

= 1.4V to V

DDQ

) to minimize

Configurations

CY7C1411AV18 – 4M x 8 CY7C1426AV18 – 4M x 9 CY7C1413AV18 – 2M x 18 CY7C1415AV18 – 1M x 36

Functional Description

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1411AV18) or 9-bit words (CY7C1426AV18) or 18-bit words (CY7C1413AV18) or 36-bit words (CY7C1415AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K

and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled

by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

(or K or K in a single clock

Selection Guide

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz Maximum Operating Current 925 875 800 700 600 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05614 Rev. *C Revised June 26, 2006

[+] Feedback [+] Feedback

Logic Block Diagram (CY7C1411A V18)

[7:0]

Address

(19:0)

Write

Reg

1M x 8 Array

Write

Reg

1M x 8 Array

Address Register

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

(19:0)

K K

CLK Gen.

DOFF

REF

WPS NWS

[1:0]

Control

Logic

Logic Block Diagram (CY7C1426AV18)

[8:0]

Address

(19:0)

K K

CLK

Gen.

DOFF

Write Add. Decode

Read Data Reg.

Write

Reg

1M x 9 Array

Write Add. Decode

Read Data Reg.

Write

Reg

1M x 9 Array

Control

Read Add. Decode

Logic

Reg.

Address Register

Control

Read Add. Decode

Logic

Reg.

RPS

[7:0]

(19:0)

RPS

REF

WPS BWS

Control

[0]

Logic

Reg.

[8:0]

Document Number: 38-05614 Rev. *C Page 2 of 28

[+] Feedback [+] Feedback

Logic Block Diagram (CY7C1413AV18)

[17:0]

Address

(18:0)

Write

Reg

512K x 18 Array

Write

Reg

512K x 18 Array

Address Register

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

(18:0)

K K

CLK Gen.

DOFF

REF

WPS BWS

[1:0]

Control

Logic

Logic Block Diagram (CY7C1415AV18)

[35:0]

Address

(17:0)

K K

CLK Gen.

DOFF

Write Add. Decode

Read Data Reg.

Write

Reg

256K x 36 Array

Write Add. Decode

Read Data Reg.

Write

Reg

256K x 36 Array

Write

Reg

256K x 36 Array

Control

Reg.

Logic

Reg.

Read Add. Decode

Reg.

Address Register

Control

Read Add. Decode

Logic

RPS

C C

RPS

C C

[17:0]

(17:0)

[35:0]

REF

WPS BWS

[3:0]

Control

Logic

144

Reg.

Document Number: 38-05614 Rev. *C Page 3 of 28

[+] Feedback [+] Feedback

Pin Configurations

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1411AV18 (4M x 8)

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

A B C D E F G H

K L M N P

A B

C D

E F G H

K L M N P

NC NC NC

NC V NC NC

DOFF

NC NC NC NC NC NC

TDO

NC/72M A

NC NC NC

D4 V NC NC

REF

NC NC Q6

D7 NC

TCK

NC NC V

Q4 NC Q5 V

DDQ

NC NC

NC NC Q7

A NC/288M K NWS

DDQ

DDQ DDQ

DDQ

NWS

ANCA

A A

KWPS

SS SS

A C

NC/144M

A A

RPS

A NC NC Q3

DDQ

DDQ DDQ

DDQ

A A

91011

NC NC D3

D2 NC NC

REF

Q1 NC NC NC NC NC

NC NC NC NC

DDQ

NC NC NC NC D0 NC NC

NC Q2

NC ZQ

D1V NC Q0

NC NC

TDITMS

CY7C1426AV18 (4M x 9)

CQ NC NC NC NC V NC NC

DOFF

NC NC NC NC NC NC

TDO

NC/72M A NC K

NC NC NC D5 V NC NC D6

REF

NC NC Q7

D8 NC

TCK

NC NC V

Q5 NC Q6 V

DDQ

NC NC D7 NC NC Q8

WPS NC/144M

A NC/288M K BWS

DDQ

DDQ DDQ

DDQ

ANCA

A A

SS SS

A C

A A

DDQ

DDQ DDQ

DDQ

A A

91011

AARPS

NC Q4

NC NC D4

D3 NC NC

REF

Q2 NC NC NC NC

NC NC NC NC

DDQ

NC NC NC NC D1 NC NC

NC ZQ

D2V

TDITMS

Document Number: 38-05614 Rev. *C Page 4 of 28

[+] Feedback [+] Feedback

Pin Configurations (continued)

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1413AV18 (2M x 18)

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

A B C

D E F G

K L M N P

A B C D E F G H

K L M N P

CQ NC

NC NC

NC V NC NC

DOFF

NC NC NC NC NC NC

TDO

NC/144M A

Q9 D9 NC

D11 V

NC Q12 D13

REF

NC Q15 NC D17

NC TCK

D10

Q10 V

Q11 D12

Q13 V

DDQ

D14

Q14

D15

D16 Q16 Q17

A NC K

DDQ

DDQ DDQ

DDQ

567

BWS

ANCA

V V V

V A A

KWPS

SS SS SS SS SS

SS SS SS SS

A C

NC/288M

BWS

A A

RPS

A NC NC Q8

DDQ

DDQ DDQ

DDQ

A A

91011

ANC/72M

NC Q7 D8 NC

NC NC Q5 NC

DDQ

NC NC NC NC D2 NC NC

D6 NC NC

REF

D3 NC Q1 NC

D7 Q6

D4V Q3 Q2

D1 Q0

TDITMS

CY7C1415AV18 (1M x 36)

Q27 D27 D28

Q29 V

Q30

D30

DOFF

D31 Q32 Q33 D33 D34 Q35

TDO

NC/288M NC/72M

Q18 Q28

D20 V D29

Q21

D22

REF

Q31

D32

Q24

Q34

D26 D35

TCK

D18 D19 Q19 V Q20 D21 Q22 V

DDQ

D23 Q23 D24 D25 Q25 Q26

456

WPS BWS

DDQ

DDQ DDQ

DDQ

BWS

ANCA

A A

K K

SS SS

A C

BWS

A A

1 0

891011

RPS

A D17

DDQ

DDQ DDQ

DDQ

A A

NC/144M

Q17 D16 Q7 D8 Q16 Q15 D14 Q5 Q13

DDQ

D12 Q12 D11 D10 D2 Q10

D15

D6 Q14 D13

D3 Q11

REF

D7 Q6

D4V Q3 Q2

D1 Q0

TDITMS

Document Number: 38-05614 Rev. *C Page 5 of 28

[+] Feedback [+] Feedback

Pin Definitions

Pin Name I/O Pin Description

[x:0]

WPS

NWS

BWS0, BWS1, BWS

, BWS

A Input-

[x:0]

RPS Input-

C Input-

K Input-

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Outputs-

Synchronous

Clock

Input-

Clock

Input-

Clock

Data input signals, sampled on the rising edge of K and K clocks during valid write operations.

CY7C1411AV18 − D CY7C1426AV18 − D CY7C1413AV18 − D CY7C1415AV18 − D

[7:0] [8:0] [17:0] [35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D

to be ignored.

[x:0]

Nibble Write Select 0, 1 − active LOW.(CY7C1411AV18 Only) Sampled on the rising edge of the K and K NWS All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble

clocks during Write operations. Used to select which nibble is written into the device

controls D

and NWS1 controls D

[3:0]

[7:4]

Write Select will cause the corresponding nibble of data to be ignored and not written into the device.

Byte Write Select 0, 1, 2, and 3 − active LOW . Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1426AV18 − BWS CY7C1413AV18 − BWS0 controls D CY7C1415AV18 − BWS0 controls D controls D All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

[35:27].

controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active Read and Write opera-

tions. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1411AV18, 4M x 9 (4 arrays each of 1M x 9) for CY7C1426AV18,2M x 18 (4 arrays each of 512K x 18) for CY7C1413AV18 and 1M x 36 (4 arrays each of 256K x 36) for CY7C1415AV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1411AV18 and CY7C1426AV18, 19 address inputs for CY7C1413AV18 and 18 address inputs for CY7C1415A V18. These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C

. when in single clock mode. When the Read port is deselected, Q

K tri-stated. CY7C1411AV18 − Q CY7C1426AV18 − Q CY7C1413AV18 − Q CY7C1415AV18 − Q

[7:0]

[8:0] [17:0] [35:0]

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of four sequential transfers.

Positive Input Clock for Output Data. C is used in conjunction with C data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

device and to drive out data through Q on the rising edge of K.

when in single clock mode. All accesses are initiated

[x:0]

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q

when in single clock mode.

[x:0]

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

[17:9].

, BWS2 controls D

[17:9]

clocks during Read operations or K and

are automatically

[x:0]

to clock out the Read

[26:18]

and BWS3

Document Number: 38-05614 Rev. *C Page 6 of 28

[+] Feedback [+] Feedback

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Pin Definitions (continued)

Pin Name I/O Pin Description

CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input

clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.

ZQ Input Output Impedance Matching Inpu t. This input is used to tune the device outputs to the system

DOFF Input DLL T urn Off - active LOW . Connecting this pin to ground will turn off the DLL inside the device.

TDO Output TDO for JTAG. TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/72M N/A Not connected to the die. Can be tied to any voltage level.

NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level.

REF

DDQ

Echo Clock

Input-

Reference

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

is referenced with respect to C. This is a free running clock and is synchronized to the Input

clock for output data (C to K

. The timings for the echo clocks are shown in the AC Timing table.

data bus impedance. CQ, CQ resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V

, which enables the minimum impedance mode. This pin cannot be conne cted directly to

DDQ

GND or left unconnected.

The timings in the DLL turned off operation will be different from those listed in this data sheet.

Reference Volt age Input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points.

) of the QDR-II. In the single clock mode, CQ is generated with respect

, and Q

output impedance are set to 0.2 x RQ, where RQ is a

[x:0]

Functional Overview

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, CY7C1415AV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1411AV18, four 9-bit data transfers in the case of CY7C1426AV18, four 18-bit data transfers in the case of CY7C1413AV18, and four 36-bit data in the case of CY7C1415AV18 transfers in two clock cycles.

Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K is referenced to the output clocks (C and C in single clock mode).

All synchronous data inputs (D registers controlled by the input clocks (K and K synchronous data outputs (Q

Document Number: 38-05614 Rev. *C Page 7 of 28

[x:0]

) and all output timing

or K and K when

) inputs pass through input

). All

) outputs pass through output

registers controlled by the rising edge of the output clocks (C and C or K and K when in single-clock mode).

All synchronous control (RPS, WPS, BWS through input registers controlled by the rising edge of the input clocks (K and K).

CY7C1413AV18 is described in the following sections. The same basic descriptions apply to CY7C1411AV18, CY7C1426AV18, and CY7C1415AV18.

Read Operations

The CY7C1413AV18 is organized internally as 4 arrays of 512K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q subsequent rising edge of C the next 18-bit data word is driven onto the Q words have been driven out onto Q will be valid 0.45 ns from the rising edge of the output clock (C or C or (K or K when in single-clock mode)). In order to maintain the internal logic, each read access must be allowed to complete. Each Read access consists of four 18-bit data

active at the rising edge of the Positive Input

using C as the output timing reference. On the

[17:0]

. This process continues until all four 18-bit data

[17:0]

) inputs pass

[x:0]

. The requested data

[+] Feedback [+] Feedback

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C single-clock mode).

When the read port is deselected, the CY7C1413AV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Positive Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D into the lower 18-bit Write Data register, provided BWS both asserted active. On the subsequent rising edge of the Negative Input Clock (K is also stored into the Write Data register, provided BWS are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Inpu t Clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When deselected, the Write port will ignore all inputs after the pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1413AV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS data words. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that b yte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1413AV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K operation is identical to the operation if the device had zero skew between the K/K remain the same in this mode. To use this mode of operation, the user must tie C and C a strap option and not alterable during device operation.

) that control both the input and output registers. This

and BWS1, which are sampled with each set of 18-bit

) the information presented to D

and C/C clocks. All timing parameters

HIGH at power on. This function is

or K and K when in

active at the

is latched and stored

[17:0]

[1:0]

are

[17:0]

[1:0]

Concurrent Tr a ns a ct ion s

The Read and Write ports on the CY7C1413AV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location when a Read follows a Write in successive clock cycles, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise.

Read accesses and Write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read.

Depth Expansion

The CY7C1413AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω

= 1.5V. The output impedance is adjusted every 1024

DDQ

cycles upon power-up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with resp ect to K and CQ echo clocks are shown in the AC Timing table.

is referenced with respect to C. These are free running

is generated with respect to K . The timings for the

to allow the SRAM to adjust its

, with

Document Number: 38-05614 Rev. *C Page 8 of 28

[+] Feedback [+] Feedback

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF

is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the

BUS

MASTER

(CPU

ASIC)

[1]

DATA IN

DATA OUT

Address

RPS# WPS# BWS#

CLKIN/CLKIN#

Source K

Source K#

Delayed K

Delayed K#

D A

R = 50ohms

SRAM #1

Vt = Vddq/2

CC#

Application Example

Truth Table

[2, 3, 4, 5, 6, 7]

DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented.the DLL may be disabled by applying ground to the DOFF pin. For information refer to the application note “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”.

CQ/CQ#

R = 250ohms

D A

SRAM #4

CC#

Vt Vt

CQ/CQ#

R = 250ohms

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

L-H H

[8]L[9]

D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑ Load address on the rising edge of K; input write data on two consecutive K and K

rising edges.

Read Cycle:

L-H L

[9]

X Q(A) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑ Q(A + 2) at C(t + 2) ↑ Q(A + 3) at C(t + 3) ↑ Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C

and C

rising edges. NOP: No Operation L-H H H D = X

Q = High-Z

Standby: Clock

Stopped X X Previous State Previous State Previous State Previous State

D = X Q = High-Z

Stopped

Notes:

1. The above application shows four QDR-II being used.

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

3. Device will power-up deselected and the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read or Write request.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

↑ represents rising edge.

Document Number: 38-05614 Rev. *C Page 9 of 28

[+] Feedback [+] Feedback

+ 19 hidden pages

CYPRESS CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, CY7C1415AV18 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual