Datasheet CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, CY7C1415AV18 Datasheet (CYPRESS)

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

36-Mbit QDR™-II SRAM 4-Word Burst

Architecture

Features

• Separate Independent Read and Write data ports — Supports concurrent tra nsactions

• 300-MHz clock for high bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 600 MHz) at 300 MHz

• Two input clocks (K and K) for precise DDR timing — SRAM uses rising edg es only

• Two input clocks for output dat a (C and C clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ high-speed systems

• Single multiplexed address input bus latches address inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency providing most current data

•Core V

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

= 1.8 (±0.1V); I/O V

) simplify data capture in

= 1.4V to V

DDQ

) to minimize

Configurations

CY7C1411AV18 – 4M x 8 CY7C1426AV18 – 4M x 9 CY7C1413AV18 – 2M x 18 CY7C1415AV18 – 1M x 36

Functional Description

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, and CY7C1415AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1411AV18) or 9-bit words (CY7C1426AV18) or 18-bit words (CY7C1413AV18) or 36-bit words (CY7C1415AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K

and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled

by the K or K registers controlled by the C or C domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

input clocks. All data outputs pass through output

(or K or K in a single clock

Selection Guide

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 300 278 250 200 167 MHz Maximum Operating Current 925 875 800 700 600 mA

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document Number: 38-05614 Rev. *C Revised June 26, 2006

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Logic Block Diagram (CY7C1411A V18)

[7:0]

Address

(19:0)

Write

Reg

1M x 8 Array

Write

Reg

1M x 8 Array

Address Register

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

(19:0)

K K

CLK Gen.

DOFF

REF

WPS NWS

[1:0]

Control

Logic

Logic Block Diagram (CY7C1426AV18)

[8:0]

Address

(19:0)

K K

CLK

Gen.

DOFF

Write Add. Decode

Read Data Reg.

Write

Reg

1M x 9 Array

Write Add. Decode

Read Data Reg.

Write

Reg

1M x 9 Array

Control

Read Add. Decode

Logic

Reg.

Address Register

Control

Read Add. Decode

Logic

Reg.

RPS

[7:0]

(19:0)

RPS

REF

WPS BWS

Control

[0]

Logic

Reg.

[8:0]

Document Number: 38-05614 Rev. *C Page 2 of 28

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Logic Block Diagram (CY7C1413AV18)

[17:0]

Address

(18:0)

Write

Reg

512K x 18 Array

Write

Reg

512K x 18 Array

Address Register

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

(18:0)

K K

CLK Gen.

DOFF

REF

WPS BWS

[1:0]

Control

Logic

Logic Block Diagram (CY7C1415AV18)

[35:0]

Address

(17:0)

K K

CLK Gen.

DOFF

Write Add. Decode

Read Data Reg.

Write

Reg

256K x 36 Array

Write Add. Decode

Read Data Reg.

Write

Reg

256K x 36 Array

Write

Reg

256K x 36 Array

Control

Reg.

Logic

Reg.

Read Add. Decode

Reg.

Address Register

Control

Read Add. Decode

Logic

RPS

C C

RPS

C C

[17:0]

(17:0)

[35:0]

REF

WPS BWS

[3:0]

Control

Logic

144

Reg.

Document Number: 38-05614 Rev. *C Page 3 of 28

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Pin Configurations

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1411AV18 (4M x 8)

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

A B C D E F G H

K L M N P

A B

C D

E F G H

K L M N P

NC NC NC

NC V NC NC

DOFF

NC NC NC NC NC NC

TDO

NC/72M A

NC NC NC

D4 V NC NC

REF

NC NC Q6

D7 NC

TCK

NC NC V

Q4 NC Q5 V

DDQ

NC NC

NC NC Q7

A NC/288M K NWS

DDQ

DDQ DDQ

DDQ

NWS

ANCA

A A

KWPS

SS SS

A C

NC/144M

A A

RPS

A NC NC Q3

DDQ

DDQ DDQ

DDQ

A A

91011

NC NC D3

D2 NC NC

REF

Q1 NC NC NC NC NC

NC NC NC NC

DDQ

NC NC NC NC D0 NC NC

NC Q2

NC ZQ

D1V NC Q0

NC NC

TDITMS

CY7C1426AV18 (4M x 9)

CQ NC NC NC NC V NC NC

DOFF

NC NC NC NC NC NC

TDO

NC/72M A NC K

NC NC NC D5 V NC NC D6

REF

NC NC Q7

D8 NC

TCK

NC NC V

Q5 NC Q6 V

DDQ

NC NC D7 NC NC Q8

WPS NC/144M

A NC/288M K BWS

DDQ

DDQ DDQ

DDQ

ANCA

A A

SS SS

A C

A A

DDQ

DDQ DDQ

DDQ

A A

91011

AARPS

NC Q4

NC NC D4

D3 NC NC

REF

Q2 NC NC NC NC

NC NC NC NC

DDQ

NC NC NC NC D1 NC NC

NC ZQ

D2V

TDITMS

Document Number: 38-05614 Rev. *C Page 4 of 28

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Pin Configurations (continued)

165-ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1413AV18 (2M x 18)

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

A B C

D E F G

K L M N P

A B C D E F G H

K L M N P

CQ NC

NC NC

NC V NC NC

DOFF

NC NC NC NC NC NC

TDO

NC/144M A

Q9 D9 NC

D11 V

NC Q12 D13

REF

NC Q15 NC D17

NC TCK

D10

Q10 V

Q11 D12

Q13 V

DDQ

D14

Q14

D15

D16 Q16 Q17

A NC K

DDQ

DDQ DDQ

DDQ

567

BWS

ANCA

V V V

V A A

KWPS

SS SS SS SS SS

SS SS SS SS

A C

NC/288M

BWS

A A

RPS

A NC NC Q8

DDQ

DDQ DDQ

DDQ

A A

91011

ANC/72M

NC Q7 D8 NC

NC NC Q5 NC

DDQ

NC NC NC NC D2 NC NC

D6 NC NC

REF

D3 NC Q1 NC

D7 Q6

D4V Q3 Q2

D1 Q0

TDITMS

CY7C1415AV18 (1M x 36)

Q27 D27 D28

Q29 V

Q30

D30

DOFF

D31 Q32 Q33 D33 D34 Q35

TDO

NC/288M NC/72M

Q18 Q28

D20 V D29

Q21

D22

REF

Q31

D32

Q24

Q34

D26 D35

TCK

D18 D19 Q19 V Q20 D21 Q22 V

DDQ

D23 Q23 D24 D25 Q25 Q26

456

WPS BWS

DDQ

DDQ DDQ

DDQ

BWS

ANCA

A A

K K

SS SS

A C

BWS

A A

1 0

891011

RPS

A D17

DDQ

DDQ DDQ

DDQ

A A

NC/144M

Q17 D16 Q7 D8 Q16 Q15 D14 Q5 Q13

DDQ

D12 Q12 D11 D10 D2 Q10

D15

D6 Q14 D13

D3 Q11

REF

D7 Q6

D4V Q3 Q2

D1 Q0

TDITMS

Document Number: 38-05614 Rev. *C Page 5 of 28

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Pin Definitions

Pin Name I/O Pin Description

[x:0]

WPS

NWS

BWS0, BWS1, BWS

, BWS

A Input-

[x:0]

RPS Input-

C Input-

K Input-

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Outputs-

Synchronous

Clock

Input-

Clock

Input-

Clock

Data input signals, sampled on the rising edge of K and K clocks during valid write operations.

CY7C1411AV18 − D CY7C1426AV18 − D CY7C1413AV18 − D CY7C1415AV18 − D

[7:0] [8:0] [17:0] [35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D

to be ignored.

[x:0]

Nibble Write Select 0, 1 − active LOW.(CY7C1411AV18 Only) Sampled on the rising edge of the K and K NWS All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble

clocks during Write operations. Used to select which nibble is written into the device

controls D

and NWS1 controls D

[3:0]

[7:4]

Write Select will cause the corresponding nibble of data to be ignored and not written into the device.

Byte Write Select 0, 1, 2, and 3 − active LOW . Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1426AV18 − BWS CY7C1413AV18 − BWS0 controls D CY7C1415AV18 − BWS0 controls D controls D All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write

[35:27].

controls D

[8:0]

and BWS1 controls D

[8:0]

, BWS1 controls D

[8:0]

Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active Read and Write opera-

tions. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 4M x 8 (4 arrays each of 1M x 8) for CY7C1411AV18, 4M x 9 (4 arrays each of 1M x 9) for CY7C1426AV18,2M x 18 (4 arrays each of 512K x 18) for CY7C1413AV18 and 1M x 36 (4 arrays each of 256K x 36) for CY7C1415AV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1411AV18 and CY7C1426AV18, 19 address inputs for CY7C1413AV18 and 18 address inputs for CY7C1415A V18. These inputs are ignored when the appropriate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C

. when in single clock mode. When the Read port is deselected, Q

K tri-stated. CY7C1411AV18 − Q CY7C1426AV18 − Q CY7C1413AV18 − Q CY7C1415AV18 − Q

[7:0]

[8:0] [17:0] [35:0]

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of four sequential transfers.

Positive Input Clock for Output Data. C is used in conjunction with C data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read

data from the device. C and C

can be used together to deskew the flight times of various devices

on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the

device and to drive out data through Q on the rising edge of K.

when in single clock mode. All accesses are initiated

[x:0]

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q

when in single clock mode.

[x:0]

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

[17:9].

, BWS2 controls D

[17:9]

clocks during Read operations or K and

are automatically

[x:0]

to clock out the Read

[26:18]

and BWS3

Document Number: 38-05614 Rev. *C Page 6 of 28

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Pin Definitions (continued)

Pin Name I/O Pin Description

CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the Input

clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table.

ZQ Input Output Impedance Matching Inpu t. This input is used to tune the device outputs to the system

DOFF Input DLL T urn Off - active LOW . Connecting this pin to ground will turn off the DLL inside the device.

TDO Output TDO for JTAG. TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/72M N/A Not connected to the die. Can be tied to any voltage level.

NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level.

REF

DDQ

Echo Clock

Input-

Reference

Power Supply Power supply inputs to the core of the device.

Ground Ground for the device.

Power Supply Power supply inputs for the outputs of the device.

is referenced with respect to C. This is a free running clock and is synchronized to the Input

clock for output data (C to K

. The timings for the echo clocks are shown in the AC Timing table.

data bus impedance. CQ, CQ resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V

, which enables the minimum impedance mode. This pin cannot be conne cted directly to

DDQ

GND or left unconnected.

The timings in the DLL turned off operation will be different from those listed in this data sheet.

Reference Volt age Input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points.

) of the QDR-II. In the single clock mode, CQ is generated with respect

, and Q

output impedance are set to 0.2 x RQ, where RQ is a

[x:0]

Functional Overview

The CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, CY7C1415AV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1411AV18, four 9-bit data transfers in the case of CY7C1426AV18, four 18-bit data transfers in the case of CY7C1413AV18, and four 36-bit data in the case of CY7C1415AV18 transfers in two clock cycles.

Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K is referenced to the output clocks (C and C in single clock mode).

All synchronous data inputs (D registers controlled by the input clocks (K and K synchronous data outputs (Q

Document Number: 38-05614 Rev. *C Page 7 of 28

[x:0]

) and all output timing

or K and K when

) inputs pass through input

). All

) outputs pass through output

registers controlled by the rising edge of the output clocks (C and C or K and K when in single-clock mode).

All synchronous control (RPS, WPS, BWS through input registers controlled by the rising edge of the input clocks (K and K).

CY7C1413AV18 is described in the following sections. The same basic descriptions apply to CY7C1411AV18, CY7C1426AV18, and CY7C1415AV18.

Read Operations

The CY7C1413AV18 is organized internally as 4 arrays of 512K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q subsequent rising edge of C the next 18-bit data word is driven onto the Q words have been driven out onto Q will be valid 0.45 ns from the rising edge of the output clock (C or C or (K or K when in single-clock mode)). In order to maintain the internal logic, each read access must be allowed to complete. Each Read access consists of four 18-bit data

active at the rising edge of the Positive Input

using C as the output timing reference. On the

[17:0]

. This process continues until all four 18-bit data

[17:0]

) inputs pass

[x:0]

. The requested data

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C single-clock mode).

When the read port is deselected, the CY7C1413AV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Positive Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D into the lower 18-bit Write Data register, provided BWS both asserted active. On the subsequent rising edge of the Negative Input Clock (K is also stored into the Write Data register, provided BWS are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Inpu t Clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K

When deselected, the Write port will ignore all inputs after the pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1413AV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS data words. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that b yte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1413AV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K operation is identical to the operation if the device had zero skew between the K/K remain the same in this mode. To use this mode of operation, the user must tie C and C a strap option and not alterable during device operation.

) that control both the input and output registers. This

and BWS1, which are sampled with each set of 18-bit

) the information presented to D

and C/C clocks. All timing parameters

HIGH at power on. This function is

or K and K when in

active at the

is latched and stored

[17:0]

[1:0]

are

[17:0]

[1:0]

Concurrent Tr a ns a ct ion s

The Read and Write ports on the CY7C1413AV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location when a Read follows a Write in successive clock cycles, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise.

Read accesses and Write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read.

Depth Expansion

The CY7C1413AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω

= 1.5V. The output impedance is adjusted every 1024

DDQ

cycles upon power-up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with resp ect to K and CQ echo clocks are shown in the AC Timing table.

is referenced with respect to C. These are free running

is generated with respect to K . The timings for the

to allow the SRAM to adjust its

, with

Document Number: 38-05614 Rev. *C Page 8 of 28

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF

is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the

BUS

MASTER

(CPU

ASIC)

[1]

DATA IN

DATA OUT

Address

RPS# WPS# BWS#

CLKIN/CLKIN#

Source K

Source K#

Delayed K

Delayed K#

D A

R = 50ohms

SRAM #1

Vt = Vddq/2

CC#

Application Example

Truth Table

[2, 3, 4, 5, 6, 7]

DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented.the DLL may be disabled by applying ground to the DOFF pin. For information refer to the application note “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”.

CQ/CQ#

R = 250ohms

D A

SRAM #4

CC#

Vt Vt

CQ/CQ#

R = 250ohms

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

L-H H

[8]L[9]

D(A) at K(t + 1) ↑ D(A + 1) at K(t +1) ↑ D(A + 2) at K(t + 2) ↑ D(A + 3) at K(t + 2) ↑ Load address on the rising edge of K; input write data on two consecutive K and K

rising edges.

Read Cycle:

L-H L

[9]

X Q(A) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑ Q(A + 2) at C(t + 2) ↑ Q(A + 3) at C(t + 3) ↑ Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C

and C

rising edges. NOP: No Operation L-H H H D = X

Q = High-Z

Standby: Clock

Stopped X X Previous State Previous State Previous State Previous State

D = X Q = High-Z

Stopped

Notes:

1. The above application shows four QDR-II being used.

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

3. Device will power-up deselected and the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K

7. It is recommended that K = K charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read or Write request.

rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line

↑ represents rising edge.

Document Number: 38-05614 Rev. *C Page 9 of 28

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Write Cycle Descriptions

(CY7C1411AV18 and CY7C1413AV18)

BWS0/NWS0BWS1/NWS1KK

[2, 10]

Comments

L L L–H – During the Data portion of a Write sequence:

CY7C1411AV18 − both nibbles (D CY7C1413AV18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L L – L-H During the Data portion of a Write sequence:

CY7C1411AV18 − both nibbles (D CY7C1413AV18 − both bytes (D

) are written into the device,

[7:0]

) are written into the device.

[17:0]

L H L–H – During the Data portion of a Write sequence :

CY7C1411AV18 − only the lower nibble (D unaltered, CY7C1413AV18 − only the lower byte (D unaltered.

) is written into the device. D

[3:0]

) is written into the device. D

[8:0]

L H – L–H During the Data portion of a Write sequence :

CY7C1411AV18 − only the lower nibble (D unaltered, CY7C1413AV18 − only the lower byte (D unaltered.

) is written into the device. D

[3:0]

) is written into the device. D

[8:0]

H L L–H – During the Data portion of a Write sequence :

CY7C1411AV18 − only the upper nibble (D remain unaltered, CY7C1413AV18 − only the upper byte (D unaltered.

) is written into the device. D

[7:4]

) is written into the device. D

[17:9]

H L – L–H During the Data portion of a Write sequence :

CY7C1411AV18 − only the upper nibble (D remain unaltered, CY7C1413AV18 − only the upper byte (D unaltered.

) is written into the device. D

[7:4]

) is written into the device. D

[17:9]

H H L–H – No data is written into the devices during this portion of a write operation. H H – L–H No data is written into the devices during this portion of a write operation.

Note:

10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS portions of a Write cycle, as long as the set-up and hold requirements are achieved.

, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different

will remain

[7:4]

will remain

[17:9]

will remain

[7:4]

will remain

[17:9]

[3:0]

will remain

[8:0]

[3:0]

will remain

[8:0]

will

Document Number: 38-05614 Rev. *C Page 10 of 28

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Write Cycle Descriptions

BWS

BWS1BWS2BWS3KK Comments

L L L L L–H – During the Data portion of a Write sequence, all four bytes (D

L L L L – L–H During the Data portion of a Write sequence, all four bytes (D

[2, 10]

(CY7C1415AV18)

into the device.

[35:0]

L H H H L–H – During the Data portion of a Write sequence, only the lower byte (D

into the device. D

will remain unaltered.

[35:9]

L H H H – L–H During the Data portion of a Write sequence, only the lower byte (D

into the device. D

H L H H L–H – During the Data portion of a Write sequence, only the byte (D

the device. D

[8:0]

H L H H – L–H During the Data portion of a Write sequence, only the byte (D

the device. D

[8:0]

H H L H L–H – During the Data portion of a Write sequence, only the byte (D

into the device. D

H H L H – L–H During the Data portion of a Write sequence, only the byte (D

into the device. D

H H H L L–H During the Data portion of a Write sequence, only the byte (D

into the device. D

H H H L – L–H During the Data portion of a Write sequence, only the byte (D

into the device. D

will remain unaltered.

[35:9]

and D

[17:0]

and D

[17:0]

will remain unaltered.

[26:0]

will remain unaltered.

[26:0]

will remain unaltered.

[35:18]

will remain unaltered.

[35:18]

[35:27]

will remain unaltered.

) is written into

[17:9]

) is written into

[17:9]

[26:18]

[35:27]

HHHHL–H–No data is written into the device during this portion of a write operation. HHHH–L–HNo data is written into the device during this portion of a write operation.

Write Cycle Descriptions

[2, 10]

(CY7C1426AV18)

) are written

) is written

[8:0]

) is written

[8:0]

) is written

BWS

L L–H – During the Data portion of a Write sequence, the single byte (D L – L–H During the Data portion of a Write sequence, the single byte (D

KK Comments

[8:0]

H L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation.

) is written into the device.

Document Number: 38-05614 Rev. *C Page 11 of 28

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates u sing JEDEC standard 1.8V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the T AP controller, TCK must be tied LOW (V

) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the T AP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram.

) for five rising

Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (V

) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices.

The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring.

The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.

TAP Instruction Set

Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.

Document Number: 38-05614 Rev. *C Page 12 of 28

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SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR sta te. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and ou tput pi ns is captured in the boundary scan register.

The user must be aware that the T AP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to th e value that will be captured. Repeatable results may not be possible.

To guarantee th at the boundary scan regi ster will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (t captured correctly if there is no way in a design to stop (o r slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK boundary scan register.

Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in.

and tCH). The SRAM clock input might not be

captured in the

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at b it #108. When this scan cell, called the “extest output bus tristate”, is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

Document Number: 38-05614 Rev. *C Page 13 of 28

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TAP Controller State Diagram

TEST-LOGIC RESET

TEST-LOGIC/

IDLE

[11]

SELECT DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

SELECT

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-DR

EXIT2-DR

UPDATE-DR

Note:

11.The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

PAUSE-IR

EXIT2-IR

UPDATE-IR

Document Number: 38-05614 Rev. *C Page 14 of 28

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TAP Controller Block Diagram

TDI

Selection Circuitry

Bypass Register

Instruction Register

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

012

Selection Circuitry

TDO

3031

012..

Identification Register

.106

012..

Boundary Scan Register

TCK TMS

TAP Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Max. Unit

V V V V V V I

OH1 OH2 OL1 OL2 IH IL

Output HIGH Voltage I Output HIGH Voltage I Output LOW Voltage IOL = 2.0 mA 0.4 V Output LOW Voltage IOL = 100 µA0.2V Input HIGH Voltage 0.65V Input LOW Voltage –0.3 0.35V Input and Output Load Current GND ≤ VI ≤ V

TAP AC Switching Characteristics Over the Operating Range

Parameter Description Min. Max. Unit

TCYC

Set-up Times

TMSS

TDIS

Hold Times

TMSH

TDIH

Notes:

12.These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

13.t

and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

14.Test conditions are specified using the load in TAP AC test conditions. t

TCK Clock Cycle Time 50 ns TCK Clock Frequency 20 MHz TCK Clock HIGH 20 ns TCK Clock LOW 20 ns

TMS Set-up to TCK Clock Rise 5 ns TDI Set-up to TCK Clock Rise 5 ns Capture Set-up to TCK Rise 5 ns

TMS Hold after TCK Clock Rise 5 ns TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns

TA P Controller

[17, 20, 12]

= −2.0 mA 1.4 V

= −100 µA1.6 V

+ 0.3 V

R/tF

= 1 ns.

[13, 14]

–5 5 µA

Document Number: 38-05614 Rev. *C Page 15 of 28

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TAP AC Switching Characteristics Over the Operating Range

[13, 14]

(continued)

Parameter Description Min. Max. Unit

Output Times

TDOV

TDOX

TAP Timing and Test Conditions

TDO

TCK Clock LOW to TDO Valid 10 ns TCK Clock LOW to TDO Invalid 0 ns

[14]

= 50Ω

(a)

0.9V

GND

50Ω

= 20 pF

ALL INPUT PULSES

1.8V

0.9V

Test Clock TCK

TMSS

TMSH

TCYC

Test Mode Select TMS

Test Data-In TDI

Test Data-Out TDO

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Cypress Device ID (28:12)

Cypress JEDEC ID (11:1)

ID Register Presence (0)

11010011011000111 11010011011001111 11010011011010111 11010011011100111 Defines the

000 000 000 000 Version

00000110100 00000110100 00000110100 00000110100 Allows unique

1 1 1 1 Indicates the

TDIS

Value

TDOV

TDIH

TDOX

DescriptionCY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

number.

type of SRAM.

identification of SRAM vendor.

presence of an ID register.

Document Number: 38-05614 Rev. *C Page 16 of 28

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Scan Register Sizes

Instruction 3 Bypass 1 ID 32 Boundary Scan 109

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and place s the register

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register

RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan

RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 1 11 Places the bypass register between TDI and TDO. This operation does

between TDI and TDO. This operation does not affect SRAM operation.

between TDI and TDO. Forces all SRAM output drivers to a High-Z state.

not affect SRAM operation.

Document Number: 38-05614 Rev. *C Page 17 of 28

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Boundary Scan Order

Bit # Bump ID Bi t # Bu mp ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 1J 16P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 47N329F605C882K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 1 1P 37 9E 65 2B 93 1L

10 10P 38 10C 66 3B 94 3N

11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H

Document Number: 38-05614 Rev. *C Page 18 of 28

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Power-Up Sequence in QDR-II SRAM

QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

Power-Up Sequence

• Apply power and drive DOFF LOW (All other inputs can be HIGH or LOW)

—Apply VDD before V —Apply V

• After the power and clock (K, K, C, C) are stable take DOFF HIGH

• The additional 1024 cycles of clocks are required for the DLL to lock.

DDQ

before V

DDQ

or at the same time as V

REF

[15, 16]

REF

Power-up Waveforms

Unstable Clock

Clock Start

(Clock Starts after Stable)

DLL Constraints

• DLL uses either K or C clock as its synchronizing input.The input should have low phase jitter, which is specified as t

KC Var

• The DLL will function at frequencies down to 80MHz.

• If the input clock is unstable and the DLL is enabled, then

the DLL may lock to an incorrect frequency, causing unstable SRAM behavior

> 1024 Stable clock

DDQ

Start Normal Operation

Notes:

15.It is recommended that the DOFF

16.During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock.

DDQ

DOFF

pin be pulled HIGH via a pull up resistor of 1Kohm.

Stable (< +/- 0.1V DC per 50ns )

DDQ

Fix High (or tied to V

DDQ

)

Document Number: 38-05614 Rev. *C Page 19 of 28

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Maximum Ratings

(Above which the useful life may be impaired.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with Powe r Applied..–55°C to +125°C Supply Voltage on V Supply Voltage on V

DC Applied to Outputs in High-Z .........–0.5V to V

DC Input Voltage

Relative to GND........–0.5V to +2.9V

Relative to GND......–0.5V to +V

DDQ

[20]

...............................–0.5V to VDD + 0.3V

DDQ

+ 0.3V

Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V

Latch-up Current..................................................... >200 mA

Operating Range

Range

Temperature (TA)V

Com’l 0°C to +70°C 1.8 ± 0.1V 1.4V to V Ind’l –40°C to +85°C

Ambient

[21]

DDQ

[21]

Current into Outputs (LOW).........................................20 mA

Electrical Characteristics Over the Operating Range

[17]

DC Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

DDQ

OH(LOW)

OL(LOW)

REF

Power Supply Voltage 1.7 1.8 1.9 V I/O Supply Voltage 1.4 1.5 V Output HIGH Voltage Note 18 V Output LOW Voltage Note 19 V Output HIGH Voltage I

= −0.1 mA, Nominal Impedance V

Output LOW Voltage IOL = 0.1 mA, Nominal Impedance V Input HIGH Voltage Input LOW Voltage Input Leakage Current GND ≤ VI ≤ V Output Leakage Current GND ≤ VI ≤ V Input Reference Voltage VDD Operating Supply V

[20]

DDQ

Output Disabled −55µA

= 1/t

DDQ,

OUT

CYC

= 0mA,

167 MHz 600 mA 200 MHz 700 mA

[22]

Typical Value = 0.75V 0.68 0.75 0.95 V

= Max., I

f = f

MAX

/2 – 0.12 V

DDQ

/2 – 0.12 V

DDQ

– 0.2 V

DDQ

+ 0.1 V

REF

–0.3 V

−55µA

/2 + 0.12 V

DDQ

/2 + 0.12 V

DDQ

0.2 V + 0.3 V

DDQ

– 0.1 V

REF

250 MHz 800 mA 278 MHz 875 mA 300 MHz 925 mA

SB1

Automatic Power-down Current

Max. VDD, Both Ports Deselected, V V

≤ VIL

f = f Inputs Static

MAX

= 1/t

≥ VIH or

CYC,

167 MHz 270 mA 200 MHz 300 mA 250 MHz 330 mA 278 MHz 355 mA 300 MHz 370 mA

AC Input Requirements

Over the Operating Range

Parameter Description Test Conditions Min. Typ. Max. Unit

Notes:

17.All Voltage referenced to Ground.

18.Output are impedance controlled. I

19.Output are impedance controlled. I

20.Overshoot: V

21.Power-up: Assumes a linear ramp from 0V to V

22.V

REF

Input HIGH Voltage V

+ 0.2 – – V

REF

Input LOW Voltage – – V

(AC) < V

(Min.) = 0.68V or 0.46V

DDQ

= −(V

= (V

+ 0.85V (Pulse width less than t

, whichever is larger, V

DDQ

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.

DDQ

/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.

DDQ

(min.) within 200 ms. During this time V

/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than t

CYC

(Max.) = 0.95V or 0.54V

REF

< V

and V

, whichever is smaller.

DDQ

< V

CYC

/2).

– 0.2 V

REF

Document Number: 38-05614 Rev. *C Page 20 of 28

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Capacitance

[23]

Parameter Description T est Conditions Max. Unit

Input Capacitance TA = 25°C, f = 1 MHz,

CLK

Clock Input Capacitance 4 pF Output Capacitance 5 pF

Thermal Resistance

[23]

V V

DD DDQ

= 1.8V

= 1.5V

5pF

165 FBGA

Parameter Description Test Conditions

Thermal Resistance

(Junction to Ambient) Thermal Resistance

(Junction to Case)

Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51.

Package Unit

17.2 °C/W

3.2 °C/W

AC Test Loads and Waveforms

= 0.75V

REF

(a)

0.75V

RQ = 250

= 50Ω

Ω

REF

= 50Ω

= 0.75V

REF

OUTPUT

Device Under Test

0.75V

RQ = 250

(b)

R = 50Ω

5pF

Ω

0.25V

ALL INPUT PULSES

1.25V

0.75V

Slew Rate = 2 V/ns

REF

OUTPUT Device

Under Test

[24]

Notes:

23.Tested initially and after any design or process change that may affect these parameters.

24.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, V pulse levels of 0.25V to 1.25V, and output loading of the specified I

and load capacitance shown in (a) of AC Test Loads.

OL/IOH

= 1.5V, input

DDQ

Document Number: 38-05614 Rev. *C Page 21 of 28

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Switching Characteristics Over the Operating Range

Cypress

Parameter

POWER

CYC

KHKH

Consortium

Parameter Description

VDD(Typical) to the First

[29]

Access

KHKH

KHKL

KLKH

KHKH

K Clock and C Clock Cycle Time

Input Clock (K/K; C/C) HIGH

Input Clock (K/K; C/C) LOW

K Clock Rise to K Clock Rise and C to C

Rise

[24, 25]

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

11111ms

3.30 5.25 3.60 5.25 4.0 6.3 5.0 7.9 6.0 8.4 ns

1.32 – 1.4 – 1.6 – 2.0 2.4 – ns

1.32 – 1.4 – 1.6 – 2.0 – 2.4 – ns

1.49 – 1.6 – 1.8 – 2.2 – 2.7 – ns

(rising edge to rising edge)

KHCH

K/K Clock Rise to C/C Clock Rise (rising edge to

0.0 1.45 0.0 1.55 0.0 1.8 0.0 2.2 0.0 2.7 ns

rising edge)

Set-up Times

SCDDR

[27]

AVKH

IVKH

DVKH

Address Set-up to K Clock Rise

Control Set-up to K Clock Rise (RPS

, WPS)

Double Data Rate Control

BWS2,

) Rise

Set-up to Clock (K, K (BWS

, BWS

BWS

)

Set-up to Clock (K/K)

[X:0]

Rise

0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Hold Times

HCDDR

KHAX

KHIX

KHDX

Address Hold after K Clock Rise

Control Hold after K Clock Rise (RPS

, WPS)

Double Data Rate Control

BWS2,

) Rise

Hold after Clock (K, K (BWS

, BWS

BWS

)

Hold after Clock

[X:0]

) Rise

(K/K

0.4 – 0.4 – 0.5 – 0.6 – 0.7 – ns

0.3 – 0.3 – 0.35 – 0.4 – 0.5 – ns

Output Times

CHQV

C/C Clock Rise (or K/K in single clock mode) to Data

0.45 0.45 – 0.45 – 0.45 – 0.50 ns

Valid

DOH

CHQX

Data Output Hold after Output C/C

Clock Rise

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

(Active to Active)

Notes:

25.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequen cy, it requires the input timings of the frequency range in which it is being operated and will output dat a with the output timings of that frequency range.

26.This part has a voltage regulator internally; t can be initiated.

27.For D2 data signal on CY7C1426AV18 device, t

, t

28.t

29.At any given voltage and temperature t

, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

CHZ

CLZ

CHZ

is the time that the power needs to be supplied above V

POWER

is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.

is less than t

CLZ

and t

less than tCO.

CHZ

minimum initially before a Read or Write operation

Document Number: 38-05614 Rev. *C Page 22 of 28

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Switching Characteristics Over the Operating Range

Cypress

Parameter

CCQO

CQOH

CQD

CQDOH

CHZ

CLZ

Consortium

Parameter Description

CHCQV

CHCQX

CQHQV

CQHQX

CHQZ

CHQX1

DLL Timing

KC Var

KC lock

KC ResettKC Reset

KC Var

KC lock

C/C Clock Rise to Echo Clock Valid

Echo Clock Hold after C/C Clock Rise

Echo Clock High to Data Valid

Echo Clock High to Data Invalid

Clock (C/C) Rise to High-Z (Active to High-Z)

Clock (C/C) Rise to

[28, 29]

Low-Z

[28, 29]

Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 – 0.20 ns DLL Lock Time (K, C) 1024 – 1024 – 1024 – 1024 – 1024 – Cycles K Static to DLL Reset 30 30 30 30 30 ns

300 MHz 278 MHz 250 MHz 200 MHz 167 MHz

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

–0.27 – –0.27 – –0.30 – –0.35 – –0.40 – ns

– 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns

–0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns

[24, 25]

(continued)

0.27 0.27 – 0.30 – 0.35 – 0.40 ns

UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Document Number: 38-05614 Rev. *C Page 23 of 28

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Switching Waveforms

[30, 31, 32]

Read/Write/Deselect Sequence

NOP

READ

RPS

WPS

A0 A1

CYC

READWRITE WRITE

345

KHKH

D10 D11

D12

HCSC

D13

NOP

D30 D31

D32

D33

CQD

Q22

Q23

CHZ

CQDOH

Q20

KHCH

CLZ

Q00

Q01 Q02

DOH

Q03

Q21

CYC

KHKH

CQOH

CCQO

CQOH

CCQO

DON’T CARE UNDEFINED

Notes:

30.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

31.Output are disabled (High-Z) one clock cycle after a NOP.

32.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Wr ite data is forwarded immediately as read results. This note applies to t he whole diagram.

Document Number: 38-05614 Rev. *C Page 24 of 28

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

167 CY7C1411AV18-167BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1426AV18-167BZC CY7C1413AV18-167BZC CY7C1415AV18-167BZC CY7C1411AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-167BZXC CY7C1413AV18-167BZXC CY7C1415AV18-167BZXC CY7C1411AV18-167BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1426AV18-167BZI CY7C1413AV18-167BZI CY7C1415AV18-167BZI CY7C1411AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-167BZXI CY7C1413AV18-167BZXI CY7C1415AV18-167BZXI

200 CY7C1411AV18-200BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1426AV18-200BZC CY7C1413AV18-200BZC CY7C1415AV18-200BZC CY7C1411AV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-200BZXC CY7C1413AV18-200BZXC CY7C1415AV18-200BZXC CY7C1411AV18-200BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1426AV18-200BZI CY7C1413AV18-200BZI CY7C1415AV18-200BZI CY7C1411AV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-200BZXI CY7C1413AV18-200BZXI CY7C1415AV18-200BZXI

250 CY7C1411AV18-250BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1426AV18-250BZC CY7C1413AV18-250BZC CY7C1415AV18-250BZC CY7C1411AV18-250BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-250BZXC CY7C1413AV18-250BZXC CY7C1415AV18-250BZXC

visit www.cypress.com for actual products offered.

Package Diagram Package Type

Operating

Range

Document Number: 38-05614 Rev. *C Page 25 of 28

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

Speed

(MHz) Ordering Code

250 CY7C1411AV18-250BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1426AV18-250BZI CY7C1413AV18-250BZI CY7C1415AV18-250BZI CY7C1411AV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-250BZXI CY7C1413AV18-250BZXI CY7C1415AV18-250BZXI

278 CY7C1411AV18-278BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1426AV18-278BZC CY7C1413AV18-278BZC CY7C1415AV18-278BZC CY7C1411AV18-278BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-278BZXC CY7C1413AV18-278BZXC CY7C1415AV18-278BZXC CY7C1411AV18-278BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1426AV18-278BZI CY7C1413AV18-278BZI CY7C1415AV18-278BZI CY7C1411AV18-278BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-278BZXI CY7C1413AV18-278BZXI CY7C1415AV18-278BZXI

300 CY7C1411AV18-300BZC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1426AV18-300BZC CY7C1413AV18-300BZC CY7C1415AV18-300BZC CY7C1411AV18-300BZXC 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-300BZXC CY7C1413AV18-300BZXC CY7C1415AV18-300BZXC CY7C1411AV18-300BZI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial CY7C1426AV18-300BZI CY7C1413AV18-300BZI CY7C1415AV18-300BZI CY7C1411AV18-300BZXI 51-85195 165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free CY7C1426AV18-300BZXI CY7C1413AV18-300BZXI CY7C1415AV18-300BZXI

visit www.cypress.com

Package Diagram Package Type

for actual products offered.

Operating

Range

Document Number: 38-05614 Rev. *C Page 26 of 28

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Package Diagram

165-ball FBGA (15 x 17 x 1.40 mm) (51-85195)

CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

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(

3%!4).'0,!.%

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8

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT ,NEC, and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Document Number: 38-05614 Rev. *C Page 27 of 28

© Cypress Semiconductor Corporation, 2006. The information contained herein is su bj ect to ch an ge without notice. Cypress Semiconductor Corporation assu mes no resp onsib ility for the u se of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cyp ress does not a uthorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1411AV18 CY7C1426AV18 CY7C1413AV18 CY7C1415AV18

Document History Page

Document Title: CY7C1411AV18/CY7C1426AV18/CY7C1413AV18/CY7C1415AV18 36-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 38-05614

REV. ECN NO.

DATE

** 247331 See ECN SYT New Data Sheet

*A 326519 See ECN SYT Removed CY7C1426AV18 from the title

*B 413953 See ECN NXR Converted from preliminary to final.

*C 468029 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly

ISSUE

ORIG. OF CHANGE DESCRIPTION OF CHANGE

Included 300 MHz Speed grade Replaced TBDs with their respective values for I Added Industrial temperature grade Replaced the TBDs on the Thermal Characteristics Table to Θ and Θ Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS

= 3.2°C/W

TRI-ST ATE on Page 16 Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability

Added CY7C1426AV18 part number to title. Added 278-MHz speed Bin. Changed C, C

Description in Feature Section and Pin Description

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Added Power-up sequence and Wave form on page# 19 Addeed Footnotes # 15, 16, 17 0n page# 19. Changed the description of I Current on page# 20. Modified the IDD and ISB values. Modified test condition in Footnote # 22 on page# 20 from V V

< V

DDQ

Replaced Package Name column with Package Diagram in the Ordering

DD.

Information table. Updated Ordering Information Table

to V

to Alternately, this pin can be connected directly to V

Included Maximum Ratings for Supply Voltage on V Changed the Maximum Ratings for DC Input Voltage from V Changed t changed t t

from 20 ns to 10 ns in TAP AC Switching Characteristics table

TDOV

Modified Power-Up waveform

from 100 ns to 50 ns, changed t

TCYC

, t

TDIS

, tCS, t

TMSH

TMSS

Changed the Maximum rating of Ambient Tempera ture with Power Applied from –10°C to +85°C to –55°C to +125°C Added additional notes in the AC parameter section Modified AC Switching Waveform. Updated the Typo in the AC Switching Characteristics Table. Updated the Ordering Information Table.

and I

from Input Load Current to Input Leakage

SB1

= 17.2°C/W

< VDD to

DDQ

DDQ.

Relative to GND

, t

TDIH

DDQ

and t

, t

from 10 ns to 5 ns and changed

to V

DDQ

from 40 ns to 20 ns,

DD.

Document Number: 38-05614 Rev. *C Page 28 of 28

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Datasheet CY7C1411AV18, CY7C1426AV18, CY7C1413AV18, CY7C1415AV18 Datasheet (CYPRESS)

Specifications and Main Features

Frequently Asked Questions

User Manual