CY7C138, CY7C139
4K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
Logic Block Diagram
Functional Description
■ True Dual-Ported memory cells that enable simultaneous reads
of the same memory location
■ 4K x 8 organization (CY7C138)
■ 4K x 9 organization (CY7C139)
■ 0.65-micron CMOS for optimum speed and power
■ High speed access: 15 ns
■ Low operating power: I
■ Fully asynchronous operation
■ Automatic power down
■ TTL compatible
■ Expandable data bus to 32/36 bits or more using
= 160 mA (max.)
CC
Master/Slave chip select when using more than one
device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Available in 68-pin PLCC
■ Pb-free packages available
The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9 can
be used as a standalone 8/9-bit dual-port static RAM or multiple
devices can be combined to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S
pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port
video/graphics memory.
Each port has independent control pins: chip enable (CE
or write enable (R/W
provided on each port (BUSY
), and output enable (OE). Two flags are
and INT). BUSY signals that the
), read
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE
) pin or SEM pin.
The CY7C138 and CY7C139 are available in a 68-pin PLCC.
Notes
1. BUSY
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06037 Rev. *D Revised March 12, 2009
is an output in master mode and an input in slave mode.
[+] Feedback
CY7C138, CY7C139
Pin Configurations
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
67
60
59
58
57
56
55
54
53
52
51
50
49
48
3132 33 34 35 36 37 38 39 40 41 42 43
5 4 3 2 168 666564636261
A
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
A
2728 29 30
98 7 6
47
46
45
44
A
1R
A
2R
A
3R
A
4R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
25
26
6L
7LA8LA9L
A
A
10L
11L
V
CC
NC
NC
CE
L
SEM
L
R/WLOE
L
NC
I/O
I/O
1L
0L
A
A
6R
7RA8RA9R
A
10R
NC
NC
CE
R
SEM
R
R/W
R
OE
R
I/O
7R
GND
A
11R
A
5R
A
5L
NC
CY7C138/9
[3]
[4]
NC
NC
\
Figure 1. 68-Pin PLCC (Top View)
Table 1. Pin Definitions
Left Port Right Port Description
I/O
0L–7L(8L)
A
0L–11L
CE
L
OE
L
R/W
L
SEML SEM
I/O
0R–7R(8R)
A
0R–11R
CE
R
OE
R
R/W
Data Bus Input/Output
Address Lines
Chip Enable
Output Enable
R
R
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight
semaphores. The three least significant bits of the address lines will
determine which semaphore to write or read. The I/O
writing to a semaphore. Semaphores are requested by writing a 0 into the
pin is used when
0
respective location.
INT
L
BUSY
L
M/S Master or Slave Select
V
CC
GND Ground
Table 2. Selection Guide
Maximum Access Time (ns) 15 25 35 55 ns
Maximum Operating Current Commercial 220 180 160 160 mA
Maximum Standby Current for I
Notes
3. I/O
4. I/O
Document #: 38-06037 Rev. *D Page 2 of 17
on the CY7C139.
8R
on the CY7C139.
8L
INT
BUSY
Description
R
R
Interrupt Flag. INTL is set when right port writes location FFE and is cleared
when left port reads location FFE. INT
FFF and is cleared when right port reads location FFF.
is set when left port writes location
R
Busy Flag
Power
SB1
Commercial 60 40 30 30 mA
7C138-15
7C139-15
7C138-25
7C139-25
7C138-35
7C139-35
7C138-55
7C139-55
Unit
[+] Feedback
CY7C138, CY7C139
Maximum Ratings
Notes
5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
6. Pulse width < 20 ns.
7. f
MAX
= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level
standby I
SB3
.
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State................................................–0.5V to +7.0V
DC Input Voltage
[6]
.........................................–0.5V to +7.0V
[5]
Electrical Characteristics Over the Operating Range
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Ambient
Tem per atur e
V
CC
Parameter Description Test Conditions
V
V
V
V
I
I
I
I
I
I
I
OH
OL
IH
IL
IX
OZ
CC
SB1
SB2
SB3
SB4
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current Output Disabled, GND < VO < V
Operating Current VCC = Max.,
I
= 0 mA,
OUT
Outputs Disabled
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
CEL and CER > VIH,
f = f
CEL and CER > VIH,
f = f
MAX
MAX
[7]
[7]
Both Ports
and CER > VCC – 0.2V,
CE
V
> VCC – 0.2V
IN
or V
IN
< 0.2V, f = 0
[7]
One Port
CE
or CER > VCC – 0.2V,
L
V
> VCC – 0.2V or
IN
< 0.2V, Active
V
IN
Port Outputs, f = f
MAX
[7]
7C138-15
7C139-15
7C138-25
7C139-25
Unit
Min Max Min Max
2.2 2.2 V
–10 +10 –10 +10 μA
CC
–10 +10 –10 +10 μA
Commercial 220 180 mA
Industrial 190
Commercial 60 40 mA
Industrial 50
Commercial 130 110 mA
Industrial 120
Commercial 15 15 mA
Industrial 30
Commercial 125 100 mA
Industrial 115
Document #: 38-06037 Rev. *D Page 3 of 17
[+] Feedback
CY7C138, CY7C139
Electrical Characteristics Over the Operating Range (continued)
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
Capacitance
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND < VI < V
CC
Output Leakage Current Output Disabled, GND < VO < V
Operating Current VCC = Max.,
I
= 0 mA,
OUT
Outputs Disabled
Standby Current
(Both Ports TTL Levels)
Standby Current
(One Port TTL Level)
Standby Current
(Both Ports CMOS Levels)
Standby Current
(One Port CMOS Level)
[8]
CEL and CER > VIH,
f = f
CEL and CER > VIH,
f = f
MAX
MAX
[7]
[7]
Both Ports
and CER > VCC – 0.2V,
CE
V
> VCC – 0.2V
IN
or V
IN
< 0.2V, f = 0
[7]
One Port
CE
or CER > VCC – 0.2V,
L
V
> VCC – 0.2V or
IN
< 0.2V, Active
V
IN
Port Outputs, f = f
MAX
[7]
7C138-35
7C139-35
7C138-55
7C139-55
Unit
Min Max Min Max
2.2 2.2 V
–10 +10 –10 +10 μA
CC
–10 +10 –10 +10 μA
Commercial 160 160 mA
Industrial 180 180
Commercial 30 30 mA
Industrial 40 40
Commercial 100 100 mA
Industrial 110 110
Commercial 15 15 mA
Industrial 30 30
Commercial 90 90 mA
Industrial 100 100
Parameter Description Test Conditions Max Unit
C
C
IN
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
Output Capacitance 15 pF
CC
10 pF
Document #: 38-06037 Rev. *D Page 4 of 17
[+] Feedback
CY7C138, CY7C139
Figure 2. AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
<
3ns
< 3 ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 893Ω
5V
OUTPUT
R2 = 347Ω
C= 30
pF
R
TH
= 250Ω
V
TH
= 1.4V
OUTPUT
C = 30pF
(b) Thé venin Equivalent(Load 1)
(c) Three-State Delay (Load 3)
C= 30pF
OUTPUT
Load (Load 2)
R1 = 893Ω
R2 = 347Ω
5V
OUTPUT
C= 5pF
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Switching Characteristics Over the Operating Range
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
[10,11,12]
t
LZOE
[10,11,12]
t
HZOE
[10,11,12]
t
LZCE
[10,11,12]
t
HZCE
[12]
t
PU
[12]
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
[9]
7C138-15
7C139-15
7C138-25
7C139-25
7C138-35
7C139-35
7C138-55
7C139-55
Min Max Min Max Min Max Min Max
Read Cycle Time 15 25 35 55 ns
Address to Data Valid 15 25 35 55 ns
Output Hold From Address Change 3 3 3 3 ns
CE LOW to Data Valid 15 25 35 55 ns
OE LOW to Data Valid 10 15 20 25 ns
OE Low to Low Z 3 3 3 3 ns
OE HIGH to High Z 10 15 20 25 ns
CE LOW to Low Z 3 3 3 3 ns
CE HIGH to High Z 10 15 20 25 ns
CE LOW to Power-Up 0 0 0 0 ns
CE HIGH to Power-Down 15 25 35 55 ns
Write Cycle Time 15 25 35 55 ns
CE LOW to Write End 12 20 30 40 ns
Address Set-Up to Write End 12 20 30 40 ns
Address Hold From Write End 2 2 2 2 ns
Address Set-Up to Write Start 0 0 0 0 ns
Write Pulse Width 12 20 25 30 ns
Data Set-Up to Write End 10 15 15 20 ns
Unit
Document #: 38-06037 Rev. *D Page 5 of 17
[+] Feedback
CY7C138, CY7C139
Switching Characteristics Over the Operating Range
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI/IOH
and 30-pF load capacitance.
10. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
15. t
BDD
is a calculated parameter and is the greater of t
WDD
– t
PWE
(actual) or t
DDD
– tSD (actual).
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
[9]
(continued)
Parameter Description
t
HD
[11,12]
t
HZWE
[11,12]
t
LZWE
[13]
t
WDD
[13]
t
DDD
BUSY TIMING
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
[15]
t
BDD
INTERRUPT TIMING
t
INS
t
INR
Data Hold From Write End 0 0 0 0 ns
R/W LOW to High Z 10 15 20 25 ns
R/W HIGH to Low Z 3 3 3 3 ns
Write Pulse to Data Delay 30 50 60 70 ns
Write Data Valid to Read Data Valid 25 30 35 40 ns
[14]
BUSY LOW from Address Match 15 20 20 45 ns
BUSY HIGH from Address Mismatch 15 20 20 40 ns
BUSY LOW from CE LOW 15 20 20 40 ns
BUSY HIGH from CE HIGH 15 20 20 35 ns
Port Set-Up for Priority 5 5 5 5 ns
R/W LOW after BUSY LOW 0 0 0 0 ns
R/W HIGH after BUSY HIGH 13 20 30 40 ns
BUSY HIGH to Data Valid Note 15 Note 15 Note 15 Note 15 ns
[14]
INT Set Time 15 25 25 30 ns
INT Reset Time 15 25 25 30 ns
SEMAPHORE TIMING
t
SOP
t
SWRD
t
SPS
SEM Flag Update Pulse (OE or SEM) 10 10 15 20 ns
SEM Flag Write to Read Time 5 5 5 5 ns
SEM Flag Contention Window 5 5 5 5 ns
7C138-15
7C139-15
7C138-25
7C139-25
7C138-35
7C139-35
7C138-55
7C139-55
Min Max Min Max Min Max Min Max
Unit
Switching Waveforms
Figure 3. Read Cycle No. 1 (Either Port Address Access)
Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)
Document #: 38-06037 Rev. *D Page 6 of 17
[16, 17]
[16, 18, 19]
[+] Feedback
CY7C138, CY7C139
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
SEM or CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA
INR
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
Notes
16. R/W
is HIGH for read cycle.
17. Device is continuously selected CE
= LOW and OE = LOW. This waveform cannot be used for semaphore reads.
18. Address valid prior to or coincident with CE
transition LOW.
19. CE
L
= L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
Switching Waveforms (continued)
Figure 5. Read Timing with Port-to-Port Delay (M/S
= L)
[20, 21]
Document #: 38-06037 Rev. *D Page 7 of 17
Figure 6. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
[22, 23, 24]
[+] Feedback
CY7C138, CY7C139
Switching Waveforms (continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
t
LZOE
SEM OR CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
SEM
OR CE
R/W
DATA OUT
DATA IN
t
LZWE
DATA VA LID
ADDRESS
Notes
20. BUSY
= HIGH for the writing port.
21. CE
L
= CER = LOW.
22. The internal write time of the memory is defined by the overlap of CE
or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and
either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
23. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ tSD) to allow the I/O drivers to turn off
and data to be placed on the bus for the required t
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not
apply and the write pulse can be as short as the specified t
PWE
.
24. R/W
must be HIGH during all address transitions.
Figure 7. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)
[22, 24, 25]
Document #: 38-06037 Rev. *D Page 8 of 17
Figure 8. Semaphore Read After Write Timing, Either Side
[26]
[+] Feedback
CY7C138, CY7C139
Switching Waveforms (continued)
t
SOP
t
AA
SEM
R/W
OE
I/O
0
VALID ADDRESS VALID ADDRESS
t
HD
DATAINVAL ID
DATA
OUT
VAL ID
t
OHA
A0–A
2
t
AW
t
HA
t
ACE
t
SOP
t
SCE
t
SD
t
SA
t
PWE
t
SWRD
t
DOE
WRITE CYCLE READ CYCLE
MATCH
t
SPS
A0L–A
2L
MATCH
R/W
L
SEM
L
A0R–A
2R
R/W
R
SEM
R
Notes
25. Data I/O pins enter high impedance when OE
is held LOW during write.
26. CE
= HIGH for the duration of the above timing (both write and read cycle).
Figure 9. Timing Diagram of Semaphore Contention
Document #: 38-06037 Rev. *D Page 9 of 17
Figure 10. Timing Diagram of Read with BUSY (M/S = HIGH)
[27, 28, 29]
[21]
[+] Feedback
CY7C138, CY7C139
Switching Waveforms (continued)
VAL ID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VAL ID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
t
PWE
R/W
BUSY
t
WB
t
WH
Figure 11. Write Timing with Busy Input (M/S=LOW)
[30]
Notes
27. I/O
= I/O0L = LOW (request semaphore); CER = CEL = HIGH
0R
28. Semaphores are reset (available to both ports) at cycle start.
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
29. If t
SPS
Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)
Document #: 38-06037 Rev. *D Page 10 of 17
[+] Feedback
CY7C138, CY7C139
Switching Waveforms (continued)
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
ADDRESS
L,R
BUSY
R
CE
L
CE
R
BUSY
L
CE
R
CE
L
ADDRESS
L,R
CEL Val i d F i rst:
CE
R
Valid First:
ADDRESS MATCH
t
PS
ADDRESS
L
BUSY
R
ADDRESS MISMATCH
t
RC
or t
WC
t
BLA
t
BHA
ADDRESS
R
ADDRESS MATCH ADDRESS MISMATCH
t
PS
ADDRESS
L
BUSY
L
tRCor t
WC
t
BLA
t
BHA
ADDRESS
R
Left Address Valid First:
Right Address Valid First:
Note
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
30. If t
PS
Document #: 38-06037 Rev. *D Page 11 of 17
Figure 13. Busy Timing Diagram No. 2 (Address Arbitration)
[30]
[+] Feedback
CY7C138, CY7C139
Switching Waveforms (continued)
WRITE FFF
t
WC
t
HA
READ FFF
t
RC
t
INR
WRITE FFE
t
WC
READ FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
Left Side Sets INTR:
Right Side Clears INT
R
:
Right Side Sets INT
L
:
Left Side Clears INTL:
[31]
[31]
[32]
[32]
[32]
[32]
Figure 14. Interrupt Timing Diagrams
Notes
depends on which enable pin (CEL or R/WL) is deasserted first.
31. t
HA
or t
32. t
INS
Document #: 38-06037 Rev. *D Page 12 of 17
depends on which enable pin (CEL or R/WL) is asserted last.
INR
[+] Feedback
CY7C138, CY7C139
Architecture
The CY7C138/9 consists of an array of 4K words of 8/9 bits each
of dual-port RAM cells, I/O and address lines, and control signals
, OE, R/W). These control pins permit independent access
(CE
for reads or writes to any location in memory. To handle simultaneous writes and reads to the same location, a BUSY
provided on each port. Two interrupt (INT
) pins can be used for
port–to–port communication. Two semaphore (SEM
pins are used for allocating shared resources. With the M/S
the CY7C138/9 can function as a master (BUSY
outputs) or as a slave (BUSY
pins are inputs). The CY7C138/9
has an automatic power down feature controlled by CE
port is provided with its own output enable control (OE
pin is
) control
pin,
pins are
. Each
), which
enables data to be read from the device.
Functional Description
Write Operation
Data must be set up for a duration of tSD before the rising edge
of R/W
in order to guarantee a valid write. A write operation is
controlled by either the OE
or the R/W
pin (see Write Cycle No. 2 waveform). Data can be
written to the device t
after the falling edge of R/W. Required inputs for non-contention
operations are summarized in Table 3.
If a location is being written to by one port and the opposite port
attempts to read that location, a port-to-port flowthrough delay
must be met before the data is read on the output; otherwise the
data read is not deterministic. Data is valid on the port t
the data is presented on the other port.
Read Operation
When reading the device, the user must assert both the OE and
CE
pins. Data is available t
asserted. If the user of the CY7C138/9 wishes to access a
semaphore flag, then the SEM pin must be asserted instead of
the CE
pin.
Interrupts
The interrupt flag (INT) permits communications between
ports.When the left port writes to location FFF, the right port’s
interrupt flag (INT
reads that same location. Setting the left port’s interrupt flag
) is set. This flag is cleared when the right port
R
(INTL) is accomplished when the right port writes to location FFE.
This flag is cleared when the left port reads location FFE. The
message at FFF or FFE is user-defined. See Table 4 for input
requirements for INT
do not require pull-up resistors to operate. BUSY
in master mode are push-pull outputs and do not require pull-up
resistors to operate.
Busy
The CY7C138/9 provides on-chip arbitration to alleviate simultaneous memory location access (contention). If both ports’ CE
are asserted and an address match occurs within t
other the Busy logic determines which port has access. If t
violated, one port definitely gains permission to the location, but
it is not guaranteed which one. BUSY
an address match or t
pin (see Write Cycle No. 1 waveform)
after the OE is deasserted or t
HZOE
after CE or t
ACE
DOE
HZWE
after
DDD
after OE is
. INTR and INTL are push-pull outputs and
and BUSY
L
of each
will be asserted t
after CE is taken LOW.
BLC
PS
BLA
is
PS
after
Master/Slave
A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY
of the master is connected to the BUSY
input of the slave. This
enables the device to interface to a master device with no
external components.Writing of slave devices must be delayed
until after the BUSY
input has settled. Otherwise, the slave chip
may begin a write cycle during a contention situation.When
presented as a HIGH input, the M/S
used as a master and therefore the BUSY
BUSY
can then be used to send the arbitration outcome to a
pin allows the device to be
line is an output.
slave.
Semaphore Operation
The CY7C138/9 provides eight semaphore latches, which are
separate from the dual-port memory locations. Semaphores are
used to reserve resources that are shared between the two
ports.The state of the semaphore indicates that a resource is in
use. For example, if the left port wants to request a given
resource, it sets a latch by writing a zero to a semaphore location.
The left port then verifies its success in setting the latch by
reading it. After writing to the semaphore, SEM
deasserted for t
The semaphore value is available t
edge of the semaphore write. If the left port was successful
before attempting to read the semaphore.
SOP
SWRD
(reads a zero), it assumes control over the shared resource,
otherwise (reads a one) it assumes the right port has control and
continues to poll the semaphore.When the right side has relinquished control of the semaphore (by writing a one), the left side
succeeds in gaining control of the a semaphore.If the left side no
longer requires the semaphore, a 1 is written to cancel its
request.
Semaphores are accessed by asserting SEM
pin functions as a chip enable for the semaphore latches (CE
must remain HIGH during SEM LOW). A
semaphore address. OE
and R/W are used in the same manner
as a normal memory access. When writing or reading a
semaphore, the other address pins have no effect.
When writing to the semaphore, only I/O
written to the left port of an unused semaphore, a one will appear
at the same semaphore address on the right port. That
semaphore can now only be modified by the side showing zero
(the left port in this case). If the left port now relinquishes control
by writing a one to the semaphore, the semaphore is set to 1 for
both sides. However, if the right port had requested the
semaphore (written a zero) while the left port had control, the
right port immediately owns the semaphore after the left port
releases it. Ta bl e 5 shows sample semaphore operations.
R
When reading a semaphore, all eight or nine data lines output
the semaphore value. The read value is latched in an output
register to prevent the semaphore from changing state during a
write from the other port. If both ports attempt to access the
semaphore within t
obtained by one side or the other, but there is no guarantee which
s
side controls the semaphore.
of each other, the semaphore is definitely
SPS
Initialization of the semaphore is not automatic and must be reset
during initialization program at power up. All semaphores on both
sides should have a 1 written into them at initialization from both
sides to assure that they are free when needed.
or OE must be
+ t
after the rising
DOE
LOW. The SEM
represents the
0–2
is used. If a zero is
0
output
Document #: 38-06037 Rev. *D Page 13 of 17
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CY7C138, CY7C139
Table 3. Non-Contending Read/Write
Inputs Outputs
CE R/W OE SEM I/O
0-7/8
Operation
H X X H High Z Power-Down
H H L L Data Out Read Data in Semaphore
X X H X High Z I/O Lines Disabled
H X L Data In Write to Semaphore
L H L H Data Out Read
L L X H Data In Write
L X X L Illegal Condition
Table 4. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)
Left Port Right Port
Function R/W CE OE A
INT R/W CE OE A
0-11
0-11
Set Left INT X X X X L L L X FFE X
Reset Left INT X L L FFE H X X X X X
Set Right INT L L X FFF X X X X X L
Reset Right INT X X X X X X L L FFF H
Table 5. Semaphore Operation Example
Function I/O
0-7/8
Left I/O
Right Status
0-7/8
No action 1 1 Semaphore free
Left port writes semaphore 0 1 Left port obtains semaphore
Right port writes 0 to semaphore 0 1 Right side is denied access
Left port writes 1 to semaphore 1 0 Right port is granted access to semaphore
Left port writes 0 to semaphore 1 0 No change. Left port is denied access
Right port writes 1 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No port accessing semaphore address
Right port writes 0 to semaphore 1 0 Right port obtains semaphore
Right port writes 1 to semaphore 1 1 No port accessing semaphore
Left port writes 0 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No port accessing semaphore
INT
Document #: 38-06037 Rev. *D Page 14 of 17
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CY7C138, CY7C139
Figure 15. Typical DC and AC Characteristics
1.4
1.0
0.4
4.0 4.5 5.0 5.5 6.0
–55 25 125
1.2
1.0
120
80
0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.0
0.8
0.8
0.6
0.6
NORMALIZED I
CC
, I
SB
V
CC
= 5.0V
V
IN
= 5.0V
0
I
CC
1.6
1.4
1.2
1.0
0.8
–55 125
NORMALIZED t
AA
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
1.4
1.3
1.2
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
AA
SUPPLY VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
120
140
100
60
40
20
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
80
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
V
CC
= 5.0V
0.6
0.8
1.25
1.0
0.75
10
NORMALIZED I
CC
0.50
NORMALIZED I
CC
vs. CYCLE TIME
CYCLE FREQUENCY (MHz)
1.00
0.25
0 1.0 2.0 3.0 5.0
NORMALIZED t
PC
25.0
30.0
20.0
10.0
5.0
0 200 400 600 800
DELTA t
AA
(ns)
0
15.0
0.0
SUPPLY VOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0
1000
0.50
28
0.2
0.6
1.2
I
SB3
NORMALIZED I,
CC
I
SB
0.2
0.4
25
1.1
5.0
T
A
= 25°C
40
160
200
5.0
40
66
0.75
I
CC
I
SB3
V
CC
= 5.0V
T
A
= 25°C
T
A
= 25°C
V
CC
= 5.0V
V
CC
= 4.5V
T
A
= 25°C
T
A
= 25°C
V
CC
= 5.0V
V
IN
= 5.0V
V
IN
= 5.0V
Document #: 38-06037 Rev. *D Page 15 of 17
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CY7C138, CY7C139
Ordering Information
51-85005-*A
4K x8 Dual-Port SRAM
Speed
(ns)
15 CY7C138-15JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
25 CY7C138-25JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
35 CY7C138-35JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
55 CY7C138-55JC J81 68-Lead Plastic Leaded Chip Carrier Commercial
Ordering Code
CY7C138-15JXC J81 68-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C138-25JXC J81 68-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C138-25JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
CY7C138-25JXI J81 68-Lead Pb-Free Plastic Leaded Chip Carrier
CY7C138-35JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
CY7C138-55JI J81 68-Lead Plastic Leaded Chip Carrier Industrial
Package
Name
Package Type
Package Diagram
Figure 16. 68-Pin Plastic Leaded Chip Carrier J81 (51-85005)
Operating
Range
Document #: 38-06037 Rev. *D Page 16 of 17
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CY7C138, CY7C139
Document History Page
Document Title: CY7C138/CY7C139 4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
Document Number: 38-06037
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 110180 SZV 09/29/01 Change from Spec number: 38-00536 to 38-06037
*A 122287 RBI 12/27/02 Power up requirements added to Maximum Ratings Information
*B 393403 YIM See ECN Added Pb-Free Logo
Added Pb-Free parts to ordering information:
CY7C138-15JXC, CY7C138-25JXC, CY7C139-25JXC
*C 2623658 VKN/PYRS 12/17/08 Added CY7C138-25JXI part
Removed CY7C139 from the Ordering information table
*D 2672737 GNKK 03/12/2009 Updated title in the Document History table
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Document #: 38-06037 Rev. *D Revised March 12, 2009 Page 17 of 17
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