Cypress CY7C139, CY7C138 User Manual

CY7C138, CY7C139

4K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

Features

Logic Block Diagram

Functional Description

■ True Dual-Ported memory cells that enable simultaneous reads

of the same memory location

■ 4K x 8 organization (CY7C138)

■ 4K x 9 organization (CY7C139)

■ 0.65-micron CMOS for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: I

■ Fully asynchronous operation

■ Automatic power down

■ TTL compatible

■ Expandable data bus to 32/36 bits or more using

= 160 mA (max.)

CC

Master/Slave chip select when using more than one
device

■ On-chip arbitration logic

■ Semaphores included to permit software handshaking

between ports

■ INT flag for port-to-port communication

■ Available in 68-pin PLCC

■ Pb-free packages available

The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and
4K x 9 dual-port static RAMs. Various arbitration schemes are
included on the CY7C138/9 to handle situations when multiple
processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C138/9 can
be used as a standalone 8/9-bit dual-port static RAM or multiple
devices can be combined to function as a 16/18-bit or wider
master/slave dual-port static RAM. An M/S

pin is provided for
implementing 16/18-bit or wider memory applications without the
need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multipro­cessor designs, communications status buffering, and dual-port
video/graphics memory.

Each port has independent control pins: chip enable (CE
or write enable (R/W
provided on each port (BUSY

), and output enable (OE). Two flags are

and INT). BUSY signals that the

), read

port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power down feature is controlled independently on
each port by a chip enable (CE

) pin or SEM pin.

The CY7C138 and CY7C139 are available in a 68-pin PLCC.

Notes

1. BUSY

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06037 Rev. *D Revised March 12, 2009

is an output in master mode and an input in slave mode.

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CY7C138, CY7C139

Pin Configurations

10

11

12
13

14

15
16

17
18

19

20

21
22

23

24

67

60

59

58
57

56

55
54

53
52

51

50
49

48

3132 33 34 35 36 37 38 39 40 41 42 43

5 4 3 2 168 666564636261

A

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

BUSY

L

GND

M/S
BUSY

R

INT

R

A

0R

I/O

2L

I/O

3L

I/O

4L

I/O

5L

GND

I/O

6L

I/O

7L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

V

CC

A

2728 29 30

98 7 6

47

46
45

44

A

1R

A

2R

A

3R

A

4R

I/O

3R

I/O

4R

I/O

5R

I/O

6R

25

26

6L

7LA8LA9L

A

A

10L

11L

V

CC

NC

NC

CE

L

SEM

L

R/WLOE

L

NC

I/O

I/O

1L

0L

A

A

6R

7RA8RA9R

A

10R

NC

NC

CE

R

SEM

R

R/W

R

OE

R

I/O

7R

GND

A

11R

A

5R

A

5L

NC

CY7C138/9

[3]

[4]

NC

NC

\

Figure 1. 68-Pin PLCC (Top View)

Table 1. Pin Definitions

Left Port Right Port Description

I/O

0L–7L(8L)

A

0L–11L

CE

L

OE

L

R/W

L

SEML SEM

I/O

0R–7R(8R)

A

0R–11R

CE

R

OE

R

R/W

Data Bus Input/Output
Address Lines
Chip Enable
Output Enable

R

R

Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight

semaphores. The three least significant bits of the address lines will
determine which semaphore to write or read. The I/O
writing to a semaphore. Semaphores are requested by writing a 0 into the

pin is used when

0

respective location.

INT

L

BUSY

L

M/S Master or Slave Select
V

CC

GND Ground

Table 2. Selection Guide

Maximum Access Time (ns) 15 25 35 55 ns
Maximum Operating Current Commercial 220 180 160 160 mA
Maximum Standby Current for I

Notes

3. I/O

4. I/O

Document #: 38-06037 Rev. *D Page 2 of 17

on the CY7C139.

8R

on the CY7C139.

8L

INT

BUSY

Description

R

R

Interrupt Flag. INTL is set when right port writes location FFE and is cleared
when left port reads location FFE. INT
FFF and is cleared when right port reads location FFF.

is set when left port writes location

R

Busy Flag

Power

SB1

Commercial 60 40 30 30 mA

7C138-15
7C139-15

7C138-25
7C139-25

7C138-35
7C139-35

7C138-55
7C139-55

Unit

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CY7C138, CY7C139

Maximum Ratings

Notes

5. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.

6. Pulse width < 20 ns.

7. f

MAX

= 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level

standby I

SB3

.

Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied ............................................ –55°C to +125°C

Supply Voltage to Ground Potential................–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State................................................–0.5V to +7.0V

DC Input Voltage

[6]

.........................................–0.5V to +7.0V

[5]

Electrical Characteristics Over the Operating Range

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current.................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

Ambient

Tem per atur e

V

CC

Parameter Description Test Conditions

V

V

V

V

I

I

I

I

I

I

I

OH

OL

IH

IL

IX

OZ

CC

SB1

SB2

SB3

SB4

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

Input LOW Voltage 0.8 0.8 V

Input Leakage Current GND < VI < V

CC

Output Leakage Current Output Disabled, GND < VO < V

Operating Current VCC = Max.,

I

= 0 mA,

OUT

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS Levels)

Standby Current
(One Port CMOS Level)

CEL and CER > VIH,
f = f

CEL and CER > VIH,
f = f

MAX

MAX

[7]

[7]

Both Ports

and CER > VCC – 0.2V,

CE
V

> VCC – 0.2V

IN

or V

IN

< 0.2V, f = 0

[7]

One Port
CE

or CER > VCC – 0.2V,

L

V

> VCC – 0.2V or

IN

< 0.2V, Active

V

IN

Port Outputs, f = f

MAX

[7]

7C138-15
7C139-15

7C138-25
7C139-25

Unit

Min Max Min Max

2.2 2.2 V

–10 +10 –10 +10 μA

CC

–10 +10 –10 +10 μA

Commercial 220 180 mA

Industrial 190

Commercial 60 40 mA

Industrial 50

Commercial 130 110 mA

Industrial 120

Commercial 15 15 mA

Industrial 30

Commercial 125 100 mA

Industrial 115

Document #: 38-06037 Rev. *D Page 3 of 17

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CY7C138, CY7C139

Electrical Characteristics Over the Operating Range (continued)

Parameter Description Test Conditions

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

Capacitance

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V

Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

Input LOW Voltage 0.8 0.8 V

Input Leakage Current GND < VI < V

CC

Output Leakage Current Output Disabled, GND < VO < V

Operating Current VCC = Max.,

I

= 0 mA,

OUT

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS Levels)

Standby Current
(One Port CMOS Level)

[8]

CEL and CER > VIH,
f = f

CEL and CER > VIH,
f = f

MAX

MAX

[7]

[7]

Both Ports

and CER > VCC – 0.2V,

CE
V

> VCC – 0.2V

IN

or V

IN

< 0.2V, f = 0

[7]

One Port
CE

or CER > VCC – 0.2V,

L

V

> VCC – 0.2V or

IN

< 0.2V, Active

V

IN

Port Outputs, f = f

MAX

[7]

7C138-35
7C139-35

7C138-55
7C139-55

Unit

Min Max Min Max

2.2 2.2 V

–10 +10 –10 +10 μA

CC

–10 +10 –10 +10 μA

Commercial 160 160 mA

Industrial 180 180

Commercial 30 30 mA

Industrial 40 40

Commercial 100 100 mA

Industrial 110 110

Commercial 15 15 mA

Industrial 30 30

Commercial 90 90 mA

Industrial 100 100

Parameter Description Test Conditions Max Unit

C

C

IN

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 5.0V

Output Capacitance 15 pF

CC

10 pF

Document #: 38-06037 Rev. *D Page 4 of 17

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CY7C138, CY7C139

Figure 2. AC Test Loads and Waveforms

3.0V

GND

90%

90%

10%

<

3ns

< 3 ns

10%

ALL INPUT PULSES

(a) Normal Load (Load 1)

R1 = 893Ω

5V

OUTPUT

R2 = 347Ω

C= 30

pF

R

TH

= 250Ω

V

TH

= 1.4V

OUTPUT

C = 30pF

(b) Thé venin Equivalent(Load 1)

(c) Three-State Delay (Load 3)

C= 30pF

OUTPUT

Load (Load 2)

R1 = 893Ω

R2 = 347Ω

5V

OUTPUT

C= 5pF

Note

8. Tested initially and after any design or process changes that may affect these parameters.

Switching Characteristics Over the Operating Range

Parameter Description

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

[10,11,12]

t

LZOE

[10,11,12]

t

HZOE

[10,11,12]

t

LZCE

[10,11,12]

t

HZCE

[12]

t

PU

[12]

t

PD

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

[9]

7C138-15
7C139-15

7C138-25
7C139-25

7C138-35
7C139-35

7C138-55
7C139-55

Min Max Min Max Min Max Min Max

Read Cycle Time 15 25 35 55 ns

Address to Data Valid 15 25 35 55 ns

Output Hold From Address Change 3 3 3 3 ns

CE LOW to Data Valid 15 25 35 55 ns

OE LOW to Data Valid 10 15 20 25 ns

OE Low to Low Z 3 3 3 3 ns

OE HIGH to High Z 10 15 20 25 ns

CE LOW to Low Z 3 3 3 3 ns

CE HIGH to High Z 10 15 20 25 ns

CE LOW to Power-Up 0 0 0 0 ns

CE HIGH to Power-Down 15 25 35 55 ns

Write Cycle Time 15 25 35 55 ns

CE LOW to Write End 12 20 30 40 ns

Address Set-Up to Write End 12 20 30 40 ns

Address Hold From Write End 2 2 2 2 ns

Address Set-Up to Write Start 0 0 0 0 ns

Write Pulse Width 12 20 25 30 ns

Data Set-Up to Write End 10 15 15 20 ns

Unit

Document #: 38-06037 Rev. *D Page 5 of 17

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CY7C138, CY7C139

Switching Characteristics Over the Operating Range

Notes

9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OI/IOH

and 30-pF load capacitance.

10. At any given temperature and voltage condition for any given device, t

HZCE

is less than t

LZCE

and t

HZOE

is less than t

LZOE

.

11. Test conditions used are Load 3.

12. This parameter is guaranteed but not tested.

13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.

14. Test conditions used are Load 2.

15. t

BDD

is a calculated parameter and is the greater of t

WDD

– t

PWE

(actual) or t

DDD

– tSD (actual).

t

RC

t

AA

t

OHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

[9]

(continued)

Parameter Description

t

HD

[11,12]

t

HZWE

[11,12]

t

LZWE

[13]

t

WDD

[13]

t

DDD

BUSY TIMING

t

BLA

t

BHA

t

BLC

t

BHC

t

PS

t

WB

t

WH

[15]

t

BDD

INTERRUPT TIMING

t

INS

t

INR

Data Hold From Write End 0 0 0 0 ns

R/W LOW to High Z 10 15 20 25 ns

R/W HIGH to Low Z 3 3 3 3 ns

Write Pulse to Data Delay 30 50 60 70 ns

Write Data Valid to Read Data Valid 25 30 35 40 ns

[14]

BUSY LOW from Address Match 15 20 20 45 ns

BUSY HIGH from Address Mismatch 15 20 20 40 ns

BUSY LOW from CE LOW 15 20 20 40 ns

BUSY HIGH from CE HIGH 15 20 20 35 ns

Port Set-Up for Priority 5 5 5 5 ns

R/W LOW after BUSY LOW 0 0 0 0 ns

R/W HIGH after BUSY HIGH 13 20 30 40 ns

BUSY HIGH to Data Valid Note 15 Note 15 Note 15 Note 15 ns

[14]

INT Set Time 15 25 25 30 ns

INT Reset Time 15 25 25 30 ns

SEMAPHORE TIMING

t

SOP

t

SWRD

t

SPS

SEM Flag Update Pulse (OE or SEM) 10 10 15 20 ns

SEM Flag Write to Read Time 5 5 5 5 ns

SEM Flag Contention Window 5 5 5 5 ns

7C138-15
7C139-15

7C138-25
7C139-25

7C138-35
7C139-35

7C138-55
7C139-55

Min Max Min Max Min Max Min Max

Unit

Switching Waveforms

Figure 3. Read Cycle No. 1 (Either Port Address Access)

Figure 4. Read Cycle No. 2 (Either Port CE/OE Access)

Document #: 38-06037 Rev. *D Page 6 of 17

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