Cypress CY7C1387FV25, CY7C1386DV25, CY7C1386FV25, CY7C1387DV25 User Manual
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
•2.5V +
• Fast clock-to-output times, 2.6 ns (for 250 MHz device)
• Provides high-performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel
• Separate processor and controller address strobes
• Synchronous self timed writes
• Asynchronous output enable
• CY7C1386DV25/CY7C1387DV25 available in
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
5% power supply (VDD)
®
Pentium®
interleaved or linear burst sequences
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1386FV25/CY7C1387FV25 available in Pb-free and
non Pb-free 119-ball BGA package
Functional Description
[1]
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 SRAM integrates 512K x 36 and 1M x 18
SRAM cells with advanced synchronous peripheral circuitry
and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE
[2]
), burst control inputs (ADSC, ADSP, and ADV), write
CE
3
enables (BW
Asynchronous inputs include the output enable (OE
), depth expansion chip enables (CE2 and
1
, and BWE), and global write (GW).
X
) and the
ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP
address strobe controller (ADSC
) are active. Subsequent
) or
burst addresses can be internally generated as controlled by
the advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Truth Table
5, 6, 7, 8, 9]
on page 9 for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
inputs. GW
active
causes all bytes to be written.
LOW
This
device incorporates an additional pipelined enable register
which delays turning off the output buffers an additional cycle
when a deselect is executed.This feature allows depth
expansion without penalizing system performance.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 operates from a +2.5V power supply. All
inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
[4,
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.0 3.4 ns
Maximum Operating Current 350 300 275 mA
Maximum CMOS Standby Current 70 70 70 mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 38-05548 Rev. *E Revised Feburary 15, 2007
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
3, CE2
[+] Feedback
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Logic Block Diagram – CY7C1386DV25/CY7C1386FV25
DQD,DQP
BYTE
DQc,DQP
BYTE
DQB,DQP
BYTE
DQA,DQP
BYTE
ENABLE
REGISTER
CONTROL
ADDRESS
REGISTER
D
C
B
A
2
BURST
COUNTER AND
LOGIC
CLR
PIPELINED
ENABLE
A[1:0]
Q1
Q0
DQD,DQP
D
BYTE
WRITE DRIVER
DQc,DQP
C
BYTE
WRITE DRIVER
DQB,DQP
B
BYTE
WRITE DRIVER
DQA,DQP
A
BYTE
WRITE DRIVER
A0,A1,A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BW
BW
BWE
GW
D
C
B
A
CE
1
CE
2
CE
3
OE
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
ZZ
[3]
(512K x 36)
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
DQP
DQP
A
B
C
D
Logic Block Diagram – CY7C1387DV25/CY7C1387FV25
A0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BWE
B
A
CE
1
CE
2
CE
3
OE
ADDRESS
REGISTER
DQB,DQP
B
BYTE
WRITE REGISTER
A ,
DQ
DQP
BYTE
WRITE REGISTER
ENABLE
REGISTER
SLEEP
CONTROL
2
BURST
COUNTER AND
CLR
PIPELINED
ENABLE
[1:0]
A
Q1
Q0
DQ
B ,
DQP
B
BYTE
DQA,DQP
A
BYTE
[3]
(1M x 18)
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQ
DQP
DQP
s,
A
B
Note
3. CY7C1386FV25 and CY7C1387FV25 have only 1 chip enable (CE
).
1
Document Number: 38-05548 Rev. *E Page 2 of 30
[+] Feedback
Pin Configurations
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
100-pin TQFP Pinout (3 Chip Enables)
DQP
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQP
DDQ
SSQ
SSQ
DDQ
V
V
DDQ
SSQ
SSQ
DDQ
NC
NC
1CE2
A
A
CE
100999897969594939291908988878685848382
C
1
C
2
C
3
4
5
C
6
C
7
C
8
C
9
10
11
C
12
C
13
14
DD
15
16
SS
17
D
18
D
19
20
21
D
22
D
23
D
24
D
25
26
27
D
28
D
29
D
30
31323334353637383940414243444546474849
AAA
MODE
A
BWDBWCBWBBW
CE3VDDV
CY7C1386DV25
(512K X 36)
1A0
A
A
SS
V
NC/72M
NC/36M
SS
CLKGWBWEOEADSC
A
A
AAAAA
DD
V
ADSP
ADV
A
A
81
DQP
80
DQ
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
NC
B
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
A
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1387DV25
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
SS
CE3VDDV
(1M x 18)
SS
DD
V
V
NC/72M
NC/36M
CLKGWBWEOEADSC
A
A
ADSP
AAAAA
ADV
A
A
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
50
A
A
Document Number: 38-05548 Rev. *E Page 3 of 30
[+] Feedback
Pin Configurations (continued)
V
A
NC/288M
B
NC/144M
C
D
G
H
K
M
N
R
U
DQ
DQ
E
V
F
DQ
DQ
V
J
DQ
DQ
L
V
DQ
DQ
P
NC
T
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
119-Ball BGA (1 Chip Enable)
CY7C1386FV25 (512K x 36)
2345671
AA AA
A
A
AA
DQP
C
DQ
C
DQ
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
DQ
D
DQP
D
A
V
C
C
C
C
C
V
V
BW
V
SS
SS
SS
SS
NC V
V
BW
V
V
V
SS
SS
SS
SS
D
D
D
D
D
MODE
AAA
ADSP
ADSC
V
NC
CE
OE
ADV
C
GW
CLK
D
NC
BWE
V
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
V
DDQ
NC/576M
DQP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQP
NC/36MNC/72M
V
NC
A
AA
DD
A
NC/1G
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
B
B
DDQ
B
B
DDQ
A
A
DDQ
A
A
B
B
B
B
B
A
A
A
A
A
NC
ZZ
V
DDQ
A1
A0
DD
DD
DD
A
V
SS
V
1
V
BW
V
SS
SS
B
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
TDOTCKTDITMS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC/72M
V
DDQ
CY7C1387FV25 (1M x 18)
2
AA AA
A
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
A
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
NC
V
SS
V
SS
V
SS
MODE
ADSC
V
DD
NC
CE
1
OE
ADV
B
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A NC/36M A
V
V
V
NC
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
A
SS
SS
SS
SS
SS
SS
SS
SS
A
AA
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DDQ
NC/576M
NC/1G
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document Number: 38-05548 Rev. *E Page 4 of 30
[+] Feedback
Pin Configurations (continued)
234 5671
NC/288M
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
NC/72M
NC/36M
CE
CE
V
DDQ
V
C
C
C
C
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
D
D
D
D
A
A
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1386DV25 (512K x 36)
BW
1
BW
2
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
C
BW
D
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
CE
B
CLK
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
891011
ADSC
ADV
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC/1G DQP
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
NC
NC/576M
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1387DV25 (1M x 18)
234 5671
NC/288M
NC/144M
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
2
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
‘V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
891011
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
ADSC
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC/1G DQP
NC
NC
NC
NC
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
NC/576M
DQ
A
DQ
A
DQ
A
DQ
A
ZZ
NCV
NC
NC
NC
NC
A
AA
A
Document Number: 38-05548 Rev. *E Page 5 of 30
[+] Feedback
Pin Definitions
Name IO Description
, A1, A Input-
A
0
BW
, BW
A
BWC, BW
B
D
GW Input-
BWE
CLK Input-
CE
1
[2]
CE
2
[2]
CE
3
OE Input-
ADV Input-
ADSP Input-
ADSC
ZZ Input-
DQs, DQPs
V
DD
Synchronous
Input-
Synchronous
Synchronous
Input-
Synchronous
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Asynchronous
Synchronous
Synchronous
Input-
Synchronous
Asynchronous
IO-
Synchronous
Power Supply Power supply inputs to the core of the device.
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Address inputs used to select one of the address locations. Sampled at the
rising edge of the CLK if ADSP
are sampled active. A1: A0 are fed to the two-bit counter.
or ADSC is active LOW, and CE1, CE2, and CE
.
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (all bytes are written, regardless of the values
on BW
and BWE).
X
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV
is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
if CE
is HIGH. CE1 is sampled only when a new external address is loaded.
1
and CE
2
[2]
to select or deselect the device. ADSP is ignored
3
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
and CE
1
[2]
to select or deselect the device. CE2 is sampled
3
only when a new external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
BGA. Where referenced, CE
and CE2 to select or deselect the device. Not connected for
1
[2]
is assumed active throughout this document for
3
BGA. CE3 is sampled only when a new external address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the
IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, DQ
pins are tri-stated, and act as input data pins. OE
is masked during the first clock
of a read cycle when emerging from a deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP
ADSC
are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Address strobe from controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP
ADSC
are both asserted, only ADSP is recognized.
ZZ sleep input, active HIGH. When asserted HIGH places the device in a
non-time-critical sleep condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull down.
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE
. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are
placed in a tri-state condition.
3
and
and
[2]
Document Number: 38-05548 Rev. *E Page 6 of 30
[+] Feedback
CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
Pin Definitions (continued)
Name IO Description
V
SS
V
SSQ
V
DDQ
MODE Input-
TDO JTAG serial output
TDI JTAG serial input
TMS JTAG serial input
TCK JTAG-
NC – No Connects. Not internally connected to the die
NC/(36M, 72M, 144M,
288M, 576M, 1G)
Ground Ground for the core of the device.
IO Ground Ground for the IO circuitry.
IO Power Supply Power supply for the IO circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied
Stat ic
to VDD or left floating selects interleaved burst sequence. This is a strap pin and
must remain static during device operation. Mode pin has an internal pull up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
If the JTAG feature is not used, this pin must be disconnected. This pin is not
available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be disconnected or connected to V
not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be disconnected or connected to V
not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must
Clock
be connected to V
. This pin is not available on TQFP packages.
SS
– These pins are not connected. They will be used for expansion to the 36M, 72M,
144M, 288M, 576M, and 1G densities.
. This pin is
DD
. This pin is
DD
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 supports secondary cache in systems using
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium
linear burst sequence is suited for processors that use a linear
burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can
initiated with either the processor address strobe (ADSP)
the controller address strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
) and byte write select (BWX) inputs. A global write
(BWE
enable (GW
) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
Synchronous chip selects CE
asynchronous output enable (OE) provide for easy bank
selection and
output tri-state control.
is HIGH.
®
and i486™ processors. The
). Address advancement
input. A
, CE2, CE
1
ADSP
[2]
and an
3
is ignored if CE
be
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the address
register while being presented to the memory core. The
corresponding data is allowed to propagate to the input of the
output registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
occurs when the SRAM is emerging from a deselected state
or
if OE is active LOW. The only exception
CO
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE
signal. Consecutive single
read cycles are supported.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 is a double-cycle deselect part. Once the
SRAM is deselected at clock rise by the chip select and either
or ADSC signals, its output will tri-state immediately
ADSP
after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
1
chip select is asserted active. The address presented is
is asserted LOW, and (2)
loaded into the address register and the address
advancement logic while being delivered to the memory core.
1
Document Number: 38-05548 Rev. *E Page 7 of 30
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CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
The write signals (GW
ignored during this first cycle.
triggered write accesses require two clock cycles to
ADSP
, BWE, and
) and ADV inputs are
BW
X
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
corresponding address location in the memory core. If GW
inputs is written into the
x
is
HIGH, then the write operation is controlled by BWE and BW
signals.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 provides byte write capability that is
described in the write cycle description table. Asserting the
byte write enable input (BWE
) with the selected byte write
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 is a common IO device, the output enable
) must be deasserted HIGH before presenting data to the
(OE
inputs. Doing so will tri-state the output drivers. As a safety
DQ
precaution, DQ are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following
conditions are satisfied: (1) ADSC
is asserted LOW, (2) ADSP
is deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and
byte(s). ADSC triggered write accesses require a single clock
) are asserted active to conduct a write to the desired
BW
X
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV
input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQ
is written into the corresponding address
X
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous self
timed write mechanism has been provided to simplify the write
operations.
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 is a common IO device, the output enable
) must be deasserted HIGH before presenting data to the
(OE
inputs. Doing so will tri-state the output drivers. As a
DQ
X
safety precaution, DQ
are automatically tri-stated whenever
X
a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/
CY7C1387FV25 provides a two-bit wraparound counter, fed
by A
, that implements either an interleaved or linear burst
[1:0]
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow
X
a linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV
LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
for the duration of t
s, ADSP, and ADSC must remain inactive
after the ZZ input returns LOW
ZZREC
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
Third
Address
A1: A0
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
.
Fourth
Address
A1: A0
Fourth
Address
A1: A0
Document Number: 38-05548 Rev. *E Page 8 of 30
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CY7C1386DV25, CY7C1386FV25
CY7C1387DV25, CY7C1387FV25
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D
Sleep mode standby current ZZ > VDD – 0.2V 80 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[4, 5, 6, 7, 8, 9]
ns
ns
ns
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE
6. The DQ pins are controlled by the current cycle and the
7. CE
8. The SRAM always initiates a read cycle when ADSP
9. OE
= L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
1
the ADSP
care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
signal. OE is asynchronous and is not sampled with the clock.
OE
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
Document Number: 38-05548 Rev. *E Page 9 of 30
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