Cypress CY7C1383FV25, CY7C1381FV25, CY7C1381DV25, CY7C1383DV25 User Manual
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
• Supports 133 MHz bus operations
• 512K x 36/1M x 18 common IO
• 2.5V core power supply (V
• 2.5V IO supply (V
DDQ
• Fast clock-to-output times, 6.5 ns (133 MHz version)
• Provides high-performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1381DV25/CY7C1383DV25 available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 165-ball FBGA package.
CY7C1381FV25/CY7C1383FV25 available in Pb-free and
non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
)
DD
)
®
Pentium®
Functional Description
[1]
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 is a 2.5V, 512K x 36 and 1M x 18
synchronous flow through SRAMs, designed to interface with
high-speed microprocessors with minimum glue logic.
Maximum access delay from clock rise is 6.5 ns (133 MHz
version). A 2-bit on-chip counter captures the first address in
a burst and increments the address automatically for the rest
of the burst access. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE
chip enables (CE2 and CE
[2]
), burst control inputs (ADSC,
3
), depth expansion
1
ADSP, and ADV), write enables (BWx, and BWE), and global
write (GW
). Asynchronous inputs include the output enable
(OE) and the ZZ pin.
The
CY7C1383FV25
CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
) or the cache controller address strobe
address strobe
(ADSP
(ADSC) inputs. Address advancement is controlled by the
address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP
) or
address strobe controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the advance pin (ADV
).
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 operates from a +2.5V core power supply
while all outputs also operate with a +2.5 supply. All inputs and
outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 210 175 mA
Maximum CMOS Standby Current 70 70 mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05547 Rev. *E Revised Feburary 14, 2007
are for TQFP and 165 FBGA package only. 119 BGA is offered only in 1 chip enable.
3, CE2
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Logic Block Diagram – CY7C1381DV25/CY7C1381FV25
A0, A1, A
MODE
ADSC
ADSP
BW
BWE
ADV
BW
BW
CLK
D
C
BW
B
A
GW
CE1
CE2
CE3
OE
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
WRITE REGISTER
SLEEP
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
D
D
,
DQP
DQ
BYTE
BYTE
C
C
DQ
,
DQP
B
B
DQ
,
DQP
A
A
DQ
,
DQP
BYTE
ENABLE
REGISTER
[1:0]
A
Q1
Q0
DQ
WRITE REGISTER
DQ
WRITE REGISTER
DQ
WRITE REGISTER
DQ
WRITE REGISTER
[3]
(512K x 36)
D
D
,
DQP
BYTE
C
C
,
DQP
B
B
,
DQP
A
,
DQP
BYTE
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQP
DQP
DQP
DQP
DQs
A
B
C
D
Logic Block Diagram – CY7C1383DV25/CY7C1383FV25
A0,A1,A
MODE
ADV
BW
BW A
BWE
GW
CE
CE 2
CE 3
OE
B
1
ADDRESS
REGISTER
DQ B,DQP B
DQ A,DQP A
ENABLE
SLEEP
CONTROL
Q1
BURST
COUNTER AND
Q0
A[1:0]
DQ B,DQP B
WRITE DRIVER
A,DQP A
DQ
WRITE DRIVER
[3]
(1M x 18)
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQs
DQP
DQP
A
B
Note
3. CY7C1381FV25 and CY7C1383FV25 have only 1 chip enable (CE
).
1
Document #: 38-05547 Rev. *E Page 2 of 28
[+] Feedback
Pin Configurations
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
100-pin TQFP Pinout (3 Chip Enable)
DQP
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
DQP
DDQ
SSQ
SSQ
DDQ
NC
V
DDQ
SSQ
SSQ
DDQ
NC
DD
1CE2
A
A
BWD
BWC
CE
100999897969594939291908988878685848382
C
1
C
2
C
3
4
5
C
6
C
7
C
8
C
9
10
11
C
12
C
13
14
15
16
SS
17
D
18
D
19
20
21
D
22
D
23
D
24
D
25
26
27
D
28
D
29
D
30
BWB
CY7C1381DV25
(512K x 36)
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
BWA
NC
CE3VDDV
SS
NC
V
V
SS
CLKGWBWEOEADSC
A
A
AAAAA
DD
ADSP
ADV
A
A
81
DQP
80
DQ
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
NC
B
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
NC
A
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1383DV25
(1 Mbit x 18)
CE3VDDV
SS
CLKGWBWEOEADSC
ADSP
31323334353637383940414243444546474849
MODE
AAA
1A0
A
A
NC
NC
A
AAAAA
A
SS
DD
V
V
ADV
A
A
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
50
A
A
Document #: 38-05547 Rev. *E Page 3 of 28
[+] Feedback
Pin Configurations (continued)
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
119-Ball BGA
Pinout
CY7C1381FV25 (512K x 36)
2345671
AA AA
AA
AA
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
V
C
C
C
C
C
V
V
BW
V
SS
SS
SS
SS
NC V
V
BW
V
V
V
SS
SS
SS
SS
D
D
D
D
D
MODE
AAA
ADSP
A
AA
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
B
B
B
B
B
A
A
A
A
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
A
SS
SS
SS
B
SS
SS
A
SS
SS
SS
ADSC
V
DD
NC
CE
1
OE
ADV
C
GW
DD
CLK
D
NC
BWE
A1
A0
V
DD
NC/36MNC/72M
TDOTCKTDITMS
NC
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC/72M
V
DDQ
CY7C1383FV25 (1M x 18)
2
AA AA
AA
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
ADSC
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
NC
V
SS
V
SS
V
SS
MODE
V
DD
NC
CE
1
OE
ADV
B
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A NC/36M A
V
V
V
NC
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
A
SS
SS
SS
SS
SS
SS
SS
SS
A
AA
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DDQ
NC/576M
NC/1G
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document #: 38-05547 Rev. *E Page 4 of 28
[+] Feedback
Pin Configurations (continued)
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1381DV25 (512K x 36)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
234 5671
NC/288M
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
V
V
V
V
V
V
V
V
V
V
CE
CE
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
BW
2
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CY7C1383DV25 (1Mx 18)
234 5671
NC/288M
NC/144M
NC
NC
NC V
NC
NC
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
ACE
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
V
DDQ
V
B
B
B
B
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
2
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
SS
V
SS
V
SS
V
SS
A
A1
A0
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
SS
891011
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
AADSC
A
NC
NC/576M
NC/1G DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
AA
B
B
B
B
B
A
A
A
A
A
891011
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
AADSC
A
A
NC/576M
NC/1G DQP
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
DQ
DQ
DQ
DQ
ZZ
A
A
A
A
NCV
NC
NC
NC
NC
A
AA
A
A
A
A
A
Document #: 38-05547 Rev. *E Page 5 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Definitions
Name IO Description
, A1, A Input-
A
0
Synchronous
, BW
BW
A
BWC, BW
B
D
Input-
Synchronous
GW Input-
Synchronous
CLK Input-
Clock
CE
1
Input-
Synchronous
CE
2
Input-
Synchronous
[2]
CE
3
Input-
Synchronous
OE Input-
Asynchronous
ADV Input-
Synchronous
ADSP Input-
Synchronous
ADSC
Input-
Synchronous
BWE
Input-
Synchronous
ZZ Input-
Asynchronous
DQ
s
IO-
Synchronous
DQP
X
IO-
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP
A
feed the 2-bit counter.
[1:0]
or ADSC is active LOW, and CE1, CE2, and CE
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE
2
[2]
to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1
3
is sampled only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE
1
[2]
to select or deselect the device. CE2 is sampled only when a new
3
external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select or deselect the device. CE3 is sampled only when a new external
1
address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE
is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
[1:0]
ADSP
is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers.
A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only
[1:0]
ADSP
is recognized
.
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE
outputs. When HIGH, DQ
and DQPX are placed in a tri-state condition.The outputs are
s
. When OE is asserted LOW, the pins behave as
automatically tri-stated during the data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE
.
Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During
write sequences, DQP
is controlled by BWX correspondingly.
X
[2]
are sampled active.
3
and BWE).
[A:D]
Document #: 38-05547 Rev. *E Page 6 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Pin Definitions (continued)
Name IO Description
MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V
left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
V
DD
V
DDQ
V
SS
V
SSQ
TDO JTAG serial output
TDI JTAG serial input
TMS JTAG serial input
TCK JTAG-
NC, NC/(36M,
72M, 144M,
288M, 576M,
1G)
V
/DNU Ground/DNU This pin can be connected to ground or can be left floating.
SS
Power Supply Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground Ground for the core of the device.
IO Ground Ground for the IO circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not used, this pin can be left unconnected. This pin is not available on TQFP
packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be left floating or connected to V
pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not used, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
Clock
connected to V
. This pin is not available on TQFP packages.
SS
- No Connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
are address expansion pins and are not internally connected to the die.
through a pull up resistor. This
DD
. This pin is not available on
DD
DD
or
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 supports secondary cache in systems using
a linear or interleaved burst sequence. The interleaved burst
order supports Pentium
burst sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP
the controller address strobe (ADSC
through the burst sequence is controlled by the ADV
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
) and byte write select (BWX) inputs. A global write
(BWE
enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE
) is 6.5 ns (133 MHz device).
CDV
®
and i486™ processors. The linear
). Address advancement
, CE2, CE
1
) provide for easy bank
[2]
3
) or
input. A
) and an
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
, CE2, and CE
1
or ADSC is asserted LOW (if
, the write inputs must be
[2]
3
are all
deserted during this first cycle). The address presented to the
address inputs is latched into the address register and the
burst counter and/or control logic, and presented to the
memory core. If the OE
input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
after clock rise. ADSP is ignored if CE1 is HIGH.
t
CDV
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
, CE2, CE
1
is asserted LOW. The addresses
[2]
are all asserted
3
presented are loaded into the address register and the burst
inputs (GW
cycle. If the write inputs are asserted active (see Truth Table
for Read/Write
, BWE, and BWX) are ignored during this first clock
[4, 9]
on page 10 for appropriate states that
indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE
input signal must be deserted
1
Document #: 38-05547 Rev. *E Page 7 of 28
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
and the IOs must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri-stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE
asserted active, (2) ADSC
is asserted LOW, (3) ADSP is
deserted HIGH, and (4) the write input signals (GW
[2]
are all
3
, BWE, and
BWX) indicate a write access. ADSC is ignored if ADSP is
active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core. The information presented to DQ
will be
X
written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE
input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE
.
Burst Sequences
The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/
CY7C1383FV25 provides an on-chip two-bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
[1:0]
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to a interleaved
burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
, CE2, CE
1
remain inactive for the duration of t
[2]
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
DD
)
Third
Address
A1: A0
Linear Burst Address Table (MODE = GND)
First
,
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Fourth
Address
A1: A0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 38-05547 Rev. *E Page 8 of 28
Sleep mode standby current ZZ > VDD – 0.2V 80 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[+] Feedback
CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Truth Table
Cycle Description
Deselected Cycle, Power
[4, 5, 6, 7, 8]
Address
Used
CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
None H X X L X L X X X L-H Tri-State
Down
Deselected Cycle, Power
None L L X L L X X X X L-H Tri-State
Down
Deselected Cycle, Power
None L X H L L X X X X L-H Tri-State
Down
Deselected Cycle, Power
None L L X L H L X X X L-H Tri-State
Down
Deselected Cycle, Power
None X X X L H L X X X L-H Tri-State
Down
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE
6. The DQ pins are controlled by the current cycle and the OE
7. The SRAM always initiates a read cycle when ADSP
8. OE
= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
the ADSP
care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
signal. OE is asynchronous and is not sampled with the clock.
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
is active (LOW).
Document #: 38-05547 Rev. *E Page 9 of 28
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