• User selectable burst counter supporting Intel
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• CY7C1381D/CY7C1383D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball
FBGA package. CY7C1381F/CY7C1383F available in
Pb-free and non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
DD
DDQ
)
)
®
Pentium®
Functional Description
[1]
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a
3.3V, 512K x 36 and 1M x 18 synchronous flow through
SRAMs, designed to interface with high-speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers
controlled by a positive edge triggered clock input (CLK). The
synchronous inputs include all addresses, all data inputs,
address pipelining chip enable (CE
enables (CE2 and CE
[2]
), burst control inputs (ADSC, ADSP,
3
), depth-expansion chip
1
and ADV), write enables (BWx, and BWE), and global write
). Asynchronous inputs include the output enable (OE)
(GW
and the ZZ pin.
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
allows interleaved or linear burst sequences, selected by the
MODE input pin. A HIGH selects an interleaved burst
sequence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated with the processor address strobe
) or the cache controller address strobe (ADSC) inputs.
(ADSP
Address advancement is controlled by the address
advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV
).
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
operates from a +3.3V core power supply while all outputs
operate with a +2.5V or +3.3V supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz100 MHzUnit
Maximum Access Time6.58.5ns
Maximum Operating Current210175mA
Maximum CMOS Standby Current7070mA
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK if ADSP
feed the 2-bit counter.
A
[1:0]
or ADSC is active LOW, and CE1, CE2, and CE
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Clock input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE
2
[2]
to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE
3
is asserted LOW, during a burst operation.
is sampled only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE
[2]
to select or deselect the device. CE2 is sampled only when a new
3
external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external
address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.
When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,
and act as input data pins. OE
is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
is recognized
.
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
[2]
are sampled active.
3
and BWE).
[A:D]
1
BWE
Input-
Synchronous
ZZInput-
Asynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep
condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull down.
DQ
s
IO-
Synchronous
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
read cycle. The direction of the pins is controlled by OE
pins behave as outputs. When HIGH, DQ
and DQPX are placed in a tri-state condition.The
s
. When OE is asserted LOW, the
clock rise of the
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
.
is controlled by BWX correspondingly.
X
DQP
regardless of the state of OE
X
IO-
Synchronous
Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During
write sequences, DQP
Document #: 38-05544 Rev. *FPage 6 of 29
[+] Feedback
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
Pin Definitions (continued)
NameIODescription
MODEInput-StaticSelects burst order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
V
DD
V
DDQ
V
SS
V
SSQ
TDOJTAG serial output
TDIJTAG serial input
TMSJTAG serial input
TCKJTAG-
NC–No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
Power Supply Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
GroundGround for the core of the device.
IO GroundGround for the IO circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available
on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be left floating or connected to V
resistor. This pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
Clock
be connected to V
. This pin is not available on TQFP packages.
SS
are address expansion pins and are not internally connected to the die.
through a pull up
DD
. This pin is not
DD
DD
VSS/DNUGround/DNUThis pin can be connected to ground or can be left floating.
Functional Overview
selection and output tri-state control. ADSP
is HIGH.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t
) is 6.5 ns (133 MHz device).
CDV
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
supports secondary cache in systems utilizing a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium
®
and i486™ processors. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with the processor address strobe (ADSP
) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
) and byte write select (BWX) inputs. A global write
(BW
E
enable (GW
) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous chip selects (CE
asynchronous output enable (OE
, CE2, CE
1
) provide for easy bank
[2]
3
) and an
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE
asserted active, and (2) ADSP
the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter and/or control logic, and later presented to the
memory core. If the OE input is asserted LOW, the requested
data will be available at the data outputs with a maximum to
after clock rise. ADSP is ignored if CE1 is HIGH.
t
CDV
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE
active, and (2) ADSP
is asserted LOW. The addresses
presented are loaded into the address register and the burst
inputs (GW, BWE, and BWX) are ignored during this first clock
cycle. If the write inputs are asserted active (see Truth Table
for Read/Write
[4, 9]
on page 10 for appropriate states that
indicate a write) on the next clock rise, the appropriate data will
be latched and written into the device. Byte writes are allowed.
All IOs are tri-stated during a byte write. As this is a common
IO device, the asynchronous OE
is ignored if CE
[2]
are all
3
or ADSC is asserted LOW (if
, the write inputs must be
[2]
are all asserted
3
input signal must be
1
Document #: 38-05544 Rev. *FPage 7 of 29
[+] Feedback
CY7C1381D, CY7C1381F
CY7C1383D, CY7C1383F
deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are
tri-stated once a write cycle is detected, regardless of the state
.
of OE
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
asserted active, (2) ADSC
, CE2, and CE
1
is asserted LOW, (3) ADSP is
[2]
3
are all
deasserted HIGH, and (4) the write input signals (GW, BWE,
and BW
) indicate a write access. ADSC is ignored if ADSP is
X
active LOW.
The addresses presented are loaded into the address register
and the burst counter, the control logic, or both, and delivered
to the memory core The information presented to DQ
[A:D]
will
be written into the specified address location. Byte writes are
allowed. All IOs are tri-stated when a write is detected, even a
byte write. Since this is a common IO device, the
asynchronous OE
input signal must be deasserted and the IOs
must be tri-stated prior to the presentation of data to DQs. As
a safety precaution, the data lines are tri-stated once a write
cycle is detected, regardless of the state of OE
.
Burst Sequences
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F
provides an on-chip two-bit wraparound burst counter inside
the SRAM. The burst counter is fed by A
, and can follow
[1:0]
either a linear or interleaved burst order. The burst order is
determined by the state of the MODE input. A LOW on MODE
will select a linear burst sequence. A HIGH on MODE will
select an interleaved burst order. Leaving MODE unconnected
will cause the device to default to a interleaved burst
sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation sleep mode. Two
clock cycles are required to enter into or exit from this sleep
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the sleep mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the sleep mode. CE
, CE2, CE
1
remain inactive for the duration of t
[2]
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
6. The DQ pins are controlled by the current cycle and the
7. The SRAM always initiates a read cycle when ADSP
8.
= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
the
care for the remainder of the write cycle.
OE
inactive or when the device is deselected, and all data bits behave as output when
or with the assertion of
ADSP
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
ADSC
signal. OE is asynchronous and is not sampled with the clock.
OE
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
is active (LOW).
OE
Document #: 38-05544 Rev. *FPage 9 of 29
[+] Feedback
Loading...
+ 20 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.