Cypress CY7C1381D, CY7C1383D, CY7C1383F, CY7C1381F User Manual

CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Features
• Supports 133 MHz bus operations
• 512K × 36 and 1M × 18 common IO
• 3.3V core power supply (V
• 2.5V or 3.3V IO supply (V
• Fast clock-to-output time
— 6.5 ns (133 MHz version)
• Provides high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• CY7C1381D/CY7C1383D available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package. CY7C1381F/CY7C1383F available in Pb-free and non Pb-free 119-ball BGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• ZZ sleep mode option
DDQ
)
)
®
Pentium®
Functional Description
[1]
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a
3.3V, 512K x 36 and 1M x 18 synchronous flow through SRAMs, designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining chip enable (CE enables (CE2 and CE
[2]
), burst control inputs (ADSC, ADSP,
3
), depth-expansion chip
1
and ADV), write enables (BWx, and BWE), and global write
). Asynchronous inputs include the output enable (OE)
(GW and the ZZ pin.
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F allows interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe
) or the cache controller address strobe (ADSC) inputs.
(ADSP Address advancement is controlled by the address advancement (ADV) input.
Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV
).
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F operates from a +3.3V core power supply while all outputs operate with a +2.5V or +3.3V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible.
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 210 175 mA
Maximum CMOS Standby Current 70 70 mA
Notes:
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 38-05544 Rev. *F Revised Feburary 07, 2007
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
3, CE2
[+] Feedback
Logic Block Diagram – CY7C1381D/CY7C1381F
[3]
(512K x 36)
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
D
,
DQP
DQ
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
DQ
C
,
DQP
WRITE REGISTER
B
,
DQP
DQ
A
DQ
,
DQP
BYTE
WRITE REGISTER
ENABLE
REGISTER
ADDRESS REGISTER
COUNTER
AND LOGIC
CLR
D
C
B
A
BURST
A
[1:0]
Q1
Q0
A0, A1, A
MODE
ADSC
ADSP
BW
BWE
ADV
BW
BW
CLK
D
BW
C
B
WRITE REGISTER
A
GW
CE1
CE2
CE3
OE
SLEEP
Logic Block Diagram – CY7C1383D/CY7C1383F
DQ
WRITE REGISTER
DQ
WRITE REGISTER
DQ
WRITE REGISTER
DQ
WRITE REGISTER
[3]
(1M x 18)
D
BYTE
B
BYTE
D
,
DQP
C
C
,
DQP
MEMORY
B
,
DQP
A
,
DQP
ARRAY
SENSE AMPS
OUTPUT BUFFERS
INPUT
REGISTERS
DQP
DQP
DQP
DQP
DQs
A
B
C
D
A0,A1,A
ADDRESS REGISTER
MODE
ADV
BW
BW
DQB,DQP
B
A
DQA,DQP
COUNTER AND
B
A
BURST
BWE
GW
CE CE
CE
1
2
3
ENABLE
OE
SLEEP
CONTROL
Note:
3. CY7C1381F and CY7C1383F have only 1 chip enable (CE
Q1
Q0
1
A[1:0]
).
DQB,DQP
B
WRITE DRIVER
A
,DQP
A
DQ
WRITE DRIVER
MEMORY
ARRAY
SENSE AMPS
OUTPUT BUFFERS
INPUT
REGISTERS
DQs DQP DQP B
A
Document #: 38-05544 Rev. *F Page 2 of 29
[+] Feedback
Pin Configurations
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
100-pin TQFP Pinout (3 Chip Enable)
DQP DQ DQ
V
DDQ
V
SSQ
DQ DQ DQ DQ
V
SSQ
V
DDQ
DQ DQ
VSS/DNU
V
DD
NC
V
SS
DQ DQ
V
DDQ
V
SSQ
DQ DQ DQ DQ
V
SSQ
V
DDQ
DQ DQ
DQP
1CE2
A
A
BWD
BWC
CE
100999897969594939291908988878685848382
C
1
C
2
C
3 4 5
C
6
C
7
C
8
C
9 10 11
C
12
C
13 14 15 16 17
D
18
D
19 20 21
D
22
D
23
D
24
D
25 26 27
D
28
D
29
D
30
BWB
CY7C1381D
(512K x 36)
BWA
CE3VDDV
SS
31323334353637383940414243444546474849
MODE
AAA
1A0
A
A
NC
NC
SS
DD
V
V
CLKGWBWEOEADSC
A
A
ADSP
AAAAA
ADV
A
A
81
DQP
80
DQ
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQ V
DDQ
V
SSQ
DQ DQ DQ DQ V
SSQ
V
DDQ
DQ DQ V
SS
NC V
DD
ZZ DQ DQ V
DDQ
V
SSQ
DQ DQ DQ DQ V
SSQ
V
DDQ
DQ DQ DQP
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
B
A
NC NC NC
V
DDQ
V
SSQ
NC
NC DQ DQ
V
SSQ
V
DDQ
DQ DQ
VSS/DNU
V
DD
NC
V
SS
DQ DQ
V
DDQ
V
SSQ
DQ DQ
DQP
NC
V
SSQ
V
DDQ
NC
NC
NC
B
B
B
B
B
B
B
B
B
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1383D
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
SS
CE3VDDV
(1M x 18)
SS
DD
NC
NC
V
V
CLKGWBWEOEADSC
A
AAAAA
A
ADSP
A
A
ADV
81
A
80
NC
79
NC
78
V
77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DDQ
V
SSQ
NC DQP DQ DQ V
SSQ
V
DDQ
DQ DQ V
SS
NC V
DD
ZZ DQ DQ V
DDQ
V
SSQ
DQ DQ NC NC V
SSQ
V
DDQ
NC NC NC
A
A
A
A
A
A
A
A
A
50
A
A
Document #: 38-05544 Rev. *F Page 3 of 29
[+] Feedback
Pin Configurations (continued)
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
A
B
C
D
E
F
G H J
K
L
M
N
P
R
T U
V
DDQ
NC/288M
NC/144M
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
119-Ball BGA
Pinout
CY7C1381F (512K x 36)
2345671
AA AA
AA
AA
DQP
DQ
DQ
DQ DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
V
C
C
C
C
C
V
V
BW
V
SS
SS
SS
SS
NC V
V
BW
V
V
V
SS
SS
SS
SS
D
D
D
D
D
MODE
AAA
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
C
GW
DD
CLK
NC
D
BWE
A1
A0
V
DD
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
SS
SS
SS
B
SS
SS
A
SS
SS
SS
A
AA
DQP
DQ
DQ
DQ DQ
V
DQ
DQ
DQ
DQ
DQP
A
B
B
B
B
B
A
A
A
A
A
NC/36MNC/72M
TDOTCKTDITMS
NC
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC/72M
V
DDQ
CY7C1383F (1M x 18)
2
AA AA
AA
NCDQ
DQ
B
NC
DQ
B
NC
V
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
A
V
V
V
NC
V
NC
V
BW
V
V
V
NC
AA
V
SS
V
SS
V
SS
BW
B
V
SS
NC V
V
SS
NC
V
SS
V
SS
V
SS
MODE
ADSC
V
NC
CE
1
OE
ADV
GW
CLK
NC
BWE
A1
A0
V
ANC/36MA
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
A AA
DQP
A
NC
DQ
A
NC
DQ
A
V
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DDQ
NC/576M
NC/1G
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document #: 38-05544 Rev. *F Page 4 of 29
[+] Feedback
Pin Configurations (continued)
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1381D (512K x 36)
A
B C D
E F G
H J K L
M N
P
R
A
B C D
E
F G H
J K
L
M
N P
R
234 5671
NC/288M
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
V
V
V
V
V
V
V
V
V
V
CE
CE
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
BW
1
BW
2
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
BW
BW
V
V
V
V
V V V
V
V
V
B
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CY7C1383D (1M x 18)
234 5671
NC/288M
NC/144M
NC
NC
NC V
NC
NC
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
ACE
A
NC
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
V
DDQ
V
B
B
B
B
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
2
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
CE
CLK
V
V
V
V V
V
V
V
V
A
A1
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
891011
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
AADSC
A
NC
NC/576M
NC/1G DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
AA
B
B
B
B
B
A
A
A
A
A
891011
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
AADSC
A
A
NC/576M
NC/1G DQP
NC
NC
NC
NC NC
DQ
DQ
DQ
DQ
NC
A
DQ
DQ
DQ
DQ
ZZ
A
A
A
A
NCV
NC
NC
NC
NC
A
AA
A
A
A
A
A
Document #: 38-05544 Rev. *F Page 5 of 29
[+] Feedback
Pin Definitions
Name IO Description
,
A
A
,
A
0
1
, BW
BW
A
BWC, BW
GW
B
D
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
[2]
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
ADV
Input-
Synchronous
ADSP
Input-
Synchronous
ADSC
Input-
Synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP
feed the 2-bit counter.
A
[1:0]
or ADSC is active LOW, and CE1, CE2, and CE
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (all bytes are written, regardless of the values on BW
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
and CE
2
[2]
to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE
3
is asserted LOW, during a burst operation.
is sampled only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE
[2]
to select or deselect the device. CE2 is sampled only when a new
3
external address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A asserted, only ADSP
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
is recognized
.
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
[2]
are sampled active.
3
and BWE).
[A:D]
1
BWE
Input-
Synchronous
ZZ Input-
Asynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull down.
DQ
s
IO-
Synchronous
Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous read cycle. The direction of the pins is controlled by OE pins behave as outputs. When HIGH, DQ
and DQPX are placed in a tri-state condition.The
s
. When OE is asserted LOW, the
clock rise of the
outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected,
.
is controlled by BWX correspondingly.
X
DQP
regardless of the state of OE
X
IO-
Synchronous
Bidirectional data parity IO lines. Functionally, these signals are identical to DQs. During write sequences, DQP
Document #: 38-05544 Rev. *F Page 6 of 29
[+] Feedback
CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
Pin Definitions (continued)
Name IO Description
MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up.
V
V
DDQ
V
SS
V
SSQ
TDO JTAG serial output
TDI JTAG serial input
TMS JTAG serial input
TCK JTAG-
NC No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G
Power Supply Power supply inputs to the core of the device.
IO Power Supply Power supply for the IO circuitry.
Ground Ground for the core of the device.
IO Ground Ground for the IO circuitry.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
Synchronous
JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be left floating or connected to V resistor. This pin is not available on TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous
is not being utilized, this pin can be disconnected or connected to V available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
Clock
be connected to V
. This pin is not available on TQFP packages.
SS
are address expansion pins and are not internally connected to the die.
through a pull up
DD
. This pin is not
DD
DD
VSS/DNU Ground/DNU This pin can be connected to ground or can be left floating.
Functional Overview
selection and output tri-state control. ADSP is HIGH.
All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t
) is 6.5 ns (133 MHz device).
CDV
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F supports secondary cache in systems utilizing a linear or interleaved burst sequence. The interleaved burst order supports Pentium
®
and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with the processor address strobe (ADSP
) or the controller address strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
) and byte write select (BWX) inputs. A global write
(BW
E
enable (GW
) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip selects (CE asynchronous output enable (OE
, CE2, CE
1
) provide for easy bank
[2]
3
) and an
Single Read Accesses
A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE asserted active, and (2) ADSP the access is initiated by ADSC deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter and/or control logic, and later presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs with a maximum to
after clock rise. ADSP is ignored if CE1 is HIGH.
t
CDV
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE active, and (2) ADSP
is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWX) are ignored during this first clock cycle. If the write inputs are asserted active (see Truth Table
for Read/Write
[4, 9]
on page 10 for appropriate states that
indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. All IOs are tri-stated during a byte write. As this is a common IO device, the asynchronous OE
is ignored if CE
[2]
are all
3
or ADSC is asserted LOW (if
, the write inputs must be
[2]
are all asserted
3
input signal must be
1
Document #: 38-05544 Rev. *F Page 7 of 29
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
deasserted and the IOs must be tri-stated prior to the presen­tation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state
.
of OE
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are satisfied at clock rise: (1) CE asserted active, (2) ADSC
, CE2, and CE
1
is asserted LOW, (3) ADSP is
[2]
3
are all
deasserted HIGH, and (4) the write input signals (GW, BWE, and BW
) indicate a write access. ADSC is ignored if ADSP is
X
active LOW.
The addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core The information presented to DQ
[A:D]
will be written into the specified address location. Byte writes are allowed. All IOs are tri-stated when a write is detected, even a byte write. Since this is a common IO device, the asynchronous OE
input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE
.
Burst Sequences
The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A
, and can follow
[1:0]
either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE
, CE2, CE
1
remain inactive for the duration of t
[2]
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
returns LOW.
Interleaved Burst Address Table (MODE = Floating or V
First
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
DD
)
Third
Address
A1: A0
Fourth
Address
A1: A0
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 38-05544 Rev. *F Page 8 of 29
Sleep mode standby current ZZ > VDD – 0.2V 80 mA Device operation to ZZ ZZ > VDD – 0.2V 2t ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ns ns ns
ZZ inactive to exit sleep current This parameter is sampled 0 ns
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CY7C1381D, CY7C1381F CY7C1383D, CY7C1383F
Truth Table
[4, 5, 6, 7, 8]
ADDRESS
Cycle Description
Deselected Cycle, Power
Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
None H X X L X L X X X L-H Tri-State
Down
Deselected Cycle, Power
None L L X L L X X X X L-H Tri-State
Down
Deselected Cycle, Power
None L X H L L X X X X L-H Tri-State
Down
Deselected Cycle, Power
None L L X L H L X X X L-H Tri-State
Down
Deselected Cycle, Power
None X X X L H L X X X L-H Tri-State
Down
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
Write Cycle, Begin Burst External L H L L H L X L X L-H D
Read Cycle, Begin Burst External L H L L H L X H L L-H Q
Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
Read Cycle, Continue Burst Next X X X L H H L H L L-H Q
Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes:
4. X=Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE
6. The DQ pins are controlled by the current cycle and the
7. The SRAM always initiates a read cycle when ADSP
8.
= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
the care for the remainder of the write cycle.
OE inactive or when the device is deselected, and all data bits behave as output when
or with the assertion of
ADSP
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
ADSC
signal. OE is asynchronous and is not sampled with the clock.
OE
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
is active (LOW).
OE
Document #: 38-05544 Rev. *F Page 9 of 29
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