Cypress CY7C1380D, CY7C1382D, CY7C1382F, CY7C1380F User Manual
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM
Features
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
3, CE2
are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.
■ Supports bus operation up to 250 MHz
■ Available speed grades are 250, 200, and 167 MHz
■ Registered inputs and outputs for pipelined operation
■ 3.3V core power supply
■ 2.5V or 3.3V I/O power supply
■ Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
■ Provides high performance 3-1-1-1 access rate
■ User selectable burst counter supporting Intel
leaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed write
■ Asynchronous output enable
■ Single cycle chip deselect
■ CY7C1380D/CY7C1382D is available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package; CY7C1380F/CY7C1382F is available in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non
Pb-free 119-ball BGA and 165-ball FBGA package
■ IEEE 1149.1 JTAG-Compatible Boundary Scan
■ ZZ sleep mode option
Pentium® inter-
Functional Description
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive edge triggered clock
input (CLK). The synchronous inputs include all addresses, all
data inputs, address-pipelining chip enable (CE
depth-expansion chip enables (CE
and CE
2
[2]
), burst control
3
inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE),
and global write (GW). Asynchronous inputs include the output
enable (OE
) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP
) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as they are controlled by the advance pin
).
(ADV
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Ta ble 1 on page 6 and “Truth Table” on page 10
for further details). Write cycles can be one to two or four bytes
wide as controlled by the byte write control inputs. GW
active LOW causes all bytes to be written.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
operates from a +3.3V core power supply while all outputs
operate with a +2.5 or +3.3V power supply. All inputs and outputs
are JEDEC-standard and JESD8-5-compatible.
[1]
1
when
),
Selection Guide
Description 250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.0 3.4 ns
Maximum Operating Current 350 300 275 mA
Maximum CMOS Standby Current 70 70 70 mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05543 Rev. *F Revised January 12, 2009
[+] Feedback
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Logic Block Diagram – CY7C1380D/CY7C1380F
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
AMPS
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
MEMORY
ARRAY
DQs
DQP
A
DQP
B
DQP
C
DQP
D
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
D
,DQP
D
BYTE
WRITE DRIVER
A0, A1, A
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
Q1
ADSC
BW
B
BW
A
CE
1
DQB,DQP
B
WRITE REGISTER
DQA,DQP
A
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
MEMORY
ARRAY
2
CE2
CE3
GW
BWE
PIPELINED
ENABLE
DQs
DQP
A
DQP
B
OUTPUT
INPUT
DQA,DQP
A
WRITE DRIVER
OUTPUT
BUFFERS
DQB,DQP
B
WRITE DRIVER
ZZ
SLEEP
CONTROL
Note
3. CY7C1380F and CY7C1382F in 119-ball BGA package have only 1 chip enable (CE
1
).
[3]
(512K x 36)
Logic Block Diagram – CY7C1382D/CY7C1382F
Document #: 38-05543 Rev. *F Page 2 of 34
[3]
(1M x 18)
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Pin Configurations
100-Pin TQFP Pinout (3-Chip Enable)
Figure 1. CY7C1380D, CY7C1380F(512K X 36) Figure 2. CY7C1382D, CY7C1382F (1M X 18)
Document #: 38-05543 Rev. *F Page 3 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
119-Ball BGA Pinout
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
DQP
C
DQ
C
DQ
D
DQ
C
DQ
D
AA AA
ADSP
V
DDQ
AA
DQ
C
V
DDQ
DQ
C
V
DDQ
V
DDQ
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
TDOTCKTDITMS
NC/36MNC/72M
NC
V
DDQ
V
DDQ
V
DDQ
AAA
A
A
AA
A
AA
A
A0
A1
DQ
A
DQ
C
DQ
A
DQ
A
DQ
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQ
B
V
DD
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
DQP
A
MODE
DQP
D
DQP
B
BW
B
BW
C
NC V
DD
NC
BW
A
NC
BWE
BW
D
ZZ
2
345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
NCDQ
B
DQ
B
DQ
B
DQ
B
AA AA
ADSP
V
DDQ
AA
NC
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
NC
NC
NC
NC/72M
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
TDOTCKTDITMS
AA
NC
V
DDQ
V
DDQ
V
DDQ
A NC/36M A
A
A
AA
A
AA
A
A0
A1
DQ
A
DQ
B
NC
NC
DQ
A
NC
DQ
A
DQ
A
NC
NC
DQ
A
NC
DQ
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
MODE
DQP
B
DQP
A
NC
BW
B
NC V
DD
NC
BW
A
NC
BWE
NC
ZZ
Figure 3. CY7C1380F (512K X 36)
Figure 4. CY7C1382F (1M X 18)
Document #: 38-05543 Rev. *F Page 4 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
165-Ball FBGA Pinout (3-Chip Enable)
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
DQP
C
DQ
C
DQP
D
NC
DQ
D
CE
1
BW
B
CE
3
BW
C
BWE
A
CE2
DQ
C
DQ
D
DQ
D
MODE
NC
DQ
C
DQ
C
DQ
D
DQ
D
DQ
D
NC/36M
NC/72M
V
DDQ
BW
D
BW
A
CLK
GW
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
A
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCK
V
SS
TDI
A
A
DQ
C
V
SS
DQ
C
V
SS
DQ
C
DQ
C
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
D
DQ
D
NC
NC
V
DDQ
V
SS
TMS
891011
A
ADV
A
ADSC
NC
OE ADSP
A
NC/576M
V
SS
V
DDQ
NC/1G DQP
B
V
DDQ
V
DD
DQ
B
DQ
B
DQ
B
NC
DQ
B
NC
DQ
A
DQ
A
V
DD
V
DDQ
V
DD
V
DDQ
DQ
B
V
DD
NC
V
DD
DQ
A
V
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DDQ
AA
V
SS
A
A
A
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQP
A
DQ
A
A
V
DDQ
A
A0
A
V
SS
234 5671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
TDO
NC/288M
NC/144M
NC
NC
DQP
B
NC
DQ
B
A
CE
1
NC
CE
3
BW
B
BWE
A
CE2
NC
DQ
B
DQ
B
MODE
NC
DQ
B
DQ
B
NC
NC
NC
NC/36M
NC/72M
V
DDQ
NC BW
A
CLK
GW
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
SS
V
DD
V
SS
V
SS
V
SS
A
V
SS
V
SS
V
SS
V
SS
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
V
DD
V
SS
V
DD
V
SS
V
SS
V
DDQ
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
V
SS
NC
TCKA0
V
SS
TDI
A
A
DQ
B
V
SS
NC V
SS
DQ
B
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
A1
DQ
B
NC
NC
NC
V
DDQ
V
SS
TMS
891011
A
ADV
A
ADSC
A
OE ADSP
A
NC/576M
V
SS
V
DDQ
NC/1G DQP
A
V
DDQ
V
DD
NC
DQ
A
DQ
A
NC
NC
NC
DQ
A
NC
V
DD
V
DDQ
V
DD
V
DDQ
DQ
A
V
DD
NC
V
DD
NCV
DD
V
DDQ
DQ
A
V
DDQ
V
DD
V
DD
V
DDQ
V
DD
V
DDQ
NC
V
DDQ
AA
V
SS
A
A
A
DQ
A
NC
NC
ZZ
DQ
A
NC
NC
DQ
A
A
V
DDQ
A
Figure 5. CY7C1380D/CY7C1380F (512K x 36)
Figure 6. CY7C1382D/CY7C1382F (1M x 18)
Document #: 38-05543 Rev. *F Page 5 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 1. Pin Definitions
Name I/O Description
, A1, A Input-
A
0
BWA, BW
BWC, BW
B
D
Synchronous
Input-
Synchronous
GW Input-
Synchronous
BWE
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
[2]
2
[2]
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP
are fed to the two-bit counter.
or ADSC is active LOW, and CE1, CE2, and CE
.
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
CE2 and CE
only when a new external address is loaded.
to select or deselect the device. ADSP is ignored
3
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
and CE
1
3
is asserted LOW, during a burst operation.
to select or deselect the device. CE2 is sampled only when a new external
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select or deselect the device. CE3 is sampled only when a new external address
1
is loaded.
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV Input-
Synchronous
ADSP Input-
Synchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP
recognized. ASDP
is ignored when CE1 is deasserted HIGH.
[2]
are sampled active. A1: A0
3
and BWE).
X
conjunction with
if CE
is HIGH.
1
CE
is sampled
1
and ADSC are both asserted, only ADSP is
ADSC
Input-
Synchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A1: A0
are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is
recognized.
ZZ Input-
Asynchronous
ZZ sleep input. This active HIGH input places the device in a non-time critical sleep condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull down.
DQs, DQP
V
DD
V
SS
V
SSQ
V
DDQ
X
I/O-
Synchronous
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
I/O Power
Supply
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle.
direction of the pins is controlled by OE
When HIGH, DQs and DQP
are placed in a tri-state condition.
X
. When OE is asserted LOW, the pins behave as outputs.
The
Power supply for the I/O circuitry.
Document #: 38-05543 Rev. *F Page 6 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Table 1. Pin Definitions (continued)
MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to V
TDO JTAG serial
output
Synchronous
TDI JTAG serial
input
Synchronous
TMS JTAG serial
input
Synchronous
TCK JTAG-
Clock
NC – No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not
floating selects interleaved burst sequence. This is a strap pin and must remain static during
device operation. Mode pin has an internal pull up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin must be disconnected. This pin is not available on TQFP
packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
not being utilized, this pin can be disconnected or connected to V
TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V
internally connected to the die.
. This pin is not available on TQFP packages.
SS
. This pin is not available on
DD
. This pin is not available on
DD
DD
or left
Document #: 38-05543 Rev. *F Page 7 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (t
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
supports secondary cache in systems using a linear or interleaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence suits
processors that use a linear burst sequence. The burst order is
user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the processor address
strobe (ADSP
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically increments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
) and byte write select (BWX) inputs. A global write enable
(BWE
(GW
) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE
selection and output tri-state control. ADSP
HIGH.
) or the controller address strobe (ADSC). Address
) is 2.6 ns (250 MHz device).
CO
) provide for easy bank
is ignored if CE1 is
Single Write Accesses Initiated by ADSP
This access is initiated when both the following conditions are
satisfied at clock rise: (1) ADSP
CE
, and CE3 are all asserted active. The address presented to
2
A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
The write signals (GW
ignored during this first cycle.
ADSP
triggered write accesses require two clock cycles to
complete. If GW
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the write operation is controlled by BWE
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides byte write capability that is described in the write cycle
descriptions table. Asserting the byte write enable input (BWE
with the selected byte write (BW
the desired bytes. Bytes not selected during a byte write
operation remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE
, BWE, and BWX) and ADV inputs are
is asserted LOW on the second clock rise, the
is asserted LOW and (2) CE1,
and BWX signals.
) input, selectively writes to only
X
) must be deserted
.
)
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2)
CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW
CE
is HIGH. The address presented to the address inputs (A)
1
is stored into the address advancement logic and the address
register while being presented to the memory array. The corresponding data is enabled to propagate to the input of the output
registers. At the rising edge of the next clock, the data is enabled
to propagate through the output register and onto the data bus
within 2.6 ns (250 MHz device) if OE
exception occurs when the SRAM is emerging from a deselected
state to a selected state; its outputs are always tri-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE
read cycles are supported. Once the SRAM is deselected at
clock rise by the chip select and either ADSP or ADSC signals,
its output tri-states immediately.
, BWE) are all deserted HIGH. ADSP is ignored if
or ADSC is asserted LOW,
is active LOW. The only
signal. Consecutive single
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC
HIGH, (3) CE
appropriate combination of the write inputs (GW
BW
) are asserted active to conduct a write to the desired
X
byte(s). ADSC
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a
common I/O device, the output enable (OE
HIGH before presenting data to the DQs inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs are
automatically tri-stated whenever a write cycle is detected,
regardless of the state of OE
, CE2, and CE3 are all asserted active, and (4) the
1
-triggered Write accesses require a single clock
is asserted LOW, (2) ADSP is deserted
, BWE, and
input is ignored during
) must be deserted
.
Document #: 38-05543 Rev. *F Page 8 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Burst Sequences
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F
provides a two-bit wraparound counter, fed by A1: A0, that implements an interleaved or a linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Asserting ADV
burst counter to the next address in the burst sequence. Both
LOW at clock rise automatically increments the
Table 2. Interleaved Burst Address Table (MODE = Floating
or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
read and write burst operations are supported.
Table 3. Linear Burst Address Table (MODE = GND)
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While in
this mode, data integrity is guaranteed. Accesses pending when
entering the sleep mode are not considered valid nor is the
completion of the operation guaranteed. The device must be
deselected prior to entering the sleep mode. CE
ADSP
, and ADSC must remain inactive for the duration of t
after the ZZ input returns LOW.
, CE2, CE3,
1
ZZREC
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Table 4. ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD – 0.2V 80 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
Fourth
Address
A1: A0
Fourth
Address
A1: A0
ns
ns
ns
Document #: 38-05543 Rev. *F Page 9 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Truth Table
Notes
4. X = Don't Care, H = Logic HIGH, L = Logic LOW.
5. WRITE
= L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.
6. The DQ pins are controlled by the current cycle and the
OE
signal. OE is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
after the
ADSP
or with the assertion of
ADSC
. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle.
8.
OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when
OE
is active (LOW)
.
The Truth Table for this data sheet follows.
Operation Add. Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D
[4, 5, 6, 7, 8]
Document #: 38-05543 Rev. *F Page 10 of 34
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CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Truth Table for Read/Write
Note
9. Table only lists a partial listing of the byte write combinations. Any combination of BW
X
is valid. Appropriate write is done based on which byte write is active.
[4, 9]
Function (CY7C1380D/CY7C1380F) GW BWE BW
D
BW
C
BW
B
BW
A
Read HHXXXX
Read HLHHHH
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA) H LHHHL
A
and DQPB)HLHHLH
B
Write Bytes B, A H L H H L L
Write Byte C – (DQ
and DQPC) HLHLHH
C
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – (DQ
and DQPD) HL LHHH
D
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX
Truth Table for Read/Write
Function (CY7C1382D/CY7C1382F) GW BWE BW
[4, 9]
B
BW
Read H H X X
Read H L H H
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA)HLHL
A
and DQPB)HLLH
B
Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X
A
Document #: 38-05543 Rev. *F Page 11 of 34
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