Cypress CY7C1380C, CY7C1382C User Manual

CY7C1380C
CY7C1382C

18-Mb (512K x 36/1M x 18) Pipelined SRAM

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 225, 200,166 and
133MHz

• Regi stered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• Offered in JEDEC-standard 100-pin TQFP , 119-ball BGA
and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

®

Functional Description

[1]

The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (
Enables (CE
and

ADV

(

). Asynchronous inputs include the Output Enable (OE)

GW

and

2

), Write Enables (

[2]

), Burst Control inputs (

CE

3

BW

), depth-expansion Chip

CE

1

, and

X

), and Global Write

BWE

ADSC, ADSP

and the ZZ pin.
Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (
Address Strobe Controller (

) are active. Subsequent

ADSC

ADSP

) or

burst addresses can be internally generated as controlled by
the Advance pin (

ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active

causes all bytes to be written.

LOW
The CY7C1380C/CY7C1382C operates from a +3.3V core

power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

,

Selection Guide

250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit

Maximum Access Time 2.6 2.8 3.0 3.4 4.2 ns
Maximum Operating Current 350 325 300 275 245 mA
Maximum CMOS Standby Cur rent 70 70 70 70 70 mA
Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www .cypress.com.

, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.

2. CE

3

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05237 Rev. *D Revised February 26, 2004

[+] Feedback

1

A

A

A
B

Logic Block Diagram – CY7C1380C (512K x 36)

CY7C1380C
CY7C1382C

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

BW

BW

BWE

GW

CE
CE
CE

OE

ZZ

2

C

B

A

1
2
3

SLEEP

CONTROL

ADDRESS
REGISTER

D ,

DQPD

DQ

BYTE

WRITE REGISTER

C ,

DQPC

DQ

BYTE

WRITE REGISTER

B ,

DQPB

DQ

BYTE

WRITE REGISTER

DQ

A ,

DQPA

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

Logic Block Diagram – CY7C1382C (1M x 18)

D

,DQP

D

DQ

BYTE

WRITE DRIVER

C ,

DQPC

DQ

BYTE

WRITE DRIVER

B ,

DQPB

DQ

BYTE

WRITE DRIVER

DQ

A ,

DQPA

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP

A
B
C
D

0, A1, A

MODE

ADV

CLK

ADDRESS
REGISTER

A[1:0]

2

Q1

BURST

COUNTER AND

LOGIC

CLR

Q0

ADSC

ADSP

DQB,DQP

B

WRITE DRIVER

DQA,DQP

A

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

DQs
DQP
DQP

INPUT

REGISTERS

BW

BW
BWE

GW

CE

CE2
CE3

DQB,DQP

B

B

A

1

WRITE REGISTER

DQA,DQP

A

WRITE REGISTER

ENABLE

REGISTER

PIPELINED

ENABLE

OE

ZZ

SLEEP

CONTROL

Document #: 38-05237 Rev. *D Page 2 of 36

[+] Feedback

Pin Configurations

1CE2

A

A

BWDBWCBWBBW

CE

A

CE3VDDV

SS

CLKGWBWEOEADSC

100-pin TQFP Pinout

A

A

ADSP

ADV

CY7C1380C
CY7C1382C

1CE2

A

A

CE

A

NCNCBWBBW

CE3VDDV

SS

CLKGWBWEOEADSC

A

A

ADSP

ADV

DQP
DQ
DQc

V

DDQ

V

DQ
DQ
DQ

DQ
V
V

DDQ

DQ

DQ

V

V
DQ
DQ

V

DDQ

V

DQ
DQ
DQ
DQ

V
V

DDQ

DQ
DQ

DQP

SSQ

SSQ

NC
NC

SSQ

SSQ

100999897969594939291908988878685848382

C

1

C

2
3
4
5

C

6

C

7

C

8

C

9
10
11

C

12

C

13
14

DD

15
16

SS

17

D

18

D

19
20
21

D

22

D

23

D

24

D

25
26
27

D

28

D

29

D

30

CY7C1380C

(512K X 36)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

NC / 72M

NC / 36M

A

A

DD

V

AAAAA

SS

V

81

DQP
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
DQP

B
B
B

B
B
B
B

B
B

A
A

A
A
A
A

A
A

NC
NC
NC

V

DDQ

V

SSQ

NC
NC

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

NC

V

DD

NC

V

SS

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQP

B

NC

V

SSQ

V

DDQ

NC
NC

A

NC

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

A

A

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1382C

(1M x 18)

31323334353637383940414243444546474849

AAA

MODE

1A0

A

A

NC / 72M

NC / 36M

A

A

DD

V

AAAAA

SS

V

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A
A
A

A
A

A
A

A
A

50

A

A

Document #: 38-05237 Rev. *D Page 3 of 36

[+] Feedback

Pin Configurations (continued)

V

A
B

C
D

E
F
G

H

J

K
L
M

N
P

R
T

U

NC
NC

DQ
DQ

V

DQ
DQ

V

DQ
DQ

V

DQ
DQ

NC
NC

V

119-ball BGA (1 Chip Enable with JTAG)

CY7C1380C (512K x 36)

2345671

DDQ

DDQ

DDQ

DDQ

DDQ

AA AA
AA

AA

C

D

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

BW

V

SS

V

SS

V

SS

MODE

DQP

C

DQ

C

C
C

D
D

D
D

DQ
DQ

DQ

V

DD

DQ
DQ
DQ

DQ

DQP

C
C
C

C

D
D
D

D

A

AAA

ADSP
ADSC

V

DD

NC

CE

1

OE

ADV

C

GW

DD

CLK

D

NC

BWE

A1
A0

V

DD

A

V
V
V

BW

V

NC

V

BW

V
V

V

NC

TDOTCKTDITMS

SS
SS
SS

SS

SS

SS
SS

SS

CY7C1380C
CY7C1382C

V

DDQ

A
AA

DQP

DQ

B

DQ

B

DQ
DQ

V

DQ
DQ
DQ

DQ

B
B

DD

A
A
A

A

B

A

DQP

A

NC / 36MNC / 72M

NC

NC
NC

DQ
DQ

V

DQ
DQ

V

DQ
DQ

V

DQ
DQ

B
B

DDQ

B
B

DDQ

A
A

DDQ

A
A

B

A

NC

ZZ

V

DDQ

A
B
C
D
E
F
G
H

J
K
L

M

N
P

R
T
U

V

DDQ

NC
NC

B

NC

V

DDQ

NC

DQ

B

V

DDQ

NC

DQ

B

V

DDQ

DQ

B

NC
NC

NC / 72M

V

DDQ

CY7C1382C (512K x 18)

2

AA AA
AA

NCDQ

DQ

B

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

DQP

B

A

345671

ADSP
ADSC

AA

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

V

SS

V

SS

V

SS

V

SS

MODE

V

DD

NC

CE

1

OE

ADV

B

GW

DD

CLK

NC

BWE

A1
A0

V

DD

A NC / 36M A

A

V
V
V
V
V

NC

V

BW

V
V
V

NC

TDOTCKTDITMS

SS
SS
SS
SS
SS

SS

SS
SS
SS

A
AA

DQP

A

NC

DQ

A

NC

DQ

A

V

DD

NC

DQ

A

A

NC

DQ

A

NC

A
AA

NC

V

DQ

V

DQ

V

DQ

V

DQ

V

DDQ

NC
NC
NC

A

DDQ

A

NC

DDQ

A

NC

DDQ

NC

A

NC
ZZ

DDQ

Document #: 38-05237 Rev. *D Page 4 of 36

[+] Feedback

Pin Configurations (continued)

234 5671

NC / 288M

A
B
C

D
E

G
H

K

M
N
P

R

A

NC

DQP

C

DQ

C

DQ

C

F

DQ
DQ

C
C

NC

J

L

DQ
DQ
DQ
DQ

DQP

D
D
D
D

D

NC

MODE

A

NC

DQ

C

DQ

C

DQ

C

DQ

C

V

SS

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC / 72M
NC / 36M

CE

CE2
V
V
V
V
V

NC

V
V
V
V
V

1

DDQ
DDQ

DDQ
DDQ
DDQ

DDQ
DDQ
DDQ
DDQ
DDQ

A
A

165-ball fBGA

CY7C1380C (512K x 36)

BW
BW

V
V

V
V
V

V
V
V
V

V
V

SS
DD

DD
DD
DD

DD
DD
DD
DD

DD
SS

A

A

BW

BW

V
V

V
V
V

V
V

V
V
V

B

A
SS
SS
SS
SS
SS

SS
SS

SS
SS
SS

C
D

NC

TDI

TMS

CE
CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

A0

CY7C1380C
CY7C1382C

891011

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCK

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A
A

NC DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

NC

NC / 144M

B

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

A
AA

A
B
C

D
E
F

G

H

J
K
L

M

N
P

R

CY7C1382C (1M x 18)

2345671

NC / 288M

NC
NC
NC
NC V
NC
NC

NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

A
A

NC

DQ

B

DQ

B

DQ

B

DQ

B

V

SS

NC
NC
NC
NC
NC

NC / 72M
NC / 36M

CE
CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A
A

BW

1

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

891011

CE

CLK

V

SS

V

SS
SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

A

A1

BWE

3

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

ADSC

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD
DD

V

DD

V

DD

V

DD

V

SS

A

A

ADV

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

A
NC DQP
NC
NC
NC
NC

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

A

NC / 144M

A

DQ

A

DQ

A

DQ

A

DQ

A

ZZ
NCV
NC
NC

NC
NC

A
AA

Document #: 38-05237 Rev. *D Page 5 of 36

[+] Feedback

CY7C1380C
CY7C1382C

CY7C1380C–Pin Definitions

Name TQFP BGA fBGA I/O Description

A

, A1 , A 37,36,32,

0

33,34,35,

42,43,44,45,

46,47,48,
49,50,81,

82,99,100

P4,N4,
A2,B2,
C2,R2,

A3,B3,C3,

T3,T4,A5,B5,

C5,

R6,P6,A2,

A10,B2,

B10,N6,P3,P4,

P8,P9,P10,

P11,R3,R4,R8,

R9,R10,R11

Input-

Synchronous

T5,A6,B6,C6,

R6

BWA,BW
BWC,BW

GW

BWE

B
D

93,94,95,

96

88

87 M4 A7 Input-

L5,G5,

G3,L3

B5,A5,A4,

B4

Synchronous

H4 B7 Input-

Synchronous

Synchronous

Input-

CLK 89 K4 B6 Input-

Clock

CE

CE

1

[2]

2

98 E4 A3 Input-

Synchronous

97 - B3 Input-

Synchronous

Address Inputs used to select one of the
256K address locations. Sampled at the rising

edge of the CLK if
LOW, and CE
active. A1: A0 are fed to the two-bit counter.

1, CE2

ADSP

, and CE

or

ADSC

3

is active

[2]

are sampled

.

Byte Write Select Inputs, active LOW.
Qualified with BWE

to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW.

When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are
written, regardless of the values on BW

).

BWE

and

X

Byte Write Enable Input, active LOW. Sam ­pled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV

is asserted LOW,

during a burst operation.
Chip Enable 1 Input, active LOW . Sampled on

the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
ADSP

is ignored if CE1 is HIGH.

Chip Enable 2 Input, active HIGH. Sampled
on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.

CE

[2]

3

92 - A6 Input-

Synchronous

Chip Enable 3 Input, active LOW . Sampled on
the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.Not
available for AJ package version.

connected for BGA. Where referenced, CE
assumed active throughout this document for

Not

is

3

BGA.

OE

86 F4 B8 Input-

Asynchronous

Output Enable, asynchronous input, activ e
LOW. Controls the direction of the I/O pins.

When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE

is masked during
the first clock of a read cycle when emerging
from a deselected state.

ADV

83 G4 A9 Input-

Synchronous

Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst
cycle.

Document #: 38-05237 Rev. *D Page 6 of 36

[+] Feedback

CY7C1380C
CY7C1382C

CY7C1380C–Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

ADSP

ADSC

ZZ 64 T7 H11 Input-

DQs, DQPs

84 A4 B9 Input-

85

52,53,56,
57,58,59,
62,63,68,
69,72,73,

74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22

,
23,24,25,
28,29,51,

80,1,30

B4 A8 Input-

K6,L6,

M6,N6,

K7,L7,
N7,P7,
E6,F6,

G6,H6,

D7,E7,

G7,H7,

D1,E1,

G1,H1,

E2,F2,

G2,H2,

K1,L1,
N1,P1,
K2,L2,

M2,N2,

P6,D6,

D2,P2

M1 1,L11,
K11,J11,

J10,K10,
L10,M10,
D10,E10,
F10,G10,
D1 1,E11,
F11,G11,

D1,E1,F1,

G1,D2,E2,F2,

G2,J1,

K1,L1,M1,

J2,K2,L2,

M2,N11,

C11,C1,N1

Synchronous

Synchronous

Asynchronous

I/O-

Synchronous

Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW . When

asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP
ADSP
CE

is deasserted HIGH.

1

Address Strobe from Controller, sampled on
the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP
ADSP

ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an
internal pull-down.

Bidirectional Data I/O lines. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
during the previous

The direction of the pins is controlled by OE
When OE
outputs. When HIGH, DQs and DQP
placed in a tri-state condition.

and ADSC are both asserted, only

is recognized. ASDP is ignored when

and ADSC are both asserted, only

is recognized.

clock rise of the read cycle.

is asserted LOW, the pins behave as

are

X

.

V

DD

V

SS

Document #: 38-05237 Rev. *D Page 7 of 36

15,41,65,91J2,C4,J4,R4,J6D4,D8,E4,E8,

17,40,67,

90

D3,E3,
F3,H3,

K3,M3,

N3,P3,
D5,E5,
F5,H5,

K5,M5,

N5,P5

F4,F8,

G4,G8,H4,H8,

J4,J8,

K4,K8,L4,

L8,M4,M8

C4,C5,C6,C7,
C8,D5,D6,D7,

E5,E6,E7,F5,

F6,F7,G5,G6,

G7,H2,H5,H6,

H7,J5,J6,J7,

K5,K6,K7,

L5,L6,L7,

M5,M6,M7,N4,

N8

Power Supply Power supply inputs to the core of the de-

vice.

Ground Ground for the core of the device.

[+] Feedback

CY7C1380C
CY7C1382C

CY7C1380C–Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

V

SSQ

V

DDQ

MODE 31 R3 R1 Input-

TDO - U5 P7 JTAG serial

TDI - U3 P5 JTAG serial

5,10,21,26,55,

60,71,

76

4,11,20,27,54,

61,70,

77

- - I/O Ground Ground for the I/O circuitry.

A1,F1,J1,M1,

U1,

A7,F7,J7,M7,

U7

C3,C9,D3,D9,

E3,E9,F3,F9,G

3,
G9,J3,J9,
K3,K9,L3,

L9,M3,M9,N3,

N9

I/O Power

Supply

Static

output

Synchronous

input

Synchronous

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND

selects linear burst sequence. When tied to V
or left floating selects interleaved burst
sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an
internal pull-up.

Serial data-out to the JTAG circuit. Delivers
data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.

Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon­nected or connected to V
available on TQFP packages.

. This pin is not

DD

DD

TMS - U2 R5 JTAG serial

TCK - U4 R7 JTAG-Clock Clock input to the JT AG circuitry. If the JT AG

NC 14,16,66,

39,38

B1,C1,

R1,T1,T2,J3,

D4,

L4,J5,R5,6T,

6U,

B7,C7,

R7

A11,B1,C2,C1

0,H1,H3,H9,

H10,
N2,N5,N7,N10
,P1,A1,B11,P2

,R2,N6

input

Synchronous

- No Connects. Not internally connected to the

Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon­nected or connected to V
available on TQFP packages.

feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.

die

. This pin is not

DD

Document #: 38-05237 Rev. *D Page 8 of 36

[+] Feedback

CY7C1382C:Pin Definitions

Name TQFP BGA fBGA I/O Description

CY7C1380C
CY7C1382C

A

, A1 , A 37,36,32,

0

33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,

99,100

P4,N4,

A2,B2,

C2,R2,

T2,A3,

B3,C3,

T3,A5,

B5,C5,

T5,A6,

R6,P6,A2,

A10,A11,

B2,B10,P3,P4,

N6,P8,P9,

P10,P11,

R3,R4,R8,R9,

R10,

R11

Input-

Synchronous

B6,C6,

R6,T6

BW

GW

BWE

A,BWB

93,94 G3,L5 B5,A4 Input-

Synchronous

88

H4 B7 Input-

Synchronous

87 M4 A7 Input-

Synchronous

CLK 89 K4 B6 Input-

Clock

CE

CE

CE

OE

ADV

1

[2]

2

[2]

3

98 E4 A3 Input-

Synchronous

97 - B3 Input-

Synchronous

92 - A6 Input-

Synchronous

86 F4 B8 Input-

Asynchronous

83 G4 A9 Input-

Synchronous

Address Inputs used to select one of the 512K
address locations. Sampled at the rising edge of

the CLK if

ADSP

or

is active LOW, and CE1,

ADSC

CE2, and CE3 are sampled active. A1: A0 are fed
to the two-bit counter.

.

Byte Write Select Inputs, active LOW. Qualified
with BWE
Sampled on the rising edge of CLK

to conduct byte writes to the SRAM.

.

Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).

Byte Write Enable Input, active LOW. Sampled
on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.

Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV

is asserted LOW, during a

burst operation.
Chip Enable 1 Input, active LOW. Sampled on the

rising edge of CLK. Used in conjunction with CE
and CE
ignored if CE

to select/deselect the device. ADSP is

3

is HIGH.

1

2

Chip Enable 2 Input, active HIGH. Sampled on
the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.

Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE2 to select/deselect the device. Not available
for AJ package version.

Where referenced, CE
throughout this document for BGA.

Not connected for BGA.
is assumed active

3

1

Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE

is masked during the first clock
of a read cycle when emerging from a deselected
state.

Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst
cycle.

Document #: 38-05237 Rev. *D Page 9 of 36

[+] Feedback

CY7C1382C:Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

CY7C1380C
CY7C1382C

ADSP

ADSC

ZZ 64 T7 H11 Input-

DQs,
DQPs

V

DD

V

SS

V

SSQ

84 A4 B9 Input-

85

58,59,62,
63,68,69,

72,73,8,9,

12,13,18,
19,22,23,

74,24

15,41,65,91C4,J2,J4,J6,R4D4,D8,E4,E8,

17,40,67,

90

5,10,21,26,55,

60,71,

76

P4 A8 Input-

P7,K7,

G7,E7,

F6,H6,L6,N6,

D1,

H1,L1,
N1,E2,
G2,K2,
M2,D6,

P2

D3,D5,

E5,E3,F3,F5,

G5,

H3,H5,

K3,K5,L3,M3,

M5,

N3,N5,

P3,P5

- - I/O Ground Ground for the I/O circuitry.

J10,K10,

L10,M10,

D11,E11,
F11,G11,J1,K1
,L1,M1,D2,E2,

F2,

G2,C11,N1

F4,F8,

G4,G8,H4,

H8,J4,J8,
K4,K8,L4,
L8,M4,M8

H2,C4,C5,C6,
C7,C8,D5,D6,
D7,E5,E6,E7,

F5,F6,F7,

G5,G6,G7,

H5,H6,H7,J5,J

6,J7,

K5,K6,K7,

L5,L6,L7,

M5,M6,M7,N4,

N8

Synchronous

Synchronous

Asynchronous

I/O-

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

Address Strobe from Processor, sampled on
the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device
are captured in the address registers. A1: A0 are
also loaded into the burst counter. When ADSP

are both asserted, only ADSP is recognized.

ADSC
ASDP

is ignored when CE1 is deasserted HIGH.

Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are
captured in the address registers. A1: A0 are also
loaded into the burst counter. When ADSP
ADSC

are both asserted, only ADSP is recognized.

ZZ “sleep” Input, active HIGH. When asserted
HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O lines . As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the
addresses presented during the previous
of the read cycle. The direction of the pins is
controlled by OE
pins behave as outputs. When HIGH, DQs and
DQPX are placed in a tri-state condition.

. When OE is asserted LOW, the

and

and

clock rise

Document #: 38-05237 Rev. *D Page 10 of 36

[+] Feedback

CY7C1382C:Pin Definitions (continued)

Name TQFP BGA fBGA I/O Description

CY7C1380C
CY7C1382C

V

DDQ

MODE 31 R3 R1 Input-

TDO - U5 P7 JTAG serial

TDI - U3 P5 JTAG serial

TMS - U2 R5 JTAG serial

TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG

NC 1,2,3,6,7,

4,11,20,27,54,

61,70,

77

14,16,25,
28,29,30,

38,39,
51,52,53,
56,57,66,
75,78,79,

95,96

A1,A7,F1,F7,
J1,J7,M1,M7,

U1,U7

B1,B7,
C1,C7,
D2,D4,
D7,E1,
E6,H2,
F2,G1,
G6,H7,

J3,J5,K1,

K6,L4,L2,L7,

M6,

N2,L7,P1,P6,

R1,

R5,R7,

T1,T4,U6

C3,C9,D3,D9,

E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,

L9,M3,M9,N3,

N9

A5,B1,B4,

C1,C2,C10,D1

,D10,

E1,E10,F1,

F10,G1,

G10,H1,H3,H9

,H10,J2,J11,

K2,

K11,L2,L1,M2,

M1 1,

N2,N10,N5,N7

N1 1,P1,A1,

B11,

P2,R2

I/O Power Sup-

ply

Static

output

Synchronous

input

Synchronous

input

Synchronous

- No Connects. Not internally connected to the die.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects

linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.

Serial data-out to the JT AG circuit. Delivers data
on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be left uncon­nected. This pin is not available on TQFP
packages.

Serial data-In to the JT AG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be left floating or connected to
V

through a pull up resistor. This pin is not avail-

DD

able on TQFP packages.
Serial data-In to the JT AG circuit. Sampled on the

rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected
to V

. This pin is not available on TQFP packages.

DD

feature is not being utilized, this pin must be
connected to V
packages.

. This pin is not available on TQFP

SS

DD

or left

Document #: 38-05237 Rev. *D Page 11 of 36

[+] Feedback

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(200-MHz device).

The CY7C1380C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP

) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV

input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE

) and Byte Write Select (BWX) inputs. A Global Write

Enable (GW

) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE
asynchronous Output Enable (OE

, CE2, CE3) and an

1

) provide for easy bank
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP

or ADSC is asserted LOW, (2)

CE1, CE2, CE3 are all asserted active, and (3) the Write
signals (GW
CE

is HIGH. The address presented to the address inputs (A)

1

is stored into the address advancement logic and the Address

, BWE) are all deserted HIGH. ADSP is ignored if

Register while being presented to the memory array. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.0 ns (200-MHz device) if OE
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single Read cycles are supported. Once
the SRAM is deselected at clock rise by the chip select and
either ADSP

or ADSC signals, its output will tri-state immedi-

ately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE

, CE2, CE3 are all asserted active. The address

1

is asserted LOW, and

) is 3.0ns

CO

is ignored if CE

is active

CY7C1380C
CY7C1382C

presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW

inputs are ignored during this first cycle.

ADV
ADSP-triggered Write accesses require two clock cycles to

complete. If GW

is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre­sponding address location in the memory array. If GW is HI GH,
then the Write operation is controlled by BWE
signals. The CY7C1380C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE
Write (BW
bytes. Bytes not selected during a Byte Write operation will

) input, will selectively write to only the desired

X

remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1380C is a common I/O device, the Output
Enable (OE) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deserted HIGH, (3) CE

1

(4) the appropriate combination of the Write inputs (GW
and BW
byte(s). ADSC

) are asserted active to conduct a Write to the desired

X

-triggered Write accesses require a single clock

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active, and

1

cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.

Because the CY7C1380C is a common I/O device, the Output
Enable (OE

) must be deserted HIGH before presenting data
to the DQs inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

Burst Sequences

The CY7C1380C provides a two-bit wraparound counter, fed
by A1: A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif­ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user se lectable
through the MODE input.

, BWE, and BWX) and

) with the selected Byte

input is ignored

and BW

.

, BWE,

.

X

Document #: 38-05237 Rev. *D Page 12 of 36

[+] Feedback

CY7C1380C
CY7C1382C

Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

Interleaved Burst Address Table
(MODE = Floating or VDD)

First

Address

A1: A0

00 01 10 11
01 00 11 10
10 11 00 01

11 10 01 00

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Linear Burst Address Table
(MODE = GND)

First

Address

A1: A0

00 01 10 11
01 10 11 00
10 11 00 01

11 00 01 10

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering

the

“sleep” mode. CE

remain inactive for the duration of t
returns LOW

.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

ZZ Mode Electrical Characteristics

Parameter Description T est Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Operation Add. Used

Deselect Cycle,Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle,Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle,Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle,Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle,Power Down None L X H L H L X X X L-H Tri-State
Snooze Mode,Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

Snooze mode standby current ZZ > VDD – 0.2V 60mA mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to snooze current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[ 3, 4, 5, 6, 7, 8]

CE

CE

CE

2

1

ZZ ADSP ADSC ADV

3

WRITE

OE

CLK DQ

ns
ns
ns

Document #: 38-05237 Rev. *D Page 13 of 36

[+] Feedback

CY7C1380C
CY7C1382C

Truth Table

[ 3, 4, 5, 6, 7, 8]

Operation Add. Used

CE

CE

CE

2

1

ZZ ADSP ADSC ADV

3

WRITE

OE

CLK DQ

READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle,Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle,Suspend Burst Current H X X L X H H L X L-H D

Notes:

3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE

5.

6. CE

7. The SRAM always initiates a read cycle when ADSP

8.

Truth Table for Read/Write

= L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.

The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

1

after the
don't care for the remainder of the write cycle

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a re ad cycle all dat a b its are Tri-St ate wh en OE is

OE
inactive or when the device is deselected, and all data bits behave as output when

or with the assertion of

ADSP

ADSC

[5]

Function (CY7C1380C)

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a

BW

.

D

BW

C

BW

B

BW

OE

GW BWE

is active (LOW)

A

Read HHXXXX
Read HLHHHH
Write Byte A – ( DQ
Write Byte B – ( DQ

and DQPA ) HLHHHL

A

and DQPB )HLHHLH

B

Write Bytes B, A H L H H L L
Write Byte C – ( DQ

and DQPC ) HLHLHH

C

Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – ( DQ

and DQPD ) HL LHHH

D

Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX

Truth Table for Read/Write

Function (CY7C1382C)

[5]

GW

BWE

BW

B

BW

A

Read H H X X
Read H L H H
Write Byte A – ( DQ
Write Byte B – ( DQ

and DQPA )HLHL

A

and DQPB )HLLH

B

Write Bytes B, A H L L L
Write All Bytes H L L L
Write All Bytes L X X X

Document #: 38-05237 Rev. *D Page 14 of 36

[+] Feedback

CY7C1380C

T

O

CY7C1382C

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1380C incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with IEEE
Standard 1149.1-1990 but does no t have the set of functions
required for full 1149.1 compliance. These functions from the
IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does
not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1380C contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V

SS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may alter­nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

0

RUN-TEST/

IDLE

1

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

SELECT

0

0

0 0

1

1 1

0 0

0

1

1

SELECT

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

1

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)
Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

1

0

0

1

0

1

1

0

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif­icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TD

TCK

MS TAP CONTROLLER

Selection

Circuitry

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.

At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO bal l on
the falling edge of TCK.

Instruction Register

012293031 ...

Identification Register

012..x ...

Boundary Scan Register

S

election

Circuitr

y

Instruction Register Three-bit instructions can be serially loaded into the instruction

register. This register is loaded when it is placed between the

Document #: 38-05237 Rev. *D Page 15 of 36

[+] Feedback

CY7C1380C
CY7C1382C

TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be pla ced betwee n the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

SS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 75-bit-long
register.

The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1 149.1
instructions are not fully implemented.

The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.

To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction reg ister
upon power-up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To g uarante e that the boun dary scan regi ster will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (

The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.

t

CS plus tCH).

Document #: 38-05237 Rev. *D Page 16 of 36

[+] Feedback

CY7C1380C

123456

T

CY7C1382C

Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass

TAP Timing

Test Clock

(TCK)

t

est Mode Select

(TMS)

t

Test Data-In

(TDI)

Test Data-Out

(TDO)

TMSS

TDIS

t

t

TMSH

t

TDIH

TH

register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

Reserved
These instructions are not implemented but are reserved for

future use. Do not use these instructions.

t

TL

t

CYC

t

TDOX

t

TDOV

DON’T CARE UNDEFINED

TAP AC Switching Characteristics Over the operating Range

[9, 10]

Parameter Symbol Min Max Units

Clock

TCK Clock Cycle Time t
TCK Clock Frequency t
TCK Clock HIGH time t
TCK Clock LOW time t

TCYC

TF
TH
TL

100 ns

10 MHz
40 ns
40 ns

Output Times

TCK Clock LOW to TDO Valid t
TCK Clock LOW to TDO Invalid t

TDOV
TDOX

0ns

20 ns

Setup Times

TMS Set-Up to TCK Clock Rise t
TDI Set-Up to TCK Clock Rise t
Capture Set-Up to TCK Rise t

TMSS

TDIS

CS

10 ns
10 ns
10

Hold Times

TMS hold after TCK Clock Rise t
TDI Hold after Clock Rise t
Capture Hold after Clock Rise t

Notes:

t

CS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register .

9.

10.Test conditions are specified using the load in TAP AC test Conditions. t

R/tF

= 1ns.

TMSH

TDIH

CH

10 ns
10 ns
10 ns

Document #: 38-05237 Rev. *D Page 17 of 36

[+] Feedback

CY7C1380C

T

F

T

F

CY7C1382C

3.3V TAP AC Test Conditions

Input pulse levels........ ........................................VSS to 3.3V

Input rise and fall times....................................................1ns

Input timing reference levels...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage...............................1.5V

3.3V TAP AC Output Load Equivalent

1.5V

50Ω

DO

Z = 50Ω

O

20p

TAP DC Electrical Characteristics And Operating Conditions

(0°C < T A < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)

2.5V TAP AC Test Conditions

Input pulse levels...............................................VSS to 2.5V

Input rise and fall time ......................................................1ns

Input timing reference levels.........................................1.25V

Output reference levels ................................................1.25V

Test load termination supply voltage ............................1.25V

2.5V TAP AC Output Load Equivalent

1.25V

50Ω

DO

[11]

Z = 50Ω

O

20p

PARAMETER DESCRIPTION TEST CONDITIONS MIN MAX U NITS

V

V

V

V

V

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = -4.0 mA,V

IOH = -1.0 mA,V

Output HIGH Voltage IOH = -100 µA

Output LOW Voltage IOL = 8.0 mA

Output LOW Voltage IOL = 100 µA

Input HIGH Voltage

Input LOW Voltage

Input Load Current GND < VIN < V

DDQ
DDQ

DDQ

= 3.3V
= 2.5V

V

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

V

= 3.3V 0.4 V

DDQ

V

= 2.5V 0.4 V

DDQ

V

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

V

= 3.3V 2.0 VDD + 0.3 V

DDQ

= 2.5V 1.7 VDD + 0.3 V

V

DDQ

V

= 3.3V -0.3 0.8 V

DDQ

= 2.5V -0.3 0.7 V

V

DDQ

2.4 V

2.0 V

-5 5 µA

Note:

11.All voltages referenced to V

Document #: 38-05237 Rev. *D Page 18 of 36

SS (GND).

[+] Feedback

Identification Register Definitions

CY7C1380C
CY7C1382C

INSTRUCTION FIELD

Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)

CY7C1380C

(512KX36)

010 0100

01010 1010
000000 000000
100101 010101

00000110100 00000110100

11

CY7C1382C

(1MX18)

DESCRIPTION

Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.

Scan Register Sizes

REGISTER NAME BIT SIZE(X36) BIT SIZE(X18)

Instruction
Bypass
ID
Boundary Scan Order

33

11
32 32
72 72

Identification Codes

INSTRUCTION CODE DESCRIPTION

EXTEST

IDCODE

SAMPLE Z

RESERVED
SAMPLE/PRELOAD

RESERVED
RESERVED
BYPASS

000

001

010

011

100

101

110
111

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.

Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.

Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect

SRAM operations.

Document #: 38-05237 Rev. *D Page 19 of 36

[+] Feedback

119-Ball BGA Boundary Scan Order

CY7C1380C (512K x 36)

BIT# BALL ID B IT# BALL ID

CY7C1380C
CY7C1382C

1
2
3M439 N4
4F440 R6
5B441 T5
6A442 T3
7G443 R2
8C644 R3

9A645 P2
10 D6 46 P1
11 D7 47 N2
12 E6 48 L2
13 G6 49 K1
14 H7 50 N1
15 E7 51 M2
16 F6 52 L1
17 G7 53 K2
18 H6 54 Not Bonded (Preset to 1)
19 T7 55 H1
20 K7 56 G2
21 L6 57 E2
22 N6 58 D1
23 P7 59 H2
24 K6 60 G1
25 L7 61 F2
26 M6 62 E1
27 N7 63 D2
28 P6 64 A5
29 B5 65 A3
30 B3 66 E4
31 C5 67 Internal
32 C3 68 L3
33 C2 69 G3
34 A2 70 G5
35 T4 71 L5
36 B6 72 Internal

K4
H4

37 B2
38 P4

Document #: 38-05237 Rev. *D Page 20 of 36

[+] Feedback

119-Ball BGA Boundary Scan Order

CY7C1382C (1M x 18)

BIT# BALL ID B IT# BALL ID

CY7C1380C
CY7C1382C

1

2

3M439 N4

4F440 R6

5B441 T5

6A442 T3

7G443 R2

8C644 R3

9 A6 45 Not Bonded (Preset to 0)
10 T6 46 Not Bonde d (Preset to 0)
11 Not Bonded (Preset to 0) 47 Not Bonded (Preset to 0)
12 Not Bonded (Preset to 0) 48 Not Bonded (Preset to 0)
13 Not Bonded (Preset to 0) 49 P2
14 D6 50 N1
15 E7 51 M2
16 F6 52 L1
17 G7 53 K2
18 H6 54 Not Bonded (Preset to 1)
19 T7 55 H1
20 K7 56 G2
21 L6 57 E2
22 N6 58 D1
23 P7 59 Not Bonded (Preset to 0)
24 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0)
25 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0)
26 Not Bonded (Preset to 0) 62 Not Bonded (Preset to 0)
27 Not Bonded (Preset to 0) 63 Not Bonded (Preset to 0)
28 Not Bonded (Preset to 0) 64 A5
29 B5 65 A3
30 B3 66 E4
31 C5 67 Internal
32 C3 68 Not Bonded (Preset to 0)
33 C2 69 Internal
34 A2 70 G3
35 T2 71 L5
36 B6 72 Internal

K4
H4

37 B2
38 P4

Document #: 38-05237 Rev. *D Page 21 of 36

[+] Feedback

165-Ball fBGA Boundary Scan Order

CY7C1380C (512K x 36)

BIT# BALL ID BIT# BALL ID

1B637N6
2B738R6
3A739P6
4B840R4
5A841R3
6B942P4
7A943P3
8 B10 44 R1
9 A10 45 N1

10 C11 46 L2

11 E10 47 K2
12 F10 48 J2
13 G10 49 M2
14 D10 50 M1
15 D11 51 L1
16 E11 52 K1
17 F11 53 J1
18 G11 54 Internal
19 H11 55 G2
20 J10 56 F2
21 K10 57 E2
22 L10 58 D2
23 M10 59 G1
24 J11 60 F1
25 K11 61 E1
26 L11 62 D1
27 M11 63 C1
28 N11 64 A2
29 R11 65 B2
30 R10 66 A3
31 R9 67 B3
32 R8 68 B4
33 P10 69 A4
34 P9 70 A5
35 P8 71 B5
36 P11 72 A6

CY7C1380C
CY7C1382C

Document #: 38-05237 Rev. *D Page 22 of 36

[+] Feedback

165-Ball fBGA Boundary Scan Order

CY7C1382C (1M x 18)

BIT# BALL ID BIT# BALL ID

0B636N6
1B737R6
2A738P6
3B839R4
4A840R3
5B941P4
6A942P3
7 B10 43 R1
8 A10 44 Not Bonded (Preset to 0)
9 A11 45 Not Bond ed (Preset to 0)

10 Not Bonded (Preset to 0) 46 Not Bonded (Preset to 0)

11 Not Bonded (Preset to 0) 47 Not Bonded (Preset to 0)
12 Not Bonded (Preset to 0) 48 N1
13 C11 49 M1
14 D11 50 L1
15 E11 51 K1
16 F11 52 J1
17 G11 53 Internal
18 H11 54 G2
19 J10 55 F2
20 K10 56 E2
21 L10 57 D2
22 M10 58 Not Bonded (Preset to 0)
23 Not Bonded (Preset to 0) 59 Not Bonded (Preset to 0)
24 Not Bonded (Preset to 0) 60 Not Bonded (Preset to 0)
25 Not Bonded (Preset to 0) 61 Not Bonded (Preset to 0)
26 Not Bonded (Preset to 0) 62 Not Bonded (Preset to 0)
27 Not Bonded (Preset to 0) 63 A2
28 R11 64 B2
29 R10 65 A3
30 R9 66 B3
31 R8 67 Not Bonded (Preset to 0)
32 P10 68 No t Bond ed (Preset to 0)
33 P9 69 A4
34 P8 70 B5
35 P11 71 A6

CY7C1380C
CY7C1382C

Document #: 38-05237 Rev. *D Page 23 of 36

[+] Feedback

CY7C1380C
CY7C1382C

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V

Relative to GND........–0.3V to +4.6V

DD

DC Voltage Applied to Outputs

in Tri-State...........................................–0.5V to V

DC Input Voltage....................................–0.5V to V

DDQ

DD

+ 0.5V
+ 0.5V

Electrical Characteristics Over the Operating Range

Operating Range

Range

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
Industrial -40°C to +85°C

[12, 13]

Ambient

Temperature V

DD

V

to V

DDQ

DD

Parameter Description Test Conditions Min. Max. Unit

V
V

V

V

V

V

I

I
I

X

OZ
DD

DD
DDQ

OH

OL

IH

IL

Power Supply Voltage 3.135 3.6 V
I/O Supply Voltage V

Output HIGH Voltage V

Output LOW Voltage V

Input HIGH Voltage

Input LOW Voltage

[12]

[12]

Input Load Current ex­cept ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply

Current

= 3.3V 3.135 V

DDQ

V

= 2.5V 2.375 2.625 V

DDQ

= 3.3V, VDD = Min., I

DDQ

V

= 2.5V, VDD = Min., I

DDQ

= 3.3V, VDD = Min., I

DDQ

V

= 2.5V, VDD = Min., I

DDQ

V

= 3.3V 2.0 VDD + 0.3V V

DDQ

V

= 2.5V 1.7 VDD + 0.3V V

DDQ

V

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

GND ≤ VI ≤ V

Input = V

Input = V

V

= Max., I

DD

f = f

MAX

SS
DD
SS
DD

= 1/t

DDQ

Output Disabled –5 5 µA

DDQ,

= 0 mA,

OUT

CYC

= –4.0 mA 2.4 V

OH

= –1.0 mA 2.0 V

OH

= 8.0 mA 0. 4 V

OL

= 1.0 mA 0. 4 V

OL

–5 5 µA

–30 µA

–30 µA

4.0-ns cycle, 250 MHz 350 mA

4.4-ns cycle, 225 MHz 325 mA

DD

5 µA

5 µA

5.0-ns cycle, 200 MHz 300 mA

6.0-ns cycle, 167 MHz 275 mA

7.5-ns cycle, 133 MHz 245 mA

I

SB1

Automatic CE
Power-down
Current—TTL Inputs

V

= Max, Device Deselected,

DD

≥ VIH or VIN ≤ V

V

IN

f = f

MAX

= 1/t

IL

CYC

4.0-ns cycle, 250 MHz 120 mA

4.4-ns cycle, 225 MHz 110 mA

5.0-ns cycle, 200 MHz 100 mA

6.0-ns cycle, 167 MHz 90 mA

7.5-ns cycle, 133 MHz 85 mA

I

SB2

Automatic CE
Power-down
Current—CMOS Inputs

V

= Max, Device Deselected,

DD

≤ 0.3V or VIN > V

V

IN

f = 0

DDQ

– 0.3V,

All speeds 70 mA

V

Document #: 38-05237 Rev. *D Page 24 of 36

[+] Feedback

CY7C1380C
CY7C1382C

Electrical Characteristics Over the Operating Range

[12, 13] (continued)

Parameter Description Test Conditions Min. Max. Unit

I

SB3

Automatic CE
Power-down
Current—CMOS Inputs

V

= Max, Device Deselected, or

DD

V

≤ 0.3V or VIN > V

IN

f = f

MAX

= 1/t

CYC

DDQ

– 0.3V

4.0-ns cycle, 250 MHz 105 mA

4.4-ns cycle, 225 MHz 100 mA

5.0-ns cycle, 200 MHz 95 mA

6.0-ns cycle, 167 MHz 85 mA

7.5-ns cycle, 133 MHz 80 mA

I

SB4

Automatic CE
Power-down
Current—TTL Inputs

V

= Max, Device Deselected,

DD

V

≥ VIH or VIN ≤ VIL, f = 0

IN

All speeds 80 mA

Shaded areas contain advance information.

Notes:

12.Overshoot: V

13.TPower-up: Assumes a linear ramp from 0v to V

Thermal Resistance

Parameter Description Test Conditions

Θ

Θ

Capacitance

(AC) < VDD +1.5V (Pulse width less than t

IH

[14]

JA

JC

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

[14]

/2), undershoot: VIL(AC) > -2V (Pulse width less than t

CYC

(min.) within 200ms. During this time VIH < VDD and V

DD

Package

T est conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.

/2).

CYC

< V

DDQ

DD\

TQFP

BGA

Package

fBGA

Package Unit

31 45 46 °C/W

6 7 3 °C/W

Parameter Description Test Conditions

CIN Input Capacitance TA = 25°C, f = 1 MHz,

V

= 3.3V.

C

CLK

C

I/O

Notes:

14.Tested initially and after any design or process change that may affect these parameters

Clock Input Capacitance 5 8 9 pF
Input/Output Capacitance 5 8 9 pF

V

DD
DDQ

= 2.5V

TQFP

Package

BGA

Package

fBGA

Package Unit

5 8 9 pF

Document #: 38-05237 Rev. *D Page 25 of 36

[+] Feedback

AC Test Loads and Waveforms

3.3V I/O Test Load

CY7C1380C
CY7C1382C

OUTPUT

Z

2.5V I/O Test Load

OUTPUT

Z

= 50Ω

0

= 50Ω

0

VL= 1.5V

(a)

= 1.25V

V

L

(a)

R

R

= 50Ω

L

= 50Ω

L

3.3V

OUTPUT

INCLUDING

2.5V

OUTPUT

INCLUDING

5pF

JIG AND

SCOPE

5pF

JIG AND

SCOPE

R = 317Ω

R = 351Ω

(b)

R = 1667Ω

R =1538Ω

(b)

GND

V

GND

DD

V

DD

≤ 1ns

≤ 1ns

ALL INPUT PULSES

10%

10%

90%

ALL INPUT PULSES

90%

90%

10%

≤ 1ns

(c)

90%

10%

≤ 1ns

(c)

Document #: 38-05237 Rev. *D Page 26 of 36

[+] Feedback

CY7C1380C
CY7C1382C

Switching Characteristics Over the Operating Range

[19, 20]

250 MHz 225 MHz 200 MHz 167 MHz 133 MHz

Parameter Description

t

POWER

VDD(Typical) to the first Access

[15]

1 1111ms

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 4.0 4.4 5 6 7.5 ns
Clock HIGH 1.7 2.0 2.0 2.2 2.5 ns
Clock LOW 1.7 2.0 2.0 2.2 2.5 ns

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid After CLK Rise 2.6 2.8 3.0 3.4 4.2 ns
Data Output Hold After CLK Rise 1.0 1.0 1.3 1.3 1.3 ns
Clock to Low-Z
Clock to High-Z

OE

LOW to Output Valid

LOW to Output Low-Z

OE
OE HIGH to Output High-Z

[16, 17, 18]

[16, 17, 18]

[16, 17, 18]

[16, 17, 18]

1.0 1.0 1.3 1.3 1.3 ns

2.6 2.8 3.0 3.4 3.4 ns

2.6 2.8 3.0 3.4 4.2 ns

0 0000 ns

2.6 2.8 3.0 3.4 4.0 ns

Setup Times

t

AS

t

ADS

Address Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
ADSC, ADSP

Set-up Before CLK

1.2 1.4 1.4 1.5 1.5 ns

Rise

t

ADVS

t

WES

t

DS

t

CES

ADV Set-up Before CLK Rise
GW, BWE, BWX

Set-up Before CLK

Rise
Data Input Set-up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns
Chip Enable Set-Up Before CLK Rise 1.2 1.4 1.4 1.5 1.5 ns

1.2 1.4 1.4 1.5 1.5 ns

1.2 1.4 1.4 1.5 1.5 ns

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

Address Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
ADSP

ADV

Hold After CLK Rise

,

GW

BWE, BW

,

ADSC

Hold After CLK Rise

Hold After CLK Rise

X

0.3 0.4 0.4 0.5 0.5 ns

0.3 0.4 0.4 0.5 0.5 ns

0.3 0.4 0.4 0.5 0.5 ns
Data Input Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns
Chip Enable Hold After CLK Rise 0.3 0.4 0.4 0.5 0.5 ns

Shaded areas contain advance information.

Notes:

15.This part has a voltage regulator internally; t
can be initiated.

, t

16.t

CHZ

17.At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions

18.This parameter is sampled and not 100% tested.

19.Timing reference level is 1.5V when V

20.Test conditions shown in (a) of AC Test Loads unless otherwise noted.

CLZ,tOELZ

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

OEHZ

DDQ

is the time that the power needs to be supplied above VDD( minimum) initially before a read or write operation

POWER

is less than t

= 3.3V and is 1.25V when V

OELZ

and t

is less than t

CHZ

= 2.5V.

DDQ

to eliminate bus contention between SRAMs when sharing the same

CLZ

UnitMin. Max Min. Max Min. Max

Document #: 38-05237 Rev. *D Page 27 of 36

[+] Feedback

Switching Waveforms

D

Read Cycle Timing

[21]

t

CYC

CY7C1380C
CY7C1382C

CLK

ADSP

ADSC

ADDRESS

GW, BWE,

BWx

CE

ADV

OE

ata Out (Q)

t

ADS

t

AS

t

CES

t

t

CL

CH

t

ADH

t

t

ADH

ADS

t

AH

A1

t

WES

t

CEH

High-Z

A2 A3

t

WEH

t

t

ADVH

ADVS

ADV
suspends
burst.

t

t

t

CLZ

t

CO

Single READ BURST READ

OEHZ

Q(A1)

OEV

t

OELZ

t

CO

t

DOH

Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst continued with
new base address

Deselect
cycle

t

CHZ

Q(A2) Q(A2 + 1)Q(A2 + 3)

Burst wraps around
to its initial state

DON’T CARE

Notes:

21.On this diagram, when CE

22.

Full width write can be initiated by either GW

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

LOW; or by GW HIGH, BWE LOW and BWX LOW.

UNDEFINED

Document #: 38-05237 Rev. *D Page 28 of 36

[+] Feedback

Switching Waveforms (continued)

D

Write Cycle Timing

[21, 22]

t

CYC

CY7C1380C
CY7C1382C

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

GW

ADV

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are
ignored for first cycle when
ADSP initiates burst

X

t

t

CEH

CES

CE

A2 A3

t

t

WEH

WES

ADV suspends burst

ADSC extends burst

t

t

ADH

ADS

t

t

WEH

WES

t

t

ADVH

ADVS

OE

Data In (D)

ata Out (Q)

t

t

DH

DS

High-Z

BURST READ BURST WRITE

t

OEHZ

D(A1)

Single WRITE

D(A2) D(A2 + 1) D(A2 + 1)

DON’T CARE

UNDEFINED

D(A2 + 2)

D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

Extended BURST WRITE

Document #: 38-05237 Rev. *D Page 29 of 36

[+] Feedback

Switching Waveforms (continued)

D

Read/Write Cycle Timing

[21, 23, 24]

t

CYC

CY7C1380C
CY7C1382C

CLK

ADSP

ADSC

ADDRESS

BWE,

BW

X

CE

ADV

OE

Data In (D)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

High-Z

t

CES

A2

t

CEH

t

CO

t

CLZ

t

OEHZ

t

t

WES

DS

A3

t

D(A3)

A1

A4 A5 A6

t

WEH

DH

t

OELZ

D(A5) D(A6)

ata Out (Q)

Note:

23.

The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by

is HIGH.

24.GW

High-Z

Q(A2)Q(A1)

Single WRITE

DON’T CARE UNDEFINED

Q(A4) Q(A4+1) Q(A4+2)

BURST READBack-to-Back READs

or ADSC

ADSP

Q(A4+3)

Back-to-Back

WRITEs

.

Document #: 38-05237 Rev. *D Page 30 of 36

[+] Feedback

Switching Waveforms (continued)

Z

[25, 26]

A

Z Mode Timing

CLK

CY7C1380C
CY7C1382C

t

ZZ

t

ZZREC

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

t

ZZI

I

DDZZ

High-Z

t

RZZI

DESELECT or READ Only

DON’T CARE

Notes:

25.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

26.DQs are in high-Z when exiting ZZ sleep mode

Document #: 38-05237 Rev. *D Page 31 of 36

[+] Feedback

Ordering Information

Speed

(MHz) Ordering Code

250 CY7C1380C-250AC

CY7C1382C-250AC
CY7C1380C-250BGC

CY7C1382C-250BGC
CY7C1380C-250BZC

CY7C1382C-250BZC

225 CY7C1380C-225AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1382C-225AC
CY7C1380C-225BGC

CY7C1382C-225BGC
CY7C1380C-225BZC

CY7C1382C-225BZC

200 CY7C1380C-200AC

CY7C1382C-200AC
CY7C1380C-200BGC BG119 119 PBGA
CY7C1382C-200BGC
CY7C1380C-200BZC BB165A 165 fBGA
CY7C1382C-200BZC

167 CY7C1380C-167AC

CY7C1382C-167AC
CY7C1380C-167BGC BG119 119 PBGA
CY7C1382C-167BGC
CY7C1380C-167BZC

CY7C1382C-167BZC

133 CY7C1380C-133AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

Package

Name Part and Package Type

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial

BG119 119 PBGA

BB165A 165 fBGA

BG119 119 PBGA

BB165A 165 fBGA

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

BB165A 165 fBGA

CY7C1380C
CY7C1382C

Operating

Range

167 CY7C1380C-167AI

CY7C1382C-167AI
CY7C1380C-167BGI

CY7C1382C-167BGI
CY7C1380C-167BZI BB165A 165 fBGA
CY7C1382C-167BZI

Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.

Document #: 38-05237 Rev. *D Page 32 of 36

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial

BG119 119 PBGA

[+] Feedback

Package Diagrams

CY7C1380C
CY7C1382C

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R0.08MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

DIMENSIONS ARE IN MILLIMETERS.

12°±1°

(8X)

SEATING PLANE

1.40±0.05

0.20 MAX.

1.60 MAX.

0.10

SEE DETAIL

A

51-85050-*A

Document #: 38-05237 Rev. *D Page 33 of 36

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circui try embodied in a Cypress Semicond uctor product. Nor d oes it convey or imply any licen se under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so ind emnifie s Cypress Semicondu ctor ag ainst all charges.

[+] Feedback

Package Diagrams (continued)

CY7C1380C
CY7C1382C

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

Document #: 38-05237 Rev. *D Page 34 of 36

[+] Feedback

Package Diagrams (continued)

CY7C1380C
CY7C1382C

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*C

i486 is a trademark, and Intel and Pentium are registered tradema rks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are th e trademarks of their respective holders.

Document #: 38-05237 Rev. *D Page 35 of 36

[+] Feedback

CY7C1380C
CY7C1382C

Document History Page

Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM
Document Number: 38-05237

REV. ECN NO. Issue Date

** 116277 08/27/02 SKX New Data Sheet

*A 121540 11/21/02 DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122

*B 121797 11/21/02 CJM Added 7C1380C-133 spec

*C 128904 09/11/03 DPM Changed ordering of notes

*D 206081 02/13/04 RKF Final Datasheet

Orig. of

Change Description of Change

(BB165A) to rev. *C

Updated Ordering Information

Updated JTAG Boundary Scan order
Removed Pipelined Read/Write Timing diagram
Added t

specification in Switching Characteristics table

POWER

Document #: 38-05237 Rev. *D Page 36 of 36

[+] Feedback