Cypress CY7C1380C, CY7C1382C User Manual
CY7C1380C
CY7C1382C
18-Mb (512K x 36/1M x 18) Pipelined SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 225, 200,166 and
133MHz
• Regi stered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 166-MHz device)
— 4.2 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Offered in JEDEC-standard 100-pin TQFP , 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
®
Functional Description
[1]
The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36
and 1,048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (
Enables (CE
and
ADV
(
). Asynchronous inputs include the Output Enable (OE)
GW
and
2
), Write Enables (
[2]
), Burst Control inputs (
CE
3
BW
), depth-expansion Chip
CE
1
, and
X
), and Global Write
BWE
ADSC, ADSP
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
Address Strobe Controller (
) are active. Subsequent
ADSC
ADSP
) or
burst addresses can be internally generated as controlled by
the Advance pin (
ADV
).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active
causes all bytes to be written.
LOW
The CY7C1380C/CY7C1382C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
,
Selection Guide
250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit
Maximum Access Time 2.6 2.8 3.0 3.4 4.2 ns
Maximum Operating Current 350 325 300 275 245 mA
Maximum CMOS Standby Cur rent 70 70 70 70 70 mA
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www .cypress.com.
, CE2 are for TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable.
2. CE
3
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05237 Rev. *D Revised February 26, 2004
[+] Feedback
1
A
A
A
B
Logic Block Diagram – CY7C1380C (512K x 36)
CY7C1380C
CY7C1382C
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
D
BW
BW
BW
BWE
GW
CE
CE
CE
OE
ZZ
2
C
B
A
1
2
3
SLEEP
CONTROL
ADDRESS
REGISTER
D ,
DQPD
DQ
BYTE
WRITE REGISTER
C ,
DQPC
DQ
BYTE
WRITE REGISTER
B ,
DQPB
DQ
BYTE
WRITE REGISTER
DQ
A ,
DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
2
BURST
COUNTER
AND
CLR
LOGIC
PIPELINED
ENABLE
A
[1:0]
Q1
Q0
Logic Block Diagram – CY7C1382C (1M x 18)
D
,DQP
D
DQ
BYTE
WRITE DRIVER
C ,
DQPC
DQ
BYTE
WRITE DRIVER
B ,
DQPB
DQ
BYTE
WRITE DRIVER
DQ
A ,
DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
DQP
DQP
A
B
C
D
0, A1, A
MODE
ADV
CLK
ADDRESS
REGISTER
A[1:0]
2
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB,DQP
B
WRITE DRIVER
DQA,DQP
A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
DQP
INPUT
REGISTERS
BW
BW
BWE
GW
CE
CE2
CE3
DQB,DQP
B
B
A
1
WRITE REGISTER
DQA,DQP
A
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
OE
ZZ
SLEEP
CONTROL
Document #: 38-05237 Rev. *D Page 2 of 36
[+] Feedback
Pin Configurations
1CE2
A
A
BWDBWCBWBBW
CE
A
CE3VDDV
SS
CLKGWBWEOEADSC
100-pin TQFP Pinout
A
A
ADSP
ADV
CY7C1380C
CY7C1382C
1CE2
A
A
CE
A
NCNCBWBBW
CE3VDDV
SS
CLKGWBWEOEADSC
A
A
ADSP
ADV
DQP
DQ
DQc
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
DQP
SSQ
SSQ
NC
NC
SSQ
SSQ
100999897969594939291908988878685848382
C
1
C
2
3
4
5
C
6
C
7
C
8
C
9
10
11
C
12
C
13
14
DD
15
16
SS
17
D
18
D
19
20
21
D
22
D
23
D
24
D
25
26
27
D
28
D
29
D
30
CY7C1380C
(512K X 36)
31323334353637383940414243444546474849
MODE
AAA
1A0
A
A
NC / 72M
NC / 36M
A
A
DD
V
AAAAA
SS
V
81
DQP
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
B
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQP
B
NC
V
SSQ
V
DDQ
NC
NC
A
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
A
A
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1382C
(1M x 18)
31323334353637383940414243444546474849
AAA
MODE
1A0
A
A
NC / 72M
NC / 36M
A
A
DD
V
AAAAA
SS
V
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
50
A
A
Document #: 38-05237 Rev. *D Page 3 of 36
[+] Feedback
Pin Configurations (continued)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
NC
NC
V
119-ball BGA (1 Chip Enable with JTAG)
CY7C1380C (512K x 36)
2345671
DDQ
DDQ
DDQ
DDQ
DDQ
AA AA
AA
AA
C
D
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
V
SS
MODE
DQP
C
DQ
C
C
C
D
D
D
D
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
C
C
C
C
D
D
D
D
A
AAA
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
C
GW
DD
CLK
D
NC
BWE
A1
A0
V
DD
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
CY7C1380C
CY7C1382C
V
DDQ
A
AA
DQP
DQ
B
DQ
B
DQ
DQ
V
DQ
DQ
DQ
DQ
B
B
DD
A
A
A
A
B
A
DQP
A
NC / 36MNC / 72M
NC
NC
NC
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
B
B
DDQ
B
B
DDQ
A
A
DDQ
A
A
B
A
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC / 72M
V
DDQ
CY7C1382C (512K x 18)
2
AA AA
AA
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
ADSC
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
V
DD
NC
CE
1
OE
ADV
B
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A NC / 36M A
A
V
V
V
V
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
AA
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DQ
V
DQ
V
DQ
V
DQ
V
DDQ
NC
NC
NC
A
DDQ
A
NC
DDQ
A
NC
DDQ
NC
A
NC
ZZ
DDQ
Document #: 38-05237 Rev. *D Page 4 of 36
[+] Feedback
Pin Configurations (continued)
234 5671
NC / 288M
A
B
C
D
E
G
H
K
M
N
P
R
A
NC
DQP
C
DQ
C
DQ
C
F
DQ
DQ
C
C
NC
J
L
DQ
DQ
DQ
DQ
DQP
D
D
D
D
D
NC
MODE
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC / 72M
NC / 36M
CE
CE2
V
V
V
V
V
NC
V
V
V
V
V
1
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
165-ball fBGA
CY7C1380C (512K x 36)
BW
BW
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
CY7C1380C
CY7C1382C
891011
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADSC
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC DQP
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
NC
NC / 144M
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1382C (1M x 18)
2345671
NC / 288M
NC
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
NC
NC
NC
NC
NC
NC / 72M
NC / 36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
891011
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
BWE
3
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
ADSC
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC DQP
NC
NC
NC
NC
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
NC / 144M
A
DQ
A
DQ
A
DQ
A
DQ
A
ZZ
NCV
NC
NC
NC
NC
A
AA
Document #: 38-05237 Rev. *D Page 5 of 36
[+] Feedback
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions
Name TQFP BGA fBGA I/O Description
A
, A1 , A 37,36,32,
0
33,34,35,
42,43,44,45,
46,47,48,
49,50,81,
82,99,100
P4,N4,
A2,B2,
C2,R2,
A3,B3,C3,
T3,T4,A5,B5,
C5,
R6,P6,A2,
A10,B2,
B10,N6,P3,P4,
P8,P9,P10,
P11,R3,R4,R8,
R9,R10,R11
Input-
Synchronous
T5,A6,B6,C6,
R6
BWA,BW
BWC,BW
GW
BWE
B
D
93,94,95,
96
88
87 M4 A7 Input-
L5,G5,
G3,L3
B5,A5,A4,
B4
Synchronous
H4 B7 Input-
Synchronous
Synchronous
Input-
CLK 89 K4 B6 Input-
Clock
CE
CE
1
[2]
2
98 E4 A3 Input-
Synchronous
97 - B3 Input-
Synchronous
Address Inputs used to select one of the
256K address locations. Sampled at the rising
edge of the CLK if
LOW, and CE
active. A1: A0 are fed to the two-bit counter.
1, CE2
ADSP
, and CE
or
ADSC
3
is active
[2]
are sampled
.
Byte Write Select Inputs, active LOW.
Qualified with BWE
to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of CLK,
a global write is conducted (ALL bytes are
written, regardless of the values on BW
).
BWE
and
X
Byte Write Enable Input, active LOW. Sam pled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV
is asserted LOW,
during a burst operation.
Chip Enable 1 Input, active LOW . Sampled on
the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
ADSP
is ignored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled
on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE
[2]
3
92 - A6 Input-
Synchronous
Chip Enable 3 Input, active LOW . Sampled on
the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.Not
available for AJ package version.
connected for BGA. Where referenced, CE
assumed active throughout this document for
Not
is
3
BGA.
OE
86 F4 B8 Input-
Asynchronous
Output Enable, asynchronous input, activ e
LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE
is masked during
the first clock of a read cycle when emerging
from a deselected state.
ADV
83 G4 A9 Input-
Synchronous
Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05237 Rev. *D Page 6 of 36
[+] Feedback
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name TQFP BGA fBGA I/O Description
ADSP
ADSC
ZZ 64 T7 H11 Input-
DQs, DQPs
84 A4 B9 Input-
85
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22
,
23,24,25,
28,29,51,
80,1,30
B4 A8 Input-
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
E2,F2,
G2,H2,
K1,L1,
N1,P1,
K2,L2,
M2,N2,
P6,D6,
D2,P2
M1 1,L11,
K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D1 1,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,F2,
G2,J1,
K1,L1,M1,
J2,K2,L2,
M2,N11,
C11,C1,N1
Synchronous
Synchronous
Asynchronous
I/O-
Synchronous
Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW . When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP
ADSP
CE
is deasserted HIGH.
1
Address Strobe from Controller, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP
ADSP
ZZ “sleep” Input, active HIGH. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
Bidirectional Data I/O lines. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
during the previous
The direction of the pins is controlled by OE
When OE
outputs. When HIGH, DQs and DQP
placed in a tri-state condition.
and ADSC are both asserted, only
is recognized. ASDP is ignored when
and ADSC are both asserted, only
is recognized.
clock rise of the read cycle.
is asserted LOW, the pins behave as
are
X
.
V
DD
V
SS
Document #: 38-05237 Rev. *D Page 7 of 36
15,41,65,91J2,C4,J4,R4,J6D4,D8,E4,E8,
17,40,67,
90
D3,E3,
F3,H3,
K3,M3,
N3,P3,
D5,E5,
F5,H5,
K5,M5,
N5,P5
F4,F8,
G4,G8,H4,H8,
J4,J8,
K4,K8,L4,
L8,M4,M8
C4,C5,C6,C7,
C8,D5,D6,D7,
E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6,
H7,J5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,N4,
N8
Power Supply Power supply inputs to the core of the de-
vice.
Ground Ground for the core of the device.
[+] Feedback
CY7C1380C
CY7C1382C
CY7C1380C–Pin Definitions (continued)
Name TQFP BGA fBGA I/O Description
V
SSQ
V
DDQ
MODE 31 R3 R1 Input-
TDO - U5 P7 JTAG serial
TDI - U3 P5 JTAG serial
5,10,21,26,55,
60,71,
76
4,11,20,27,54,
61,70,
77
- - I/O Ground Ground for the I/O circuitry.
A1,F1,J1,M1,
U1,
A7,F7,J7,M7,
U7
C3,C9,D3,D9,
E3,E9,F3,F9,G
3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
I/O Power
Supply
Static
output
Synchronous
input
Synchronous
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND
selects linear burst sequence. When tied to V
or left floating selects interleaved burst
sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an
internal pull-up.
Serial data-out to the JTAG circuit. Delivers
data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
. This pin is not
DD
DD
TMS - U2 R5 JTAG serial
TCK - U4 R7 JTAG-Clock Clock input to the JT AG circuitry. If the JT AG
NC 14,16,66,
39,38
B1,C1,
R1,T1,T2,J3,
D4,
L4,J5,R5,6T,
6U,
B7,C7,
R7
A11,B1,C2,C1
0,H1,H3,H9,
H10,
N2,N5,N7,N10
,P1,A1,B11,P2
,R2,N6
input
Synchronous
- No Connects. Not internally connected to the
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
feature is not being utilized, this pin must be
connected to VSS. This pin is not available on
TQFP packages.
die
. This pin is not
DD
Document #: 38-05237 Rev. *D Page 8 of 36
[+] Feedback
CY7C1382C:Pin Definitions
Name TQFP BGA fBGA I/O Description
CY7C1380C
CY7C1382C
A
, A1 , A 37,36,32,
0
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
99,100
P4,N4,
A2,B2,
C2,R2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
R6,P6,A2,
A10,A11,
B2,B10,P3,P4,
N6,P8,P9,
P10,P11,
R3,R4,R8,R9,
R10,
R11
Input-
Synchronous
B6,C6,
R6,T6
BW
GW
BWE
A,BWB
93,94 G3,L5 B5,A4 Input-
Synchronous
88
H4 B7 Input-
Synchronous
87 M4 A7 Input-
Synchronous
CLK 89 K4 B6 Input-
Clock
CE
CE
CE
OE
ADV
1
[2]
2
[2]
3
98 E4 A3 Input-
Synchronous
97 - B3 Input-
Synchronous
92 - A6 Input-
Synchronous
86 F4 B8 Input-
Asynchronous
83 G4 A9 Input-
Synchronous
Address Inputs used to select one of the 512K
address locations. Sampled at the rising edge of
the CLK if
ADSP
or
is active LOW, and CE1,
ADSC
CE2, and CE3 are sampled active. A1: A0 are fed
to the two-bit counter.
.
Byte Write Select Inputs, active LOW. Qualified
with BWE
Sampled on the rising edge of CLK
to conduct byte writes to the SRAM.
.
Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written,
regardless of the values on BWX and BWE).
Byte Write Enable Input, active LOW. Sampled
on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV
is asserted LOW, during a
burst operation.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE
ignored if CE
to select/deselect the device. ADSP is
3
is HIGH.
1
2
Chip Enable 2 Input, active HIGH. Sampled on
the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
and CE2 to select/deselect the device. Not available
for AJ package version.
Where referenced, CE
throughout this document for BGA.
Not connected for BGA.
is assumed active
3
1
Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When
deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE
is masked during the first clock
of a read cycle when emerging from a deselected
state.
Advance Input signal, sampled on the rising
edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst
cycle.
Document #: 38-05237 Rev. *D Page 9 of 36
[+] Feedback
CY7C1382C:Pin Definitions (continued)
Name TQFP BGA fBGA I/O Description
CY7C1380C
CY7C1382C
ADSP
ADSC
ZZ 64 T7 H11 Input-
DQs,
DQPs
V
DD
V
SS
V
SSQ
84 A4 B9 Input-
85
58,59,62,
63,68,69,
72,73,8,9,
12,13,18,
19,22,23,
74,24
15,41,65,91C4,J2,J4,J6,R4D4,D8,E4,E8,
17,40,67,
90
5,10,21,26,55,
60,71,
76
P4 A8 Input-
P7,K7,
G7,E7,
F6,H6,L6,N6,
D1,
H1,L1,
N1,E2,
G2,K2,
M2,D6,
P2
D3,D5,
E5,E3,F3,F5,
G5,
H3,H5,
K3,K5,L3,M3,
M5,
N3,N5,
P3,P5
- - I/O Ground Ground for the I/O circuitry.
J10,K10,
L10,M10,
D11,E11,
F11,G11,J1,K1
,L1,M1,D2,E2,
F2,
G2,C11,N1
F4,F8,
G4,G8,H4,
H8,J4,J8,
K4,K8,L4,
L8,M4,M8
H2,C4,C5,C6,
C7,C8,D5,D6,
D7,E5,E6,E7,
F5,F6,F7,
G5,G6,G7,
H5,H6,H7,J5,J
6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,N4,
N8
Synchronous
Synchronous
Asynchronous
I/O-
Synchronous
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
Address Strobe from Processor, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1: A0 are
also loaded into the burst counter. When ADSP
are both asserted, only ADSP is recognized.
ADSC
ASDP
is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are
captured in the address registers. A1: A0 are also
loaded into the burst counter. When ADSP
ADSC
are both asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH. When asserted
HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines . As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the
addresses presented during the previous
of the read cycle. The direction of the pins is
controlled by OE
pins behave as outputs. When HIGH, DQs and
DQPX are placed in a tri-state condition.
. When OE is asserted LOW, the
and
and
clock rise
Document #: 38-05237 Rev. *D Page 10 of 36
[+] Feedback
CY7C1382C:Pin Definitions (continued)
Name TQFP BGA fBGA I/O Description
CY7C1380C
CY7C1382C
V
DDQ
MODE 31 R3 R1 Input-
TDO - U5 P7 JTAG serial
TDI - U3 P5 JTAG serial
TMS - U2 R5 JTAG serial
TCK - U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
NC 1,2,3,6,7,
4,11,20,27,54,
61,70,
77
14,16,25,
28,29,30,
38,39,
51,52,53,
56,57,66,
75,78,79,
95,96
A1,A7,F1,F7,
J1,J7,M1,M7,
U1,U7
B1,B7,
C1,C7,
D2,D4,
D7,E1,
E6,H2,
F2,G1,
G6,H7,
J3,J5,K1,
K6,L4,L2,L7,
M6,
N2,L7,P1,P6,
R1,
R5,R7,
T1,T4,U6
C3,C9,D3,D9,
E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,N3,
N9
A5,B1,B4,
C1,C2,C10,D1
,D10,
E1,E10,F1,
F10,G1,
G10,H1,H3,H9
,H10,J2,J11,
K2,
K11,L2,L1,M2,
M1 1,
N2,N10,N5,N7
N1 1,P1,A1,
B11,
P2,R2
I/O Power Sup-
ply
Static
output
Synchronous
input
Synchronous
input
Synchronous
- No Connects. Not internally connected to the die.
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is
a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.
Serial data-out to the JT AG circuit. Delivers data
on the negative edge of TCK. If the JTAG feature is
not being utilized, this pin should be left unconnected. This pin is not available on TQFP
packages.
Serial data-In to the JT AG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be left floating or connected to
V
through a pull up resistor. This pin is not avail-
DD
able on TQFP packages.
Serial data-In to the JT AG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected
to V
. This pin is not available on TQFP packages.
DD
feature is not being utilized, this pin must be
connected to V
packages.
. This pin is not available on TQFP
SS
DD
or left
Document #: 38-05237 Rev. *D Page 11 of 36
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