CYPRESS CY7C1379B User Manual

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CY7C1379B

9-Mbit (256K x 32) Flow-through SRAM

with NoBL™ Architecture

Features

• Can support up to 133-MHz bus operations with zero
wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™
devices

• Internally self-timed output buffer control to eliminate
the need to use

• Registered inputs for flow-through operation

• Byte Write capability

• 256K x 32 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.0 ns (for 117-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP and 165 fBGA packages

• Burst Capability—linear or interleaved burst order

• Low standby power

OE

) pin to suspend operation

Functional Description

[1]

The CY7C1379B is a 3.3V, 256K x 32 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1379B is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN

) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).

Write operations are controlled by the two Byte Write Select
(BW
conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE

) and a Write Enable (WE) input. All writes are

[A:D]

, CE2, CE3) and an

1

) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

MODE

ADV/LD

BW
BW
BW
BW

C

A

B

C

D

WE

OE
CE1
CE2
CE3

ZZ

LK

EN

1

CE

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

ADDRESS
REGISTER

ADV/LD

WRITE ADDRESS

REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP
Control

A1

D1

A0

D0

BURST

C

LOGIC

A1'

Q1

A0'

Q0

O
U

T
P

D

U

A

T

T
A

B
U

S

F

T

F

E

E

E

R

R

S

I
N
G

E

DQ

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

REGISTER

S
E

N

S

E
A

M

P

S

E

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05438 Rev. *A Revised April 15, 2004

CY7C1379B

Selection Guide

133 MHz 117 MHz Unit

Maximum Access Time

Maximum Operating Current 250 220 mA

Maximum CMOS Standby Current

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Pin Configurations

100-lead TQFP

6.5 7.0 ns

30 30 mA

BYTE C

BYTE D

1CE2

A

A

CE

100

99989796959493929190898887868584838281

NC
DQ
DQ

V

DDQ

V
DQ
DQ
DQ
DQ

V

V

DDQ

DQ
DQ

V

/DNU

SS

V

NC

V
DQ
DQ

V

DDQ

V
DQ
DQ
DQ
DQ

V

V

DDQ

DQ
DQ

NC

SS

SS

DD

SS

SS

SS

1
2

C

3

C

4
5
6

C

7

C

8

C

9

C

10
11
12

C

13

C

14
15
16
17
18

D

19

D

20
21
22

D

23

D

24

D

25

D

26
27
28

D

29

D

30

C

BWDBW

BWBBWACE3VDDV

CY7C1379B

SS

CLKWECEN

OE

ADV/LD

A

NC(18M)

A

A

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V

ZZ

DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ

SS

SS

DDQ

SS

DD

DDQ

SS

SS

DDQ

B

B

B

B

BYTE B

B

B

B

B

A

A

A

A

A

A

A

A

BYTE A

31323334353637383940414243

A

A

A

A

A1

A0

MODE

NC

NC

SS

DD

V

V

44454647484950

A

A

A

NC(72M)

NC(36M)

A

A

A

A

Document #: 38-05438 Rev. *A Page 2 of 15

Pin Configurations (continued)

234 5671

A

B
C
D

E
F
G

H

J
K
L
M
N
P

R

NC/288M

NC

NC

DQ

C

DQ

C

DQ

C

DQ

C

NC

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC

MODE

A

A

NC

DQ

C

DQ

C

DQ

C

DQ

C

V

DD

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC / 72M

NC / 36M

CE

CE2

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

CY7C1379B

165-ball fBGA

CY7C1379B (256K x 32)

891011

BW

1

BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

A

A

BW

C

D

BW

V

V

V

V

V
V
V

V

V

V

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

NC

NC

NC

CE

B

CLK

A

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

A1

A0

CEN

3

WE

V

V

V

V

V
V

V

V

V

V

NC

NC

NC

SS

SS

SS

SS

SS

SS

SS

SS

SS

SS

ADV/LD

OE

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

A

NC / 18M

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

A

A

A

A

NC

NC / 144M

NC NC

DQ

DQ

DQ

DQ

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

DQ

DQ

DQ

NC

A

DQ

A

DQ

A

DQ

A

DQ

A

NC

NC

B

B

B

B

ZZ

A

A

A

A

AA

CY7C1379B—Pin Definitions

Name TQFP fBGA I/O Description

A0, A1, A 37,36,32,33,34,

35,44,45,46,

47,48,49,50,81,

82,83,99,100

BWA, BWB,
BW

, BW

C

WE

ADV/LD

93,94,95,96 B5,A5,A4,

D

88 B7 Input-

85 A8 Input-

CLK 89 B6 Input-Clock Clock Input. Used to capture all synchronous inputs to the de-

CE

CE

CE

1

2

3

98 A3 Input-

97 B3 Input-

92 A6 Input-

R6,P6,A2,

A9,A10,B2
B10,P3,P4,
P8,P9,P10,

R3,R4,R8,

R9,R10,R11

B4

Input-

Synchronous

Input-

Synchronous

Synchronous

Synchronous

Synchronous

Synchronous

Synchronous

Address Inputs used to select one of the 256K address
locations. Sampled at the rising edge of the CLK. A

to the two-bit burst counter.

Byte Write Inputs, active LOW. Qualified with
writes to the SRAM. Sampled on the rising edge of CLK.

WE

are fed

[1:0]

to conduct

Write Enable Input, active LOW. Sampled on the rising edge
of CLK if CEN

is active LOW. This signal must be asserted LOW

to initiate a write sequence.

Advance/Load Input. Used to advance the on-chip address
counter or load a new address. When HIGH (and CEN

is assert­ed LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After
being deselected, ADV/LD

should be driven LOW in order to load

a new address.

vice. CLK is qualified with CEN

. CLK is only recognized if CEN

is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.

, and CE3 to select/deselect

2

Chip Enable 2 Input, active HIGH. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.

and CE3 to select/deselect

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.

and CE2 to select/deselect

1

Document #: 38-05438 Rev. *A Page 3 of 15

CY7C1379B—Pin Definitions(continued)

Name TQFP fBGA I/O Description

OE

CEN

86 B8 Input-

Asynchronous

87 A7 Input-

Synchronous

ZZ 64 H11 Input-

Asynchronous

DQ

s

52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,

2,3,6,7,

8,9,12,13,

18,19,22,23,

24,25,28,29

M11,L11,

K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,

I/O-

Synchronous

D1,E1,F1,

G1,D2,E2,

F2,G2,J1,
K1,L1,M1,

J2,K2,L2

M2

Mode 31 R1 Input

Strap Pin

V

DD

15,41,65,91 D4,D8,E4,

E8,F4,F8,

Power Supply Power supply inputs to the core of the device.

G4,G8,H2,

H4,H8,J4,
J8,K4,K8,
L4,L8,M4,

M8

V

DDQ

4,11,20,27,54,

61,70,77

C3,C9,D3,

D9,E3,E9,

I/O Power

Supply

F3,F9,G3,

G9,J3,J9,

K3,K9,L3,

L9,M3,M9,

N3,N9

Output Enable, asynchronous input, active LOW. Combined
with the synchronous logic block inside the device to control the
direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE
data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been
deselected.

Clock Enable Input, active LOW. When asserted LOW the
Clock signal is recognized by the SRAM. When deasserted
HIGH the Clock signal is masked. Since deasserting CEN
not deselect the device, CEN
cycle when required.

ZZ “sleep” Input. This active HIGH input places the device in a
non-time critical “sleep” condition with data integrity preserved.
During normal operation, this pin can be connected to V
floating.

Bidirectional Data I/O Lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge of CLK.
As outputs, they deliver the data contained in the memory loca­tion specified by address during the clock rise of the Read cycle.
The direction of the pins is controlled by OE and the internal
control logic. When OE

is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
tion. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, re­gardless of the state of OE.

Mode Input. Selects the burst order of the device.

When tied to GND selects linear burst sequence. When tied to
VDD or left floating selects interleaved burst sequence.

Power supply for the I/O circuitry.

CY7C1379B

is masked during the

SS

does

or left

can be used to extend the previous

are placed in a three-state condi-

s

Document #: 38-05438 Rev. *A Page 4 of 15

CY7C1379B

CY7C1379B—Pin Definitions(continued)

Name TQFP fBGA I/O Description

V

SS

NC 1,16,30,38,39,

VSS/DNU 14 - Ground/DNU This pin can be connected to Ground or should be left floating.

5,10,17,21,
26,40,55,60,
67,71,76,90,

42,43,51,66,80,

84,95,96

C4,C5,C6,
C7,C8,D5,

D6,D7,E5,

E6,E7,F5,

F6,F7,G5,

G6,G7,H5,

H6,H7,J5,
J6,J7,K5,K6,
K7,L5,L6,L7,

M5,M6,M7,

N4,N8

A1,A11,B1,

B9,B11,C1,

C2,C10,C11,

H1,H3,H9,

H10,N1,N2,

N5,N6,N7
N10,N11,P1,

P2,P5,P7,

P11,R2,R5,

R7

Ground Ground for the device.

– No Connects. Not Internally connected to the die.

18M,36M,72M, 144M and 288M are address expansion pins and
are not internally connected to the die.

Functional Overview

The CY7C1379B is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN

). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t

Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.

Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
deselected in order to load a new address for the next
operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read

) is 6.5 ns (133-MHz device).

CDV

, CE2, CE3) active at the rising edge of the clock. If Clock

1

) is active LOW and ADV/LD is asserted LOW,

). BW

can be used to

[A:D]

). All

, CE2, CE3) and an

1

) simplify depth expansion.

should be driven LOW once the device has been

is asserted LOW, (2) CE1, CE2,

are ALL asserted active, (3) the Write Enable input

3

is deasserted HIGH, and 4) ADV/LD is asserted

access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE

is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE

and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.

Burst Read Accesses

The CY7C1379B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD
the state of chip enable inputs or WE

will increment the internal burst counter regardless of

. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address bus

are ALL asserted active, and (3) the Write signal WE

3

is asserted LOW, (2) CE1, CE2,

is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs.

Document #: 38-05438 Rev. *A Page 5 of 15