Cypress CY7C1371D, CY7C1373D User Manual
Features
CY7C1371D
CY7C1373D
18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM with NoBL™ Architecture
Functional Description
[1]
• No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
• Supports up to 133-MHz bus operations with zero wait
states
— Data is transferred on every clock
• Pin-compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V IO power supply (V
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard Pb-free 100-pin TQFP,
Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA
package.
• Three chip enables for simple depth expansion
• Automatic Power down feature available using ZZ mode or
CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability — linear or interleaved burst order
• Low standby power
) pin to enable clock and suspend
DDQ
)
The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18
Synchronous flow through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
with no wait state insertion. The CY7C1371D/CY7C1373D is
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data through the
SRAM, especially in systems that require frequent Write-Read
transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BW
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
) and a Write Enable (WE) input. All writes are
X
) signal, which when deasserted
, CE2, CE3) and an
1
) provide for easy bank
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 210 175 mA
Maximum CMOS Standby Current 70 70 mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05556 Rev. *F Revised July 09, 2007
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Logic Block Diagram – CY7C1371D (512K x 36)
CY7C1371D
CY7C1373D
ADDRESS
REGISTER
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
D1
D0
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BW
BW
BW
BW
WE
CE1
CE2
CE3
ZZ
CE
A
B
C
D
OE
Logic Block Diagram – CY7C1373D (1M x 18)
BURST
LOGIC
A1'
Q1
A0'
Q0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
DQP
DQP
A
B
C
D
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER
S
E
N
S
E
A
M
P
S
E
CLK
CEN
A0, A1, A
MODE
C
ADV/LD
BW
BW
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER
CE
ADV/LD
A1
A0
D1
D0
BURST
LOGIC
Q1
Q0
A1'
A0'
C
WRITE ADDRESS
REGISTER
S
E
N
INPUT
S
E
A
M
P
S
E
A
B
WRITE REGISTRY
AND DATA COHERENCY
WRITE
DRIVERS
MEMORY
ARRAY
CONTROL LOGIC
REGISTER
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
A
B
READ LOGIC
SLEEP
CONTROL
Document #: 38-05556 Rev. *F Page 2 of 29
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Pin Configurations
100-Pin TQFP Pinout
CY7C1371D
CY7C1373D
BYTE C
BYTE D
DQP
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
DQP
SS
SS
NC
DD
NC
SS
SS
SS
1CE2
A
CE
A
100
999897
1
C
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
D
C
BWDBW
BWBBWACE3VDDV
969594939291908988878685848382
SS
CLKWECEN
OE
ADV/LD
A
A
CY7C1371D
A
A
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
DQP
B
B
B
B
BYTE B
B
B
B
B
B
A
A
A
A
BYTE A
A
A
A
A
A
31323334353637383940414243
A
A
A
A
A1
A0
MODE
NC/288M
NC/144M
SS
DD
V
V
NC/72M
444546
NC/36M
474849
A
A
A
A
50
A
A
A
Document #: 38-05556 Rev. *F Page 3 of 29
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Pin Configurations (continued)
100-Pin TQFP Pinout
CY7C1371D
CY7C1373D
BYTE B
V
DDQ
V
DQ
DQ
V
V
DDQ
DQ
DQ
V
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQP
V
V
DDQ
NC
NC
NC
SS
NC
NC
SS
NC
DD
NC
SS
SS
NC
SS
NC
NC
NC
1CE2
A
100
A
999897
CE
NC
1
2
3
4
5
6
7
8
B
9
B
10
11
12
B
13
B
14
15
16
17
18
B
19
B
20
21
22
B
23
B
24
B
25
26
27
28
29
30
BBWA
NC
BW
969594939291908988878685848382
CE3VDDV
SS
CLKWECEN
OE
ADV/LD
A
A
A
CY7C1373D
A
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
A
A
A
A
A
BYTE A
A
A
A
A
31323334353637383940414243
A
A
A
A
A1
A0
MODE
NC/288M
NC/144M
SS
DD
V
V
NC/72M
444546
NC/36M
474849
A
A
A
A
50
A
A
A
Document #: 38-05556 Rev. *F Page 4 of 29
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Pin Configurations (continued)
CY7C1371D
CY7C1373D
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC/144M
NC
V
DDQ
119-Ball BGA
Pinout
CY7C1371D (512K x 36)
2345671
AA AAV
CE
2
A
AA
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
V
C
C
C
C
C
V
V
BW
V
SS
SS
SS
C
SS
NC V
V
BW
V
V
V
SS
D
SS
SS
SS
D
D
D
D
D
MODE
AAA
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
DD
CLK
NC
CEN
A1
A0
V
DD
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
DDQ
B
A
NC/288M
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
V
NC
NC
DDQ
DDQ
DDQ
ZZ
DDQ
CE
3
AA
DQP
DQ
B
DQ
B
DQ
DQ
V
DQ
DQ
DQ
DQ
B
B
DD
A
A
A
A
B
A
DQP
A
NC/36MNC/72M
NC
B
B
B
B
A
A
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC/144M
NC/72M
V
DDQ
CY7C1373D (1Mx 18)
2
AA AAV
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
A
A
ADV/LD
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
NC
V
SS
V
SS
V
SS
MODE
V
DD
NC
CE
OE
B
A
WE
DD
CLK
NC
CEN
A1
A0
V
DD
V
V
1
V
NC
V
NC
V
BW
V
V
V
NC
ANC/36MA
TDOTCKTDITMS
A
SS
SS
SS
SS
SS
SS
SS
SS
DDQ
A
NC/288M
DQ
V
DQ
V
DQ
V
DQ
V
NC
NC
NC
A
DDQ
A
NC
DDQ
A
NC
DDQ
NC
A
ZZ
DDQ
CE
3
AA
DQP
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
Document #: 38-05556 Rev. *F Page 5 of 29
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Pin Configurations (continued)
165-Ball FBGA Pinout
CY7C1371D (512K x 36)
CY7C1371D
CY7C1373D
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
234 5671
NC/576M
NC/1G
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC/144M
MODE
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CY7C1373D (1M x 18)
234 5671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC/144M
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
SS
891011
A
A
NC
NC
NC DQP
DQ
DQ
DQ
DQ
DQ
B
DQ
B
DQ
B
DQ
B
NC
A
A
A
A
DQ
DQ
DQ
DQ
DQP
NC/288M
DQ
DQ
DQ
DQ
NC
A
B
B
B
B
B
ZZ
A
A
A
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
891011
A
A
NC
NC DQP
A
A
A
A
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
NC/288M
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
Document #: 38-05556 Rev. *F Page 6 of 29
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Pin Definitions
Name IO Description
, A1, A Input-
A
0
BWA, BW
BWC, BW
Synchronous
B
Synchronous
D
Input-
WE Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of the
CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
CY7C1371D
CY7C1373D
ADV/LD
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
ZZ Input-
Asynchronous
DQ
s
IO-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN
address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a new
must be
driven LOW to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN
is active LOW.
Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select/deselect the device.
1
Output Enable, asynchronous input, Active LOW. Combined with the synchronous logic block
inside the device to control the direction of the IO pins. When LOW, the IO pins are allowed to
behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE
is masked during the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
Clock Enable Input, Active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. While deasserting CEN
deselect the device, use CEN
to extend the previous cycle when required.
does not
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull down.
Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by the addresses presented during the previous clock rise of the read cycle. The direction of the
pins is controlled by OE
DQ
and DQP
s
the data portion of a write sequence, during the first clock when emerging from a deselected state,
[A:D]
. When OE is asserted LOW, the pins behave as outputs. When HIGH,
are placed in a tri-state condition.The outputs are automatically tri-stated during
and when the device is deselected, regardless of the state of OE.
DQP
X
IO-
Synchronous
Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQs.
MODE Input Strap Pin Mode Input. Selects the burst order of the device.
or left floating selects interleaved
DD
V
V
V
DD
DDQ
SS
When tied to Gnd selects linear burst sequence. When tied to V
burst sequence.
Power Supply Power supply inputs to the core of the device.
IO Power
Power supply for the IO circuitry.
Supply
Ground Ground for the device.
Document #: 38-05556 Rev. *F Page 7 of 29
[+] Feedback
Pin Definitions (continued)
Name IO Description
TDO JTAG serial
output
Synchronous
TDI JTAG serial
input
Synchronous
TMS JTAG serial
input
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being used, this pin must be left unconnected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not
being used, this pin can be left floating or connected to V
not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not
being used, this pin can be disconnected or connected to V
packages.
CY7C1371D
CY7C1373D
through a pull up resistor. This pin is
DD
. This pin is not available on TQFP
DD
TCK JTAG-
NC – No Connects. Not internally connected to the die. NC/(36 M, 72 M, 144 M, 288M, 576M, 1G)are
Clock
Functional Overview
The CY7C1371D/CY7C1373D is a synchronous flow through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN
nized and all internal states are maintained. All synchronous
operations are qualified with CEN
from the clock rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
1
Enable (CEN
the address presented to the device is latched. The access
can either be a read or write operation, depending on the
status of the Write Enable (WE
byte write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
deselected to load a new address for the next operation.
). If CEN is HIGH, the clock signal is not recog-
CDV
, CE2, CE3) active at the rising edge of the clock. If Clock
) is active LOW and ADV/LD is asserted LOW,
must be driven LOW after the device has been
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be
connected to V
address expansion pins and are not internally connected to the die.
. Maximum access delay
) is 6.5 ns (133-MHz device).
). BWX can be used to conduct
) simplify depth expansion.
. This pin is not available on TQFP packages.
SS
is in progress and allows the requested data to propagate to
the output buffers. The data is available within 6.5 ns
(133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output is tri-stated
immediately.
Burst Read Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
). All
inputs. ADV/LD
into the SRAM, as described in the Single Read Access
section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A
sequence, and wraps around when incremented sufficiently. A
HIGH input on ADV/LD
regardless of the state of chip enable inputs or WE
latched at the beginning of a burst cycle. Therefore, the type
of access (Read or Write) is maintained throughout the burst
sequence.
must be driven LOW to load a new address
is active LOW. After the first
increments the internal burst counter
and A1 in the burst
0
. WE is
Single Read Accesses
A read access is initiated when these conditions are satisfied
at clock rise:
is asserted LOW
•CEN
•CE
, CE2, and CE3 are ALL asserted active
1
• The Write Enable input signal WE
•ADV/LD
The address presented to the address inputs is latched into
the Address Register and presented to the memory array and
control logic. The control logic determines that a read access
Document #: 38-05556 Rev. *F Page 8 of 29
is asserted LOW.
is deasserted HIGH
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see truth table for
are ALL asserted active, and (3) the write signal WE
3
input
X
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CY7C1371D
CY7C1373D
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
signals. The CY7C1371D/CY7C1373D provides byte
X
write capability that is described in the truth table. Asserting
the Write Enable input (WE
) with the selected Byte Write
Select input selectively writes to only the desired bytes. Bytes
not selected during a byte write operation remains unaltered.
A synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Because the CY7C1371D/CY7C1373D is a common IO
device, data must not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQs and DQP
Doing so tri-states the output drivers. As a safety precaution,
) can be deasserted
inputs.
X
DQs and DQPX are automatically tri-stated during the data
portion of a write cycle, regardless of the state of OE
.
Burst Write Accesses
The CY7C1371D/CY7C1373D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD
must be driven LOW to load the initial
address, as described in the Single Write Access section
above. When ADV/LD
rise, the Chip Enables (CE
ignored and the burst counter is incremented. The correct
BW
inputs must be driven in each cycle of the burst write, to
X
write the correct bytes of data.
is driven HIGH on the subsequent clock
, CE2, and CE3) and WE inputs are
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1: A0
DD
)
Third
Address
A1: A0
Fourth
Address
A1: A0
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min Max Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Document #: 38-05556 Rev. *F Page 9 of 29
Sleep mode standby current ZZ > VDD – 0.2V 80 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
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