Cypress CY7C1370D, CY7C1372D User Manual
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b
c
d
C
CY7C1370D
CY7C1372D
18-Mbit (512K x 36/1M x 18) Pipelined
SRAM with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 M Hz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 3.3V core power supply (VDD)
• 3.3V/2.5V I/O power supply(V
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
DDQ
)
Functional Description
The CY7C1370D and CY7C1372D are 3.3V, 512K x 36 and
1M x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL™) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1370D and CY7C1372D are
equipped with the advanced (NoBL) logic requi red to enable
consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1370D and CY7C1372D are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
–BWd for CY7C1370D and BWa–BWb for CY7C1372D)
(BW
a
and a Write Enable (WE
) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
) signal,
Logic Block Diagram-CY7C1370D (512K x 36)
A0, A1, A
MODE
CLK
C
EN
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
C
WRITE ADDRESS
REGISTER 2
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05555 Rev. *F Revised June 28, 2006
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Logic Block Diagram-CY7C1372D (1M x 18)
CY7C1370D
CY7C1372D
CLK
EN
A0, A1, A
MODE
C
ADV/LD
BW
a
BW
b
WE
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
D1D0Q1
A0
BURST
ADV/LD
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
LOGIC
C
Q0
A1'
A0'
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
U
T
P
S
U
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
INPUT
REGISTER 0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
DQs
DQP
DQP
E
E
OE
CE1
CE2
READ LOGIC
CE3
ZZ
Sleep
Control
Selection Guide
250 MHz 200 MHz 167 MHz Unit
Maximum Access Time 2.6 3.0 3.4 ns
Maximum Operating Current 350 300 275 mA
Maximum CMOS Standby Current 70 70 70 mA
Document #: 38-05555 Rev. *F Page 2 of 28
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Pin Configurations
a
100-pin TQFP Pinout
CY7C1370D
CY7C1372D
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWd
BWc
3
CE
VDDV
SS
CLKWECEN
BWa
BWb
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
CY7C1370D
(512K × 36)
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
31323334353637383940414243444546474849
OE
A
ADV/LD
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
DQb
DQb
V
DDQ
V
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
bBWa
3
CE
BW
NC
NC
CY7C1372D
(1M × 18)
VDDV
SS
CLKWECEN
OE
A
A
ADV/LD
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
0
A
A1A
SS
DD
V
V
NC(144)
NC(288)
AAA
A
NC(72)
NC(36)
A
A
A
A
AAA
MODE
1A0
A
AAA
A
DD
SS
V
V
NC(144)
NC(288)
A
NC(36)
NC(72)
A
A
Document #: 38-05555 Rev. *F Page 3 of 28
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Pin Configurations (continued)
CY7C1370D
CY7C1372D
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC/144M
NC
V
DDQ
V
DDQ
NC/576M
NC/1G
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC/144M
NC/72M
V
DDQ
119-Ball BGA
CY7C1370D (512K x 36)
Pinout
2345671
AA AAAV
CE
2
A
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQd
DQ
d
DQP
d
A
NC/72M
TMS
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
BW
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC DQP
CE
1
OE
c
A
WE
V
DD
CLK
NC
d
CEN
A1
A0 V
V
DD
A NC/36M
TCK
ACE3NC
AANC
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
SS
DQ
b
DQ
b
DQ
DQ
DQ
DQ
DQ
DQ
b
b
DD
a
a
a
a
b
a
DQP
NC
A
NCTDI TDO V
DDQ
DQ
b
a
DQ
V
DQ
DQ
V
DQ
DQ
V
DQ
DQ
b
b
DDQ
b
b
DDQ
a
a
DDQ
a
a
NC/288MA
ZZ
DDQ
CY7C1372D (1M x 18)
2345671
AA AAAV
CE
A
NCDQ
DQ
NC
DQ
NC
V
DD
DQ
NC
DQ
NC
DQP
A
A
TMS
2
b
b
b
b
b
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC NCDQP
CE
1
OE
b
ANCNC
WE
V
DD
CLK
NC NC
CEN
A1
A0 V
V
DD
NC/36M
A
AANC
V
SS
V
SS
V
SS
V
SS
NC V
SS
BW
a
V
SS
V
SS
SS
NC
A
TCK
CE
3
NC
DQ
a
DQ
a
DD
NCV
DQ
a
NC V
DQ
a
NC
A
A
NCTDI TDO V
a
DDQ
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
DDQ
NC
DQ
a
NC/288M
ZZ
DDQ
Document #: 38-05555 Rev. *F Page 4 of 28
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Pin Configurations (continued)
165-Ball FBGA Pinout
CY7C1370D (512K x 36)
CY7C1370D
CY7C1372D
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2345671
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
A
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
b
a
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
c
d
NC
TDI
TMS
CY7C1372D (1M x 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
b
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
a
891011
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC DQP
DQ
DQ
DQ
DQ
DQ
b
DQ
b
DQ
b
DQ
b
NC
a
a
a
a
DQ
DQ
DQ
DQ
DQP
NC/288M
DQ
DQ
DQ
DQ
NC
A
NC
NC
b
b
b
b
b
ZZ
a
a
a
a
a
AA
891011
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
A A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC
NC DQP
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
a
a
a
a
A
NCV
NC
NC
NC
NC
NC/288M
A
a
a
a
a
a
ZZ
AA
Document #: 38-05555 Rev. *F Page 5 of 28
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CY7C1370D
CY7C1372D
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
A
BW
a
BW
b
BW
c
BW
d
WE Input-
ADV/LD Input-
CLK Input-
CE
1
CE
2
CE
3
OE Input-
CEN Input-
DQ
S
DQP
X
MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order .
TDO JT AG ser ial
TDI JT AG ser ial
TMS Test Mode
TCK JTAG-Clock Clock input to the JTAG circuitry.
V
DD
Input-
Synchronous
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
controls DQc and DQPc, BWd controls DQd and DQPd.
BW
c
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
Synchronous
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
CLK is only recognized if CEN
Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
and CE2 to select/deselect the device.
CE
1
is active LOW.
Output Enable, active LOW. Comb ined with the synchronous logic block inside the device to
Asynchronous
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE
the data portion of a write sequence, during the first clock when emerging from a deselected
state and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
Synchronous
I/O-
Synchronous
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A
controlled by OE
as outputs. When HIGH, DQ
ically tri-stated during the data portion of a write seq uence, during the fi rst clock when emerging
during the previous clock rise of the read cycle. The direction of the pins is
[17:0]
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automat-
a
from a deselected state, and when the device is deselected, regardless of the state of OE
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally , these signals are identical to DQs. During write
sequences, DQP
and DQP
d
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
a
is controlled by BWd.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
input
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Select
Synchronous
Power Supply Power supply inputs to the core of the device.
should
is masked during
does not
.
Document #: 38-05555 Rev. *F Page 6 of 28
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Pin Definitions (continued)
Pin Name I/O Type Pin Description
V
DDQ
V
SS
NC – No connects. This pin is not connected to the die.
NC/(36M,72M,
144M, 288M,
576M, 1G)
ZZ Input-
I/O Power
Power supply for the I/O circuitry.
Supply
Ground Ground for the device. Should be connected to ground of the system.
– These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M and 1G densities.
ZZ “sleep” Input. This active HIGH input pla ces the device in a non-time critical “s leep” condition
Asynchronous
with data integrity preserved. During normal operation, this pin can be connected to V
floating. ZZ pin has an internal pull-down.
CY7C1370D
CY7C1372D
or left
SS
Introduction
Functional Overview
The CY7C1370D and CY7C1372D are synchronous-pipelined
Burst NoBL SRAMs designed specifically to eliminate wait
states during Write/Read transitions. All synchronous inputs
pass through input registers controlled by the rising edge of
the clock. The clock signal is qualified with the Clock Enable
input signal (CEN
recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.6 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
(CE
, CE2, CE3) active at the rising edge of the clock. If Clock
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE
conduct byte write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE
and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
). If CEN is HIGH, the clock signal is not
) is active LOW and ADV/LD is asserted LOW,
). BWX can be used to
). All
, CE2, CE3) and an
1
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is active LOW. After the first
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1370D and CY7C1372D have an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter i s
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE
. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented is loaded into the
are ALL asserted active, and (3) the write signal WE
3
is asserted LOW, (2) CE1, CE2,
Address Register. The write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
CY7C1372D). In addition, the address for the subsequent
a,b,c,d
/DQP
for CY7C1370D and DQ
a,b,c,d
input signal. This
and DQP
a,b
/DQP
a,b
for
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQ
CY7C1372D) (or a subset for byte write operations, see Write
a,b,c,d
/DQP
for CY7C1370D & DQ
a,b,c,d
a,b
and DQP
/DQP
a,b
for
Cycle Description table for details) inputs is latched into the
device and the write is complete.
The data written during the write operation is controlled by BW
(BW
signals. The CY7C1370D/CY7C1372D provides byte write
for CY7C1370D and BW
a,b,c,d
for CY7C1372D)
a,b
capability that is described in the Write Cycle Description table.
Document #: 38-05555 Rev. *F Page 7 of 28
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CY7C1370D
CY7C1372D
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BW
) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations. Byte write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1370D and CY7C1372D are common I/O
devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE
HIGH before presenting data to the DQ
(DQ
CY7C1372D) inputs. Doing so will tri-state the output drivers.
a,b,c,d
/DQP
for CY7C1370D and DQ
a,b,c,d
As a safety precaution, DQ and DQP (DQ
CY7C1370D and DQ
automatically tri-stated during the data portion of a write cycle,
a,b
/DQP
a,b
) can be deasserted
and DQP
/DQP
a,b
/DQP
a,b,c,d
for CY7C1372D) are
a,b
a,b,c,d
for
for
regardless of the state of OE.
Burst Write Accesses
The CY7C1370D/CY7C1372D has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four write operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD
quent clock rise, the chip enables (CE
WE
inputs are ignored and the burst counter is incremented.
The correct BW
CY7C1372D) inputs must be driven in each cycle of the burst
(BW
a,b,c,d
is driven HIGH on the subse-
, CE2, and CE3) and
1
for CY7C1370D and BW
a,b
for
write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
for the duration of t
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Address
Third
Fourth
Address
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
Fourth
Address
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current ZZ > VDD − 0.2V 80 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
ns
ns
ns
Document #: 38-05555 Rev. *F Page 8 of 28
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CY7C1370D
CY7C1372D
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Address
Operation
Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
NOP/Write Abort (Begin Burst) None L L L L H X L L-H Tri-State
Write Abort (Continue Burst) Next X L H X H X L L-H Tri-State
Ignore Clock Edge (Stall) Current X L X X X X H L-H –
Sleep Mode None X H X X X X X X Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
5. CEN
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when OE
7. OE
is inactive or when the device is deselected, and DQ
and BWX. See Write Cycle Description table for details.
stands for ALL Chip Enables active. BWx = L signifies at least one B yte W rite Select is active, BWx = Valid
signal.
.
= data when OE is active.
s
Document #: 38-05555 Rev. *F Page 9 of 28
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