9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
CY7C1366B
CY7C1367B
Features
• Supports bus operation up to 225 MHz
• Available speed grades are 225, 200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
• 3.3V –5% and +10% core power supply (V
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
DD
)
Functional Description
[1]
The CY7C1366B/CY7C1367B SRAM integrates 262,144 x 36
and 524,288 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (
Enables (CE
and
ADV
(
). Asynchronous inputs include the Output Enable (OE)
GW
and the ZZ pin.
and
2
), Write Enables (
[2]
), Burst Control inputs (
CE
3
BW
), depth-expansion Chip
CE
1
, and
X
), and Global Write
BWE
ADSC, ADSP
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
Address Strobe Controller (
) are active. Subsequent
ADSC
ADSP
) or
burst addresses can be internally generated as controlled by
the Advance pin (
ADV
).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW
causes all bytes to be written.
This device incorporates an
active
LOW
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penalizing system performance.
The CY7C1366B/CY7C1367B operates from a +3.3V core
power supply while all outputs operate with a +3.3V or a +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
,
Selection Guide
225 MHz200 MHz166 MHzUnit
Maximum Access Time2.83.03.5ns
Maximum Operating Current250220180mA
Maximum CMOS Standby Current303030mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.
2. CE
3
Cypress Semiconductor Corporation•3901 North First Street•San Jose, CA 95134•408-943-2600
Document #: 38-05096 Rev. *B Revised February 23, 2004
Address Inputs used to select one of the 256K
address locations. Sampled at the rising edge of the
CLK if
and
CE3
two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with
BWE
to conduct byte writes to the SRAM. Sampled on
the rising edge of CLK.
Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BWX and BWE).
Byte Write Enable Input, active LOW. Sampled on the
rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to
the device. Also used to increment the burst counter
when ADV
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
[2]
CE
3
CE
is HIGH.
1
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
[2]
CE
3
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
CE2 to select/deselect the device.
BGA. Where referenced, CE
throughout this document for BGA.
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are three-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when
emerging from a deselected state.
Advance Input signal, sampled on the rising edge of
CLK, active LOW. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP
ADSP
deasserted HIGH.
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP
Power Supply Power supply inputs to the core of the device.
GroundGround for the core of the device.
I/O Power Sup-
ply
Stati c
output
Synchronous
input
Synchronous
input
Synchronous
CY7C1366
CY7C1367
ZZ “sleep” Input, active HIGH. When asserted HIGH
places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous
cycle. The direction of the pins is controlled by OE
When OE
When HIGH, DQs and DQP
condition.
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear
burst sequence. When tied to V
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data on
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be disconnected. This pin
is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to
V
DD
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to
V
DD
is asserted LOW, the pins behave as outputs.
. This pin is not available on TQFP packages.
. This pin is not available on TQFP packages.
clock rise of the read
are placed in a three-state
X
or left floating selects
DD
.
Document #: 38-05096 Rev. *BPage 7 of 32
CY7C1366
B
B
CY7C1367
CY7C1366B–Pin Definitions (continued)
BGA
NameTQFP
TCK–U4R7JTAG-ClockClock input to the JTAG circuitry. If the JTAG feature
NC14,16,66,
42,39,38
CY7C1367B–Pin Definitions
NameTQFP
, A1 , A37,36,32,33,
A
0
BW
,BW
A
GW
BWE
CLK89K4B6Input-
34,35,43,44,
45,46,47,48,
49,50,80,81,
82,99,100
93,94G3,L5B5,A4Input-
B
88
87M4A7Input-
(2 Chip
Enable)fBGAI/ODescription
is not being utilized, this pin must be connected to V
This pin is not available on TQFP packages.
B1,C1,R1,
T1,T2,J3,
D4,L4,5J,
5R,6T,6U,
B7,C7,R7
A11,B1,C2,
C10,H1,H3,
H9,H10,N2,
N5,N7,N10,
P1,A1,B11,P2
–No Connects. Not internally connected to the die
,R2,N6
BGA
(2-Chip
Enable)fBGAI/ODescription
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
B6,C6,R6,
T6
R6,P6,A2,
A10,A11,B2,
B10,P3,P4,
P8,P9,P10,
P11,R3,R4,
R8,R9,R10,
R11
H4B7Input-
Input-
Synchronous
Synchronous
Synchronous
Address Inputs used to select one of the 512K
address locations. Sampled at the rising edge of the
CLK if
and
CE3
two-bit counter.
or
ADSP
[2]
are sampled active. A1: A0 are fed to the
is active LOW, and CE1, CE2,
ADSC
Byte Write Select Inputs, active LOW. Qualified with
BWE
to conduct byte writes to the SRAM. Sampled on
the rising edge of CLK
.
Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BWX and BWE).
Byte Write Enable Input, active LOW. Sampled on the
Synchronous
rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to
Clock
the device. Also used to increment the burst counter
when ADV
is asserted LOW, during a burst operation.
SS
.
CE
CE
CE
OE
1
2
[2]
3
98E4A3Input-
Synchronous
97B2B3Input-
Synchronous
92–A6Input-
Synchronous
86F4B8Input-
Asynchronous
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
[2]
CE
to select/deselect the device. ADSP is ignored if
3
CE
is HIGH.
1
and
2
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
[2]
to select/deselect the device.
CE
3
and
1
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
CE2 to select/deselect the device.
BGA. Where referenced, CE
throughout this document for BGA.
Not connected for
[2]
is assumed active
3
1
and
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are three-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when
emerging from a deselected state.
Power Supply Power supply inputs to the core of the device.
GroundGround for the core of the device.
Advance Input signal, sampled on the rising edge of
CLK, active LOW. When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP
is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP
is recognized.
ADSP
ZZ “sleep” Input, active HIGH. When asserted HIGH
places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous
cycle. The direction of the pins is controlled by OE
When OE
When HIGH, DQs and DQP
condition.
–No Connects. Not internally connected to the die.
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear
burst sequence. When tied to V
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data on
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be left unconnected. This
pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being utilized, this pin can be left floating or connected to V
through a pull up resistor. This pin is not available on
TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being utilized, this pin can be disconnected or connected to VDD.
This pin is not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature
is not being utilized, this pin must be connected to V
This pin is not available on TQFP packages.
or left floating selects
DD
DD
SS
.
Document #: 38-05096 Rev. *BPage 10 of 32
CY7C1366
B
B
CY7C1367
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1366B/CY7C1367B supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
) and Byte Write Select (BWX) inputs. A Global Write
(BWE
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous
Synchronous Chip Selects CE
asynchronous Output Enable (OE
selection and
is HIGH.
CE
1
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW
, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE
single read cycles are supported.
The CY7C1366B/CY7C1367B is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP
immediately after the next clock rise.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
be initiated with either the Processor Address
)
or the Controller Address Strobe (ADSC
input. A two-bit on-chip wraparound
self-timed write circuitry.
ADSP
[2]
and an
3
is ignored if
, CE2, CE
1
) provide for easy bank
output three-state control.
if OE is active LOW. The only exception
co
signal. Consecutive
or ADSC signals, its output will three-state
is asserted LOW, and (2)
The write signals (GW
ignored during this first cycle.
triggered write accesses require two clock cycles to
ADSP
complete. If GW
data presented to the DQ
sponding address location in the memory core. If GW
, BWE, and
) and ADV inputs are
BW
X
is asserted LOW on the second clock rise, the
inputs is written into the corre-
x
then the write operation is controlled by BWE
signals. The CY7C1366B/CY7C1367B provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE
) with the selected
Byte Write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
).
been provided to simplify the write operations.
Because the CY7C1366B/CY7C1367B is a common I/O
device, the Output Enable (OE
before presenting data to the DQ
three-state the output drivers. As a safety precaution, DQ are
) must be deasserted HIGH
inputs. Doing so will
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE
.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC
is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and
byte(s). ADSC
) are asserted active to conduct a write to the desired
BW
X
triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV
input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address
1
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1366B/CY7C1367B is a common I/O
device, the Output Enable (OE
before presenting data to the DQ
three-state the output drivers. As a safety precaution, DQ
) must be deasserted HIGH
inputs. Doing so will
X
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1366B/CY7C1367BCY7C1367B provides a two-bit
wraparound counter, fed by A
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.
Asserting ADV
LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
, that implements either an
[1:0]
is HIGH,
and
BW
are
X
X
Document #: 38-05096 Rev. *BPage 11 of 32
CY7C1366
B
B
CY7C1367
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
00011011
01001110
10110001
11100100
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
ZZ Mode Electrical Characteristics
ParameterDescriptionTest ConditionsMin.Max.Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Snooze mode standby currentZZ > VDD – 0.2V35mA
Device operation to ZZZZ > VDD – 0.2V2t
ZZ recovery timeZZ < 0.2V2t
ZZ Active to snooze currentThis parameter is sampled2t
ZZ Inactive to exit snooze currentThis parameter is sampled0ns
[ 3, 4, 5, 6, 7, 8]
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00011011
01101100
10110001
11000110
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
inactive for the duration of t
LOW.
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
5. The DQ pins are controlled by the current cycle and the
6. CE
7. The SRAM always initiates a read cycle when ADSP
8.
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW
= L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
1
after the
a don't care for the remainder of the write cycle
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE
OE
is
inactive or when the device is deselected, and all data bits behave as output when
or with the assertion of
ADSP
. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
ADSC
signal. OE is asynchronous and is not sampled with the clock.
OE
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
is active (LOW)
OE
is valid Appropriate write will be done based on which byte write is active.
ReadHHXX
ReadHLHH
Write Byte A – ( DQ
Write Byte B – ( DQ
and DQPA )HLHL
A
and DQPB )HLLH
B
Write All BytesHLLL
Write All BytesLXXX
Document #: 38-05096 Rev. *BPage 13 of 32
CY7C1366
B
B
T
O
CY7C1367
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1366B/CY7C1367B incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1366B/CY7C1367B contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
SS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
0
RUN-TEST/
IDLE
1
DR-SCAN
11
CAPTURE-DR
SHIFT-DR
EXIT1-DR
PAUSE-DR
00
EXIT2-DR
UPDATE-DR
1 0
1
SELECT
0
0
00
1
11
00
0
1
1
IR-SCAN
CAPTURE-IR
SHIFT-IR
EXIT1-IR
PAUSE-IR
EXIT2-IR
UPDATE-IR
1
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
SELECT
0
0
1
1
1
1
0
0
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
012
TDITD
TCK
MSTAP CONTROLLER
Selection
Circuitry
Performing a Tap Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Tap Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
012293031...
Identification Register
012..x...
Boundary Scan Register
S
election
Circuitr
y
Document #: 38-05096 Rev. *BPage 14 of 32
CY7C1366
B
B
CY7C1367
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V
SS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 71-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
t
CS plus tCH).
Document #: 38-05096 Rev. *BPage 15 of 32
CY7C1366
B
B
CY7C1367
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05096 Rev. *BPage 16 of 32
B
B
TAP Timing
123456
T
Test Clock
(TCK)
est Mode Select
(TMS)
Test Data-In
(TDI)
Test Data-Out
(TDO)
t
TMSS
t
TDIS
t
t
TH
TL
t
TMSH
t
TDIH
DON’T CAREUNDEFINED
t
CYC
t
TDOX
t
TDOV
CY7C1366
CY7C1367
TAP AC Switching Characteristics
Over the operating Range
[10, 11]
ParameterSymbolMinMaxUnit
Clock
TCK Clock Cycle Timet
TCK Clock Frequencyt
TCK Clock HIGH timet
TCK Clock LOW timet
Output Times
TCK Clock LOW to TDO Validt
TCK Clock LOW to TDO Invalidt
Setup Times
TMS Set-Up to TCK Clock Riset
TDI Set-Up to TCK Clock Riset
Capture Set-Up to TCK Riset
Hold Times
TMS hold after TCK Clock Riset
TDI Hold after Clock Riset
Capture Hold after Clock Riset
Notes:
t
CS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10.
11. Test conditions are specified using the load in TAP AC test Conditions. t
R/tF
= 1ns.
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
50ns
20MHz
25ns
25ns
5ns
0ns
5ns
5ns
5
5ns
5ns
5ns
Document #: 38-05096 Rev. *BPage 17 of 32
CY7C1366
B
B
T
F
T
F
CY7C1367
3.3V TAP AC Test Conditions
Input pulse levels ....... ........................................VSS to 3.3V
Input rise and fall times...................... ..............................1ns
Test load termination supply voltage .................... ........1.25V
2.5V TAP AC Output Load Equivalent
1.25V
50Ω
DO
Z = 50Ω
O
DD
20p
= 3.3V ±0.165V unless
ParameterDescriptionConditionsMin.Max.Unit
V
V
V
V
V
V
V
I
OH1
OH2
OL1
OL2
IH
IL
X
Output HIGH Voltage IOH = –4.0 mA
IOH = –1.0 mA
Output HIGH Voltage IOH = –100 µA
Output LOW VoltageIOL = 8.0 mA
IOL = 8.0 mA
Output LOW VoltageIOL = 100 µA
Input HIGH Voltage
Input LOW Voltage
Input Load CurrentGND < VIN < V
DDQ
= 3.3V2.4V
DDQ
V
= 2.5V2.0V
DDQ
V
= 3.3V2.9V
DDQ
V
= 2.5V2.1V
DDQ
V
= 3.3V0.4V
DDQ
V
= 2.5V0.4V
DDQ
V
= 3.3V0.2V
DDQ
V
= 2.5V0.2V
DDQ
V
= 3.3V2.0VDD + 0.3V
DDQ
V
= 2.5V1.7VDD + 0.3V
DDQ
V
= 3.3V–0.50.7V
DDQ
V
= 2.5V–0.30.7V
DDQ
–55µA
to 2.5V
SS
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Note:
12. All voltages referenced to V
Document #: 38-05096 Rev. *BPage 18 of 32
SS (GND).
(256K x36)
001001
0101001010
000000000000
100110010110
0000011010000000110100
11
Cy7c1366B
Cy7c1367B
(512K x18)Description
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
CY7C1366
B
B
CY7C1367
Scan Register Sizes
Register NameBit Size (x36)Bit Size (x18)
Instruction
Bypass
ID
Boundary Scan Order
33
11
3232
7171
Identification Codes
INSTRUCTIONCODEDESCRIPTION
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
000
001
010
011
100
101
110
111
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order
CY7C1366B (256K x 36)CY7C1367B (512K x 18)
BALL IDSignal
BIT#
1
K4
2H4 GW
3M4BWE
NameBIT# BALL ID
CLK37P4A01
38N4A12H4GW38N4A1
39R6A3M4BWE39R6A
4F4 OE40T5A4F4OE40T5A
5B4ADSC
6A4ADSP
7G4ADV
41T3A5B4ADSC41T3A
42R2A6A4ADSP42R2A
43R3MODE7G4ADV43R3MODE
8C3 A 44 P2 DQP
9B3 A 45 P1 DQ
10D6DQP
11H7DQ
12G6DQ
13E6DQ
14D7DQ
15E7DQ
16F6DQ
17G7DQ
18H6DQ
46L2DQ
B
47K1DQ
B
48N2DQ
B
49N1DQ
B
50M2DQ
B
51L1DQ
B
52K2DQ
B
53InternalInternal17G7DQ
B
54H1DQ
B
Signal
NameBIT#BALL ID
K4
D
D
D
D
D
D
D
D
D
C
8C3A44InternalInternal
9B3A45InternalInternal
10T2A46InternalInternal
11InternalInternal47InternalInternal
12InternalInternal48P2DQP
13InternalInternal49N1DQ
14D6DQP
15E7DQ
16F6DQ
18H6DQ
Signal
NameBIT#BALL ID
CLK37P4A0
A
A
A
A
A
50M2DQ
51L1DQ
52K2DQ
53InternalInternal
54H1DQ
Signal
Name
B
B
B
B
B
B
Document #: 38-05096 Rev. *BPage 19 of 32
CY7C1366
B
B
CY7C1367
119-Ball BGA Boundary Scan Order (continued)
CY7C1366B (256K x 36)CY7C1367B (512K x 18)
BALL IDSignal
BIT#
NameBIT# BALL ID
19T7ZZ55G2DQ
20K7DQ
21L6DQ
22N6DQ
23P7DQ
24N7DQ
25M6DQ
26L7DQ
27K6DQ
28P6DQP
56E2DQ
A
57D1DQ
A
58H2DQ
A
59G1DQ
A
60F2DQ
A
61E1DQ
A
62D2DQP
A
63C2A27InternalInternal63C2A
A
64A2A28InternalInternal64A2A
A
29T4A65E4CE
30A3A66B2CE
31C5A67L3BW
32B5A68G3BW
33A5A69G5BW
34C6A70L5BW
35A6A71InternalInternal35A6A71InternalInternal
36B6A36B6A
Signal
NameBIT#BALL ID
C
C
C
C
C
C
C
C
1
2
D
C
B
A
19T7ZZ55G2DQ
20K7DQ
21L6DQ
22N6DQ
23P7DQ
24InternalInternal60InternalInternal
25InternalInternal61InternalInternal
26InternalInternal62InternalInternal
29T6A65E4CE
30A3A66B2CE
31C5A67InternalInternal
32B5A68InternalInternal
33A5A69G3BW
34C6A70L5BW
Signal
NameBIT#BALL ID
A
A
A
A
56E2DQ
57D1DQ
58InternalInternal
59InternalInternal
Signal
Name
B
B
B
1
2
B
A
165-Ball fBGA Boundary Scan Order
CY7C1366B (256K x 36) CY7C1367B (512K x 18)
BIT# BALL ID
NameBIT#BALL ID
1B6CLK37R6A01B6CLK37R6A0
Signal
2B7GW
3A7BWE
4B8OE
5A8ADSC
6B9ADSP
7A9ADV
38P6A12B7GW38P6A1
39R4A3A7BWE39R4A
40P4A4B8OE40P4A
41R3A5A8ADSC41R3A
42P3A6B9ADSP42P3A
43R1MODE7A9ADV43R1MODE
8B10 A 44 N1 DQP
9A10 A 45 L2 DQ
10C11DQP
11E10DQ
12F10DQ
13G10DQ
14D10DQ
15D11DQ
16E11DQ
17F11DQ
46K2DQ
B
47J2DQ
B
48M2DQ
B
49M1DQ
B
50L1DQ
B
51K1DQ
B
52J1DQ
B
53InternalInternal17F11DQ
B
Signal
NameBIT# BALL ID
D
D
D
D
D
D
D
D
D
8B10A44InternalInternal
9A10A45InternalInternal
10A11A46InternalInternal
11InternalInternal47InternalInternal
12InternalInternal48N1DQP
13InternalInternal49M1DQ
14C11DQP
15D11DQ
16E11DQ
Signal
NameBIT#BALL ID
A
A
A
A
50L1DQ
51K1DQ
52J1DQ
53InternalInternal
Signal
Name
B
B
B
B
B
Document #: 38-05096 Rev. *BPage 20 of 32
B
B
165-Ball fBGA Boundary Scan Order (continued)
CY7C1366B (256K x 36) CY7C1367B (512K x 18)
BIT# BALL ID
18G11DQ
NameBIT#BALL ID
54G2DQ
B
19H11ZZ55F2DQ
Signal
20J10DQ
21K10DQ
22L10DQ
23M10DQ
24J11DQ
25K11DQ
26L11DQ
27M11DQ
28N11DQP
56E2DQ
A
57D2DQ
A
58G1DQ
A
59F1DQ
A
60E1DQ
A
61D1DQ
A
62C1DQP
A
63B2A27InternalInternal63B2A
A
64A2A28InternalInternal64A2A
A
29R11A65A3CE
30R10A66B3CE
31P10A67B4BW
32R9A68A4BW
33P9A69A5BW
34R8A70B5BW
35P8A71A6CE
36P11A36P11A
Signal
NameBIT# BALL ID
C
C
C
C
C
C
C
C
C
1
2
D
C
B
A
3
18G11DQ
19H11ZZ55F2DQ
20J10DQ
21K10DQ
22L10DQ
23M10DQ
24InternalInternal60InternalInternal
25InternalInternal61InternalInternal
26InternalInternal62InternalInternal
29R11A65A3CE
30R10A66B3CE
31P10A67InternalInternal
32R9A68InternalInternal
33P9A69A4BW
34R8A70B5BW
35P8A71A6CE
CY7C1366
CY7C1367
Signal
NameBIT#BALL ID
A
A
A
A
A
54G2DQ
56E2DQ
57D2DQ
58InternalInternal
59InternalInternal
Signal
Name
B
B
B
B
1
2
B
A
3
Document #: 38-05096 Rev. *BPage 21 of 32
CY7C1366
B
B
CY7C1367
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
Relative to GND........ –0.5V to +4.6V
DD
DC Voltage Applied to Outputs
in three-state ....................................... –0.5V to V
DC Input Voltage....................................–0.5V to V
DDQ
DD
+ 0.5V
+ 0.5V
Electrical Characteristics Over the Operating Range
Current into Outputs (LOW)......................................... 20 mA
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
Industrial-40°C to +85°C
[13, 14]
Ambient
Tem per atur eV
DD
V
toV
DDQ
DD
ParameterDescriptionTest ConditionsMin.Max.Unit
V
V
V
V
V
V
I
I
I
X
OZ
DD
DD
DDQ
OH
OL
IH
IL
Power Supply Voltage3.1353.6V
I/O Supply VoltageV
Output HIGH VoltageV
Output LOW VoltageV
Input HIGH Voltage
Input LOW Voltage
[13]
[13]
Input Load Current except ZZ and MODE
Input Current of MODE Input = V
Input Current of ZZInput = V
Output Leakage Current GND ≤ VI ≤ V
VDD Operating Supply
Current
= 3.3V3.135V
DDQ
V
= 2.5V2.3752.625V
DDQ
= 3.3V, VDD = Min., I
DDQ
V
= 2.5V, VDD = Min., IOH= –1.0 mA2.0V
DDQ
= 3.3V, VDD = Min., I
DDQ
V
= 2.5V, VDD = Min., I
DDQ
V
= 3.3V2.0VDD + 0.3VV
DDQ
V
= 2.5V1.7VDD + 0.3VV
DDQ
V
= 3.3V–0.30.8V
DDQ
V
= 2.5V–0.30.7V
DDQ
GND ≤ VI ≤ V
Input = V
Input = V
V
= Max., I
DD
f = f
MAX
SS
DD
SS
DD
= 1/t
DDQ
Output Disabled–55µA
DDQ,
= 0 mA,
OUT
CYC
= –4.0 mA2.4V
OH
= 8.0 mA0.4V
OL
= 1.0 mA0.4V
OL
–55µA
–30µA
–5µA
30µA
4.4-ns cycle, 225 MHz250mA
5-ns cycle, 200 MHz220mA
DD
5µA
6-ns cycle, 166 MHz180mA
I
SB1
I
SB2
I
SB3
I
SB4
Shaded areas contain advance information.
Notes:
13. Overshoot: V
14. TPower-up: Assumes a linear ramp from 0v to V
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—TTL Inputs
(AC) < VDD +1.5V (Pulse width less than t
IH
V
DD
V
≥ VIH or VIN ≤ V
IN
f = f
MAX
V
DD
≤ 0.3V or VIN > V
V
IN
f = 0
V
DD
V
≤ 0.3V or VIN > V
IN
f = f
MAX
V
DD
V
≥ VIH or VIN ≤ VIL, f = 0
IN
DD
= Max, Device Deselected,
= 1/t
IL
CYC
= Max, Device Deselected,
– 0.3V,
DDQ
= Max, Device Deselected, or
– 0.3V
= 1/t
CYC
DDQ
= Max, Device Deselected,
/2), undershoot: VIL(AC) > -2V (Pulse width less than t
CYC
(min.) within 200ms. During this time VIH < VDD and V
All speeds50mA
All speeds30mA
All speeds50mA
All Speeds40mA
DDQ
< V
DD\
CYC
/2).
V
Document #: 38-05096 Rev. *BPage 22 of 32
CY7C1366
B
B
CY7C1367
Thermal Resistance
[15]
ParameterDescriptionTest Conditions
Θ
JA
Θ
JC
Capacitance
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
[15]
Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.
ParameterDescriptionTest Conditions
C
Input CapacitanceTA = 25°C, f = 1 MHz,
IN
C
CLK
C
I/O
Clock Input Capacitance555pF
Input/Output Capacitance577pF
V
V
= 3.3V.
DD
DDQ
= 2.5V
AC Test Loads and Waveforms
3.3V I/O Test Load
= 50Ω
3.3V
OUTPUT
INCLUDING
5pF
JIG AND
SCOPE
(b)
OUTPUT
Z
2.5V I/O Test Load
= 50Ω
0
VL= 1.5V
(a)
R
L
R = 317Ω
R = 351Ω
TQFP
Package
BGA
Package
fBGA
PackageUnit
252527°C/W
966°C/W
TQFP
Package
BGA
Package
fBGA
PackageUnit
555pF
V
GND
DD
≤ 1ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1ns
(c)
OUTPUT
= 50Ω
Z
0
= 1.25V
V
L
R
L
(a)
Note:
15. Tested initially and after any design or process change that may affect these parameters.
2.5V
OUTPUT
= 50Ω
5pF
INCLUDING
JIG AND
SCOPE
R = 1667Ω
R =1538Ω
(b)
V
DD
GND
≤ 1ns
ALL INPUT PULSES
10%
90%
90%
10%
≤ 1ns
(c)
Document #: 38-05096 Rev. *BPage 23 of 32
CY7C1366
B
B
CY7C1367
Switching Characteristics Over the Operating Range
[20, 21]
225 MHz200 MHz166 MHz
ParameterDescription
t
POWER
VDD(Typical) to the first Access
[16]
Min.MaxMin.MaxMin.Max
111ms
Clock
t
CYC
t
CH
t
CL
Clock Cycle Time4.45.06.0ns
Clock HIGH1.82.02.4ns
Clock LOW1.82.02.4ns
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Data Output Valid After CLK Rise2.83.03.5ns
Data Output Hold After CLK Rise1.251.251.25ns
Clock to Low-Z
Clock to High-Z
OE
LOW to Output Val id
LOW to Output Low-Z
OE
OE HIGH to Output High-Z
[17, 18, 19]
[17, 18, 19]
[17, 18, 19]
[17, 18, 19]
1.251.251.25ns
1.252.81.253.01.253.5ns
2.83.03.5ns
000ns
2.83.03.5ns
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Address Set-up Before CLK Rise1.41.51.5ns
,
ADSC
Set-up Before CLK Rise
ADSP
ADV Set-up Before CLK Rise
GW, BWE, BWX
Set-up Before CLK Rise1.41.51.5ns
1.41.51.5ns
1.41.51.5ns
Data Input Set-up Before CLK Rise1.41.51.5ns
Chip Enable Set-Up Before CLK Rise1.41.51.5ns
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Shaded areas contain advance information.
Notes:
16. This part has a voltage regulator internally; t
can be initiated.
, t
17. t
CHZ
CLZ,tOELZ
18. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
19. This parameter is sampled and not 100% tested.
20. Timing reference level is 1.5V when V
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Address Hold After CLK Rise0.40.50.5ns
,
ADSP
ADV
Hold After CLK Rise
,
GW
BWE, BW
Hold After CLK Rise
ADSC
Hold After CLK Rise
X
0.40.50.5ns
0.40.50.5ns
0.40.50.5ns
Data Input Hold After CLK Rise0.40.50.5ns
Chip Enable Hold After CLK Rise0.40.50.5ns
is the time that the power needs to be supplied above VDD( minimum) initially before a read or write operation
POWER
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
OEHZ
is less than t
OEHZ
= 3.3V and is 1.25V when V
DDQ
OELZ
and t
is less than t
CHZ
DDQ
= 2.5V.
to eliminate bus contention between SRAMs when sharing the same
CLZ
Unit
Document #: 38-05096 Rev. *BPage 24 of 32
B
B
Switching Waveforms
Read Cycle Timing
[22]
t
CYC
CY7C1366
CY7C1367
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
X
CE
ADV
OE
Data Out (DQ)
t
ADS
t
AS
t
CES
A1
t
ADH
t
t
t
t
CL
CH
t
t
ADH
ADS
AH
A2A3
t
t
WEH
WES
CEH
t
t
ADVH
ADVS
ADV suspends burst
High-Z
t
CLZ
t
OEHZ
t
OELZ
t
Q(A1)
t
CO
OEV
t
DOH
Q(A2)
t
CO
Q(A2 + 1)
Single READBURST READ
Q(A2 + 2)
Q(A2 + 3)
Burst continued with
new base address
Deselect
cycle
Q(A2)
Q(A2 + 1)
Q(A3)
Burst wraps around
to its initial state
t
CHZ
DON’T CARE
Notes:
22. On this diagram, when CE
is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05096 Rev. *BPage 25 of 32
UNDEFINED
B
B
Switching Waveforms (continued)
Write Cycle Timing
[22, 23]
t
CYC
CY7C1366
CY7C1367
CLK
ADSP
ADSC
ADDRESS
BWE,
BW
X
GW
CE
ADV
OE
t
t
CL
CH
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
CEH
CES
t
DS
A2A3
t
DH
t
WES
t
WEH
ADSC extends burst
ADV suspends burst
t
ADS
t
ADH
t
WES
t
ADVS
t
WEH
t
ADVH
Data in (D)
High-Z
t
OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READBURST WRITE
Single WRITE
Extended BURST WRITE
DON’T CAREUNDEFINED
Note:
23.
Full width write can be initiated by either GW
Document #: 38-05096 Rev. *BPage 26 of 32
LOW; or by GW HIGH, BWE LOW and BWX LOW.
B
B
Switching Waveforms (continued)
t
D
Read/Write Cycle Timing
[22, 24, 25]
CYC
CY7C1366
CY7C1367
CLK
ADSP
ADSC
ADDRESS
BWE, BW
X
CE
ADV
OE
Data In (D)
t
t
CL
CH
t
t
ADH
ADS
t
t
AH
AS
t
CES
High-Z
A2
t
CEH
t
CLZ
A3
t
WES
t
t
CO
t
OEHZ
t
DS
D(A3)
A1
A4A5A6
t
WEH
DH
t
OELZ
D(A5)D(A6)
ata Out (Q)
High-Z
Back-to-Back READs
Q(A2)Q(A1)
Single WRITE
Q(A4)
Q(A4+1)Q(A4+2)
BURST READ
Q(A4+3)
Back-to-Back
WRITEs
DON’T CARE
Notes:
24.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
is HIGH.
25. GW
UNDEFINED
ADSP
or ADSC
.
Document #: 38-05096 Rev. *BPage 27 of 32
B
B
Switching Waveforms (continued)
A
Z
[26, 27]
Z Mode Timing
CLK
CY7C1366
CY7C1367
t
ZZ
t
ZZREC
ZZ
I
SUPPLY
LL INPUTS
(except ZZ)
Outputs (Q)
t
ZZI
I
DDZZ
High-Z
DON’T CARE
t
RZZI
DESELECT or READ Only
Ordering Information
Speed
(MHz)Ordering Code
225 CY7C1366B-225AC
CY7C1367B-225AC
CY7C1366B-225AI
CY7C1367B-225AI
CY7C1366B-225BGCBG119119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with
CY7C1367B-225BGC
CY7C1366B-225BGIIndustrial
CY7C1367B-225BGI
CY7C1366B-225BZCBB165A165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
CY7C1367B-225BZC
CY7C1366B-225BZIIndustrial
CY7C1367B-225BZI
200 CY7C1366B-200AC
CY7C1367B-200AC
CY7C1366B-200AI
CY7C1367B-200AI
CY7C1366B-200BGCBG119119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with
CY7C1367B-200BGC
CY7C1366B-200BGIIndustrial
CY7C1367B-200BGI
CY7C1366B-200BZCBB165A165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
CY7C1367B-200BZC
CY7C1366B-200BZIIndustrial
CY7C1367B-200BZI
Notes:
26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode.
Package
NamePart and Package Type
A101100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
JTAG
3 Chip Enables with JTAG
A101100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
JTAG
3 Chip Enables with JTAG
Operating
Range
Commercial
Industrial
Commercial
Commercial
Commercial
Industrial
Commercial
Commercial
Document #: 38-05096 Rev. *BPage 28 of 32
B
B
Ordering Information (continued)
Speed
(MHz)Ordering Code
166 CY7C1366B-166ACA101100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
CY7C1367B-166AC
CY7C1366B-166AIIndustrial
CY7C1367B-166AI
CY7C1366B-166BGCBG119119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with
CY7C1367B-166BGC
CY7C1366B-166BGIndustrial
ICY7C1367B-166BGI
CY7C1366B-166BZCBB165A165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
CY7C1367B-166BGC
CY7C1366B-166BZIIndustrial
CY7C1367B-166BGI
Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.
Package
NamePart and Package Type
3 Chip Enables
JTAG
3 Chip Enables with JTAG
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
CY7C1366
CY7C1367
Operating
Range
Commercial
Commercial
Commercial
GAUGE PLANE
R 0.08 MIN.
0.20 MAX.
0.25
0°-7°
0.60±0.15
1.00 REF.
20.00±0.10
22.00±0.20
16.00±0.20
14.00±0.10
100
1
30
3150
0° MIN.
R0.08MIN.
0.20 MAX.
0.20 MIN.
A
DETAIL
81
80
0.30±0.08
0.65
TYP.
51
STAND-OFF
0.05 MIN.
0.15 MAX.
DIMENSIONS ARE IN MILLIMETERS.
12°±1°
(8X)
SEATING PLANE
1.40±0.05
0.20 MAX.
1.60 MAX.
0.10
SEE DETAIL
A
51-85050-*A
Document #: 38-05096 Rev. *BPage 29 of 32
B
B
Package Diagrams (continued)
CY7C1366
CY7C1367
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05096 Rev. *BPage 30 of 32
Package Diagrams (continued)
CY7C1366B
CY7C1367B
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
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