CYPRESS CY7C1366B, CY7C1367B User Manual

查询CY7C1366B-166AC供应商

9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM

CY7C1366B

CY7C1367B

Features

• Supports bus operation up to 225 MHz

• Available speed grades are 225, 200 and 166 MHz

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

• 3.3V –5% and +10% core power supply (V

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.5 ns (for 166-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium



interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

DD

)



Functional Description

[1]

The CY7C1366B/CY7C1367B SRAM integrates 262,144 x 36
and 524,288 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (
Enables (CE
and

ADV

(

). Asynchronous inputs include the Output Enable (OE)

GW

and the ZZ pin.

and

2

), Write Enables (

[2]

), Burst Control inputs (

CE

3

BW

), depth-expansion Chip

CE

1

, and

X

), and Global Write

BWE

ADSC, ADSP

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (
Address Strobe Controller (

) are active. Subsequent

ADSC

ADSP

) or

burst addresses can be internally generated as controlled by
the Advance pin (

ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW
causes all bytes to be written.

This device incorporates an

active

LOW

additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal­izing system performance.

The CY7C1366B/CY7C1367B operates from a +3.3V core
power supply while all outputs operate with a +3.3V or a +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

,

Selection Guide

225 MHz 200 MHz 166 MHz Unit

Maximum Access Time 2.8 3.0 3.5 ns

Maximum Operating Current 250 220 180 mA

Maximum CMOS Standby Current 30 30 30 mA

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

Notes:

1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable.

2. CE

3

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05096 Rev. *B Revised February 23, 2004

B

B

1

A

A
B

A

Logic Block Diagram – CY7C1366B (256K x 36)

CY7C1366

CY7C1367

DQD,DQP

BYTE

DQc,DQP

BYTE

DQB,DQP

BYTE

DQA,DQP

BYTE

ENABLE

REGISTER

SLEEP

CONTROL

ADDRESS
REGISTER

D

C

B

A

2

BURST

COUNTER AND

LOGIC

CLR

PIPELINED

ENABLE

A[1:0]

Q1

Q0

DQD,DQP

WRITE DRIVER

DQc,DQP

WRITE DRIVER

DQB,DQP

WRITE DRIVER

DQA,DQP

WRITE DRIVER

0,A1,A

MODE

ADV

CLK

ADSC
ADSP

BW

BW

BW

BW
BWE

GW

CE
CE
CE

OE

2

D

C

B

A

1
2
3

ZZ

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

Logic Block Diagram – CY7C1367B (512K x 18)

BYTE

BYTE

BYTE

BYTE

D

C

B

A

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQs
DQP
DQP
DQP
DQP

A
B
C
D

0, A1, A

MODE

ADV

CLK

ADSC

ADDRESS
REGISTER

2

Q1

BURST

COUNTER AND

LOGIC

CLR

Q0

[1:0]

A

ADSP

DQ

B ,

DQP

B

BYTE

WRITE DRIVER

DQ

A,

DQPA

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQ
DQP
DQP

s,

BWB

BWA
BWE

GW

CE
CE

CE

OE

ZZ

DQ

B,

DQP

B

BYTE

WRITE REGISTER

DQ

A ,

DQP

A

BYTE

WRITE REGISTER

1
2

3

ENABLE

REGISTER

PIPELINED

ENABLE

SLEEP

CONTROL

Document #: 38-05096 Rev. *B Page 2 of 32

B

B

Pin Configurations

1CE2

A

A

BWDBWCBWBBW

CE

A

CE3VDDV

SS

CLKGWBWEOEADSC

100-pin TQFP Pinout (3 Chip Enables)

A

A

ADSP

ADV

1CE2

A

A

NCNCBWBBW

CE

A

CE3VDDV

SS

CLKGWBWEOEADSC

CY7C1366

CY7C1367

A

A

ADSP

ADV

DQP
DQ

DQ
V
V

DQ

DQ

DQ

DQ
V
V

DQ

DQ

DQ

DQ
V
V

DQ

DQ

DQ

DQ
V
V

DQ

DQ

DQP

DDQ

SSQ

SSQ

DDQ

NC

V

V

DDQ

SSQ

SSQ

DDQ

NC

100999897969594939291908988878685848382

C

1

C

2

C

3
4
5

C

6

C

7

C

8

C

9
10
11

C

12

C

13
14

DD

15
16

SS

17

D

18

D

19
20
21

D

22

D

23

D

24

D

25
26
27

D

28

D

29

D

30

CY7C1366B

(256K X 36)

31323334353637383940414243444546474849

MODE

AAA

1A0

A

A

NC / 72M

NC / 36M

A

DD

V

AAAAA

SS

V

NC / 18M

81

DQP

80

DQ

79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
DQP

B

B

B

B

B

B

B

B

A

A

A

A

A

A

A

A

NC

B

NC
NC

V

DDQ

V

SSQ

NC
NC

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

NC

V

DD

NC

V

SS

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQP

B

NC

V

SSQ

V

DDQ

NC
NC
NC

A

50

A

A

100999897969594939291908988878685848382

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CY7C1367B

(512K x 18)

31323334353637383940414243444546474849

AAA

MODE

1A0

A

A

NC / 72M

NC / 36M

A

DD

V

AAAAA

SS

V

NC / 18M

81

A

80

NC

79

NC

78

V

77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

DDQ

V

SSQ

NC
DQP
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ
DQ
V

DDQ

V

SSQ

DQ
DQ
NC
NC
V

SSQ

V

DDQ

NC
NC
NC

A

A

A

A

A

A

A

A

A

50

A

A

Document #: 38-05096 Rev. *B Page 3 of 32

B

B

Pin Configurations (continued)

V

A

B

C

D

E

F

G
H

J

K

L

M

N

P

R

T

U

NC

NC

DQ

DQ

V

DQ
DQ

V

DQ

DQ

V

DQ

DQ

NC

NC

V

119-ball BGA (2 Chip Enable with JTAG)

CY7C1366B (256K x 36)

2345671

DDQ

DDQ

DDQ

DDQ

DDQ

AA AA

CE

2

A

AA

C

D

V

SS

V

SS

V

SS

BW

V

SS

NC V

V

SS

BW

V

SS

V

SS

V

SS

MODE

DQP

C

DQ

C

C

C

D

D

D

D

DQ

DQ
DQ

V

DD

DQ

DQ

DQ

DQ

DQP

C

C

C

C

D

D

D

D

A

AAA

ADSP

ADSC

V

DD

NC

CE

1

OE

ADV

C

GW

DD

CLK

D

NC

BWE

A1

A0

V

DD

A

V

V

V

BW

V

NC

V

BW

V

V

V

NC

TDOTCKTDITMS

SS

SS

SS

SS

SS

SS

SS

SS

CY7C1366

CY7C1367

V

DDQ

A

AA

DQP

DQ

B

DQ

B

DQ
DQ

V

DQ

DQ

DQ

DQ

B

B

DD

A

A

A

A

B

A

DQP

A

NCNC
NC

NC

NC

DQ

DQ

V

DQ
DQ

V

DQ

DQ

V

DQ

DQ

B

B

DDQ

B

B

DDQ

A

A

DDQ

A

A

B

A

NC

ZZ

V

DDQ

CY7C1367B (512K x 18)

2

A

B

C

D

G

H

K

M

N

R

U

V

DDQ

NC

NC

B

V

NC

DDQ

E

F

NC

DQ

B

V

J

DDQ

NC

L

P

DQ

V

DQ

B

DDQ

B

NC

NC

V

NC

DDQ

T

AA AA

CE

2

NCDQ

DQ

B

NC

DQ

B

NC

V

DD

DQ

B

NC

DQ

B

NC

DQP

B

A

345671

ADSP

A

AA

V

SS

V

SS

V

SS

BW

B

V

SS

NC V

V

SS

V

SS

V

SS

V

SS

V

SS

MODE

ADSC

V

DD

NC

CE

1

OE

ADV

GW

DD

CLK

NC

BWE

A1

A0

V

DD

A

V

V

V

V

V

NC

V

BW

V

V

V

NC

SS

SS

SS

SS

SS

SS

A

SS

SS

SS

ANCA

TDOTCKTDITMS

A

AA

DQP

NC

DQ

NC

DQ

V

DD

NC

DQ

NC

DQ

NC

A

AA

NC

V

DDQ

NC

NC

NC

A

DQ

A

V

DQ

V

DQ

V

DQ

DDQ

A

NC

DDQ

A

NC

DDQ

NC

A

A

A

A

A

NC

ZZ

V

DDQ

Document #: 38-05096 Rev. *B Page 4 of 32

B

B

Pin Configurations (continued)

234 5671

NC / 288M

A

B

C

D

G

H

K

M

N

R

A

NC

DQP

C

DQ

C

E
F

DQ

DQ

DQ

C

C

C

NC

J

L

P

DQ

DQ

DQ

DQ

DQP

NC

D

D

D

D

D

MODE

A

NC

DQ

C

DQ

C

DQ

C

DQ

C

V

SS

DQ

D

DQ

D

DQ

D

DQ

D

NC

NC / 72M

NC / 36M

CE

CE

V

V

V

V

V

NC

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

CY7C1366

CY7C1367

165-ball fBGA (3 Chip Enable)

CY7C1366B (256K x 36)

891011

BW

1

BW

2

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

BW

C

D

BW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

B

A

CE

3

CLK

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC / 18M

A1

A0

BWE

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCK

ADSC

ADV

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

V

V

V

V

V

V

V

V

V

V

A

A

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

A

A

NC DQP

DQ

B

DQ

B

DQ

B

DQ

B

NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

NC

NC / 144M

B

DQ

B

DQ

B

DQ

B

DQ

B

ZZ

DQ

A

DQ

A

DQ

A

DQ

A

DQP

A

A

AA

A

B
C
D

E
F
G

H

J
K
L

M

N
P

R

CY7C1367B (512K x 18)

234 5671

NC / 288M

NC

NC

NC

NC V

NC

NC
NC

DQ

B

DQ

B

DQ

B

DQ

B

DQP

B

NC

MODE

A

A

NC

DQ

B

DQ

B

DQ

B

DQ

B

V

SS

NC

NC

NC

NC

NC

NC / 72M

NC / 36M

CE
CE

V

V

V

V

V

V

V

V

V

V

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

BW

1

2

B

NC BW

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

SS

A

A

NC

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

‘V

SS

V

SS

V

SS

V

SS

NC

TDI

TMS

A

CE

3

CLK

V

SS

V

SS

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC / 18M

A1

BWE

GW

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

NC

TDO

TCKA0

891011

ADSC

ADV

OE ADSP

V

SS

V

DD

V

DD

V

DD

V

DD

V

DD

DD

V

DD

V

DD

V

DD

V

SS

V

V

V

V

V

V

V

V

V

V

A

A

DDQ

DDQ

DDQ

DDQ

DDQ

NC

DDQ

DDQ

DDQ

DDQ

DDQ

A

A

A

A

NC DQP

NC

NC

NC

NC
NC

DQ

A

DQ

A

DQ

A

DQ

A

NC

A

A

NC / 144M

A

DQ

A

DQ

A

DQ

A

DQ

A

ZZ

NCV

NC

NC

NC

NC

A

AA

Document #: 38-05096 Rev. *B Page 5 of 32

B

B

CY7C1366B–Pin Definitions

BGA

(2 Chip

Name TQFP

A

, A1 , A 37,36,32,33

0

,34,35,43,4
4,45,46,47,

48,49,50,81

,82,99,100

BW

A,BWB

BWC,BW

93,94,95,96 L5,G5,G3,L3B5,A5,A4,B4 Input-

D

GW

BWE

88

87 M4 A7 Input-

Enable) fBGA I/O Description

P4,N4,A2,
C2,R2,3A,

B3,C3,T3,
T4,A5,B5,
C5,T5,A6,

B6,C6,R6

R6,P6,A2,

A10,B2,B10,

P3,P4,P8,P9,

P10,P11,R3,

R4,R8,R9,

R10,R11

Input-

Synchronous

Synchronous

H4 B7 Input-

Synchronous

Synchronous

CLK 89 K4 B6 Input-

Clock

CE

1

CE

2

[2]

CE

3

OE

ADV

ADSP

ADSC

98 E4 A3 Input-

Synchronous

97 B2 B3 Input-

Synchronous

92 - A6 Input-

Synchronous

86 F4 B8 Input-

Asynchronous

83 G4 A9 Input-

Synchronous

84 A4 B9 Input-

Synchronous

85

B4 A8 Input-

Synchronous

CY7C1366

CY7C1367

Address Inputs used to select one of the 256K
address locations. Sampled at the rising edge of the

CLK if
and

CE3

two-bit counter.

Byte Write Select Inputs, active LOW. Qualified with
BWE

to conduct byte writes to the SRAM. Sampled on

the rising edge of CLK.
Global Write Enable Input, active LOW. When

asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BWX and BWE).

Byte Write Enable Input, active LOW. Sampled on the
rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to
the device. Also used to increment the burst counter
when ADV

Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE

[2]

CE

3

CE

is HIGH.

1

Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE

[2]

CE

3

Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
CE2 to select/deselect the device.

BGA. Where referenced, CE
throughout this document for BGA.

Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are three-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when
emerging from a deselected state.

Advance Input signal, sampled on the rising edge of
CLK, active LOW. When asserted, it automatically

increments the address in a burst cycle.

Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW. When asserted LOW,

addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP
ADSP
deasserted HIGH.

Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted LOW,

addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP

or

ADSP

[2]

are sampled active. A1: A0 are fed to the

is active LOW, and CE1, CE2,

ADSC

is asserted LOW, during a burst operation.

and

to select/deselect the device. ADSP is ignored if

2

and

to select/deselect the device.

Not connected for

[2]

is assumed active

3

1

1

and

and ADSC are both asserted, only

is recognized. ASDP is ignored when CE1 is

is recognized.

Document #: 38-05096 Rev. *B Page 6 of 32

B

B

CY7C1366B–Pin Definitions (continued)

BGA

Name TQFP

ZZ 64 T7 H11 Input-

DQs, DQPs

V

DD

V

SS

V

SSQ

V

DDQ

MODE 31 R3 R1 Input-

TDO – U5 P7 JTAG serial

TDI – U3 P5 JTAG serial

TMS – U2 R5 JTAG serial

52,53,56,57

,58,59,62,6
3,68,69,72,

73,74,75,

78,79,2,3,6,

7,8,9,

12,13,18,19

,22,23,24,2
5,28,29,51,

80,1,30

15,41,65,91 J2,C4,J4,R

17,40,67,90 D3,E3,F3,

5,10,21,26,

55,60,71,76

4,11,20,27,

54,61,70,77

(2 Chip

Enable) fBGA I/O Description

Asynchronous

K6,L6,M6,

N6,K7,L7,
N7,P7,E6,
F6,G6,H6,
D7,E7,G7,
H7,D1,E1,
G1,H1,E2,
F2,G2,H2,

K1,L1,N1,

P1,K2,L2,

M2,N2,P6,

D6,D2,P2

4,J6

H3,K3,M3,

N3,P3,D5,

E5,F5,H5,

K5,M5,N5,

P5

A1,F1,J1,

M1,U1,A7,

F7,J7,M7,

U7

M11,L11,K11,

J11,J10,K10,
L10,M10,D10
,E10,F10,G10
,D11,E11,F11,

G11,D1,E1,

F1,G1,D2,E2,

F2,G2,J1,K1,
L1,M1,J2,K2,

L2,M2,N11,

C11,C1,N1

D4,D8,E4,E8,
F4,F8,G4,G8,

H4,H8,J4,J8,
K4,K8,L4,L8,

M4,M8

C4,C5,C6,C7,
C8,D5,D6,D7,

E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6

,H7,J5,J6,J7,

K5,K6,K7,L5,
L6,L7,M5,M6,

M7,N4,N8

– – I/O Ground Ground for the I/O circuitry.

C3,C9,D3,D9,

E3,E9,F3,F9,

G3,G9,J3,J9,

K3,K9,L3,L9,
M3,M9,N3,N9

I/O-

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

I/O Power Sup-

ply

Stati c

output

Synchronous

input

Synchronous

input

Synchronous

CY7C1366

CY7C1367

ZZ “sleep” Input, active HIGH. When asserted HIGH

places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.

Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous
cycle. The direction of the pins is controlled by OE
When OE
When HIGH, DQs and DQP
condition.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear

burst sequence. When tied to V
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.

Serial data-out to the JTAG circuit. Delivers data on
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be disconnected. This pin
is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to
V

DD

Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being
utilized, this pin can be disconnected or connected to
V

DD

is asserted LOW, the pins behave as outputs.

. This pin is not available on TQFP packages.

. This pin is not available on TQFP packages.

clock rise of the read

are placed in a three-state

X

or left floating selects

DD

.

Document #: 38-05096 Rev. *B Page 7 of 32

CY7C1366

B

B

CY7C1367

CY7C1366B–Pin Definitions (continued)

BGA

Name TQFP

TCK – U4 R7 JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature

NC 14,16,66,

42,39,38

CY7C1367B–Pin Definitions

Name TQFP

, A1 , A 37,36,32,33,

A

0

BW

,BW

A

GW

BWE

CLK 89 K4 B6 Input-

34,35,43,44,
45,46,47,48,
49,50,80,81,

82,99,100

93,94 G3,L5 B5,A4 Input-

B

88

87 M4 A7 Input-

(2 Chip

Enable) fBGA I/O Description

is not being utilized, this pin must be connected to V
This pin is not available on TQFP packages.

B1,C1,R1,

T1,T2,J3,
D4,L4,5J,

5R,6T,6U,

B7,C7,R7

A11,B1,C2,
C10,H1,H3,
H9,H10,N2,
N5,N7,N10,

P1,A1,B11,P2

– No Connects. Not internally connected to the die

,R2,N6

BGA
(2-Chip
Enable) fBGA I/O Description

P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,

B6,C6,R6,

T6

R6,P6,A2,

A10,A11,B2,

B10,P3,P4,
P8,P9,P10,
P11,R3,R4,

R8,R9,R10,

R11

H4 B7 Input-

Input-

Synchronous

Synchronous

Synchronous

Address Inputs used to select one of the 512K
address locations. Sampled at the rising edge of the

CLK if
and

CE3

two-bit counter.

or

ADSP

[2]

are sampled active. A1: A0 are fed to the

is active LOW, and CE1, CE2,

ADSC

Byte Write Select Inputs, active LOW. Qualified with
BWE

to conduct byte writes to the SRAM. Sampled on

the rising edge of CLK

.

Global Write Enable Input, active LOW. When
asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BWX and BWE).

Byte Write Enable Input, active LOW. Sampled on the

Synchronous

rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.

Clock Input. Used to capture all synchronous inputs to

Clock

the device. Also used to increment the burst counter
when ADV

is asserted LOW, during a burst operation.

SS

.

CE

CE

CE

OE

1

2

[2]

3

98 E4 A3 Input-

Synchronous

97 B2 B3 Input-

Synchronous

92 – A6 Input-

Synchronous

86 F4 B8 Input-

Asynchronous

Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE

[2]

CE

to select/deselect the device. ADSP is ignored if

3

CE

is HIGH.

1

and

2

Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE

[2]

to select/deselect the device.

CE

3

and

1

Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
CE2 to select/deselect the device.

BGA. Where referenced, CE
throughout this document for BGA.

Not connected for

[2]

is assumed active

3

1

and

Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are three-stated, and act as input data pins. OE
is masked during the first clock of a read cycle when
emerging from a deselected state.

Document #: 38-05096 Rev. *B Page 8 of 32

B

B

CY7C1367B–Pin Definitions (continued)

BGA

Name TQFP

(2-Chip
Enable) fBGA I/O Description

CY7C1366

CY7C1367

ADV

ADSP

ADSC

ZZ 64 T7 H11 Input-

DQs, DQPs

V

DD

V

SS

83 G4 A9 Input-

84 A4 B9 Input-

85

58,59,62,63,
68,69,72,73,
8,9,12,13,18
,19,22,23,74

,24

15,41,65,91 C4,J2,J4,

17,40,67,90 D3,D5,E5,

P4 A8 Input-

P7,K7,G7,

E7,F6,H6,
L6,N6,D1,
H1,L1,N1,

E2,G2,K2,

M2,D6,P2

J6,R4

E3,F3,F5,

G5,H3,H5,

K3,K5,L3,

M3,M5,N3,

N5,P3,P5

J10,K10,L10,

M10,D11,

E11,F11,G11

,J1,K1,L1,M1

,D2,E2,F2,

G2,C11,N1

D4,D8,E4,E8

,F4,F8,G4,

G8,H4,H8,J4

,J8,K4,K8,L4

,L8,M4,M8

H2,C4,C5,C6

,C7,C8,D5,
D6,D7,E5,E6
,E7,F5,F6,F7

,G5,G6,G7,

H5,H6,H7,J5

,J6,J7,K5,K6,

K7,L5,L6,L7,

M5,M6,M7,

N4,N8

Synchronous

Synchronous

Synchronous

Asynchronous

I/O-

Synchronous

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

Advance Input signal, sampled on the rising edge of
CLK, active LOW. When asserted, it automatically

increments the address in a burst cycle.

Address Strobe from Processor, sampled on the
rising edge of CLK, active LOW. When asserted LOW,

addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP

is recognized. ASDP is ignored when CE1 is

deasserted HIGH.

Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted LOW,

addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP

is recognized.

ADSP

ZZ “sleep” Input, active HIGH. When asserted HIGH
places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.

Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous

cycle. The direction of the pins is controlled by OE
When OE
When HIGH, DQs and DQP
condition.

is asserted LOW, the pins behave as outputs.

and ADSC are both asserted, only

clock rise of the read

.

are placed in a three-state

X

V

SSQ

Document #: 38-05096 Rev. *B Page 9 of 32

5,10,21,26,

55,60,71,76

– – I/O Ground Ground for the I/O circuitry.

B

B

CY7C1367B–Pin Definitions (continued)

BGA

Name TQFP

(2-Chip
Enable) fBGA I/O Description

CY7C1366

CY7C1367

V

DDQ

MODE 31 R3 R1 Input-

TDO – U5 P7 JTAG serial

TDI – U3 P5 JTAG serial

TMS – U2 R5 JTAG serial

TCK – U4 R7 JTAG-

NC 1,2,3,6,7,14,

4,11,20,27,

54,61,70,77

16,25,28,29,
30,38,39,42,
51,52,53,56,
57,66,75,78,

79,95,96

A1,A7,F1,

F7,J1,J7,

M1,M7,U1,

U7

B1,B7,C1,

C7,D2,D4,

D7,E1,E6,

H2,F2,G1,

G6,H7,J3,

J5,K1,K6,

L4,L2,L7,

M6,N2,L7,

P1,P6,R1,
R5,R7,T1,

T4,U6

C3,C9,D3,

D9,E3,E9,
F3,F9,G3,

G9,J3,J9,K3,

K9,L3,L9,M3,

M9,N3,N9

A5,B1,B4,C1

,C2,C10,D1,

D10,E1,E10,

F1,F10,G1,

G10,H1,H3,

H9,H10,J2,

J11,K2,K11,

L2,L1,M2,

M11,N2,N10,

N5,N7,N11,

P1,A1,B11,

P2,R2,N6

I/O Power

Supply

Stati c

output

Synchronous

input

Synchronous

input

Synchronous

Clock

– No Connects. Not internally connected to the die.

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear

burst sequence. When tied to V
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.

Serial data-out to the JTAG circuit. Delivers data on
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be left unconnected. This
pin is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being uti­lized, this pin can be left floating or connected to V
through a pull up resistor. This pin is not available on
TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK. If the JTAG feature is not being uti­lized, this pin can be disconnected or connected to VDD.
This pin is not available on TQFP packages.

Clock input to the JTAG circuitry. If the JTAG feature
is not being utilized, this pin must be connected to V
This pin is not available on TQFP packages.

or left floating selects

DD

DD

SS

.

Document #: 38-05096 Rev. *B Page 10 of 32

CY7C1366

B

B

CY7C1367

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1366B/CY7C1367B supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte write operations are qualified with the Byte Write Enable

) and Byte Write Select (BWX) inputs. A Global Write

(BWE
Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip
synchronous

Synchronous Chip Selects CE
asynchronous Output Enable (OE
selection and

is HIGH.

CE

1

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW

, BWE) are all deasserted HIGH. ADSP is ignored if CE
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre­sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within t
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE
single read cycles are supported.

The CY7C1366B/CY7C1367B is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP
immediately after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.

be initiated with either the Processor Address

)

or the Controller Address Strobe (ADSC

input. A two-bit on-chip wraparound

self-timed write circuitry.

ADSP

[2]

and an

3

is ignored if

, CE2, CE

1

) provide for easy bank

output three-state control.

if OE is active LOW. The only exception

co

signal. Consecutive

or ADSC signals, its output will three-state

is asserted LOW, and (2)

The write signals (GW
ignored during this first cycle.

triggered write accesses require two clock cycles to

ADSP
complete. If GW
data presented to the DQ
sponding address location in the memory core. If GW

, BWE, and

) and ADV inputs are

BW

X

is asserted LOW on the second clock rise, the

inputs is written into the corre-

x

then the write operation is controlled by BWE
signals. The CY7C1366B/CY7C1367B provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE

) with the selected
Byte Write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has

).

been provided to simplify the write operations.

Because the CY7C1366B/CY7C1367B is a common I/O
device, the Output Enable (OE
before presenting data to the DQ
three-state the output drivers. As a safety precaution, DQ are

) must be deasserted HIGH

inputs. Doing so will

automatically three-stated whenever a write cycle is detected,
regardless of the state of OE

.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi­tions are satisfied: (1) ADSC

is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and
byte(s). ADSC

) are asserted active to conduct a write to the desired

BW

X

triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV

input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address

1

location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.

Because the CY7C1366B/CY7C1367B is a common I/O
device, the Output Enable (OE
before presenting data to the DQ
three-state the output drivers. As a safety precaution, DQ

) must be deasserted HIGH

inputs. Doing so will

X

automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.

Burst Sequences

The CY7C1366B/CY7C1367BCY7C1367B provides a two-bit
wraparound counter, fed by A
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.

Asserting ADV

LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.

, that implements either an

[1:0]

is HIGH,

and

BW

are

X

X

Document #: 38-05096 Rev. *B Page 11 of 32

CY7C1366

B

B

CY7C1367

Interleaved Burst Address Table
(MODE = Floating or VDD)

First

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Truth Table

Snooze mode standby current ZZ > VDD – 0.2V 35 mA

Device operation to ZZ ZZ > VDD – 0.2V 2t

ZZ recovery time ZZ < 0.2V 2t

ZZ Active to snooze current This parameter is sampled 2t

ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[ 3, 4, 5, 6, 7, 8]

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
inactive for the duration of t
LOW.

Second

Address

A1: A0

Third

Address

A1: A0

s, ADSP, and ADSC must remain

after the ZZ input returns

ZZREC

CYC

CYC

CYC

Fourth

Address

A1: A0

ns

ns

ns

Operation Add. Used

CE

CE

CE

2

1

ZZ ADSP ADSC ADV

3

WRITE

CLK DQ

OE

Deselect Cycle,Power-down None H X X L X L X X X L-H three-state

Deselect Cycle,Power-down None L L X L L X X X X L-H three-state

Deselect Cycle,Power-down None L X H L L X X X X L-H three-state

Deselect Cycle,Power-down None L L X L H L X X X L-H three-state

Deselect Cycle,Power-down None L X H L H L X X X L-H three-state

Snooze Mode,Power-down None X X X H X X X X X X three-state

READ Cycle, Begin Burst External L H L L L X X X L L-H Q

READ Cycle, Begin Burst External L H L L L X X X H L-H three-state

WRITE Cycle, Begin Burst External L H L L H L X L X L-H D

READ Cycle, Begin Burst External L H L L H L X H L L-H Q

READ Cycle, Begin Burst External L H L L H L X H H L-H three-state

READ Cycle, Continue Burst Next X X X L H H L H L L-H Q

READ Cycle, Continue Burst Next X X X L H H L H H L-H three-state

Notes:

3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

4. WRITE

5. The DQ pins are controlled by the current cycle and the

6. CE

7. The SRAM always initiates a read cycle when ADSP

8.

9. Table only lists a partial listing of the byte write combinations. Any Combination of BW

= L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.

, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.

1

after the
a don't care for the remainder of the write cycle

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE

OE
is

inactive or when the device is deselected, and all data bits behave as output when

or with the assertion of

ADSP

. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is

ADSC

signal. OE is asynchronous and is not sampled with the clock.

OE

is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks

is active (LOW)

OE

is valid Appropriate write will be done based on which byte write is active.

X

.

Document #: 38-05096 Rev. *B Page 12 of 32

CY7C1366

B

B

CY7C1367

Truth Table

[ 3, 4, 5, 6, 7, 8]

Operation Add. Used

CE

CE

CE

2

1

ZZ ADSP ADSC ADV

3

WRITE

CLK DQ

OE

READ Cycle, Continue Burst Next H X X L X H L H L L-H Q

READ Cycle, Continue Burst Next H X X L X H L H H L-H three-state

WRITE Cycle,Continue Burst Next X X X L H H L L X L-H D

WRITE Cycle,Continue Burst Next H X X L X H L L X L-H D

READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q

READ Cycle, Suspend Burst Current X X X L H H H H H L-H three-state

READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q

READ Cycle, Suspend Burst Current H X X L X H H H H L-H three-state

WRITE Cycle,Suspend Burst Current X X X L H H H L X L-H D

WRITE Cycle,Suspend Burst Current H X X L X H H L X L-H D

Partial Truth Table for Read/Write

Function (CY7C1366B)

[5, 9]

GW BWE

BW

D

BW

C

BW

B

BW

A

Read HHXXXX
Read HLHHHH
Write Byte A – ( DQ

and DQPA ) HLHHHL

A

Write Byte B – ( DQB and DQPB )HLHHLH
Write Bytes B, A H L H H L L
Write Byte C – ( DQ

and DQPC ) HLHLHH

C

Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – ( DQ

and DQPD ) HL LHHH

D

Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX

Truth Table for Read/Write

[5]

Function (CY7C1367B)

GW

BWE

BW

B

BW

A

Read H H X X
Read H L H H
Write Byte A – ( DQ
Write Byte B – ( DQ

and DQPA )HLHL

A

and DQPB )HLLH

B

Write All Bytes H L L L
Write All Bytes L X X X

Document #: 38-05096 Rev. *B Page 13 of 32

CY7C1366

B

B

T

O

CY7C1367

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1366B/CY7C1367B incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using

1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.

The CY7C1366B/CY7C1367B contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V

SS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may alter­nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.

TAP Controller State Diagram

TEST-LOGIC

1

RESET

0

0

RUN-TEST/

IDLE

1

DR-SCAN

1 1

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

0 0

EXIT2-DR

UPDATE-DR

1 0

1

SELECT

0

0

0 0

1

1 1

0 0

0

1

1

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

1

The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.

SELECT

0

0

1

1

1

1

0

0

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif­icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)

TAP Controller Block Diagram

0

Bypass Register

012

TDI TD

TCK

MS TAP CONTROLLER

Selection

Circuitry

Performing a Tap Reset

A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.

At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.

Tap Registers

Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.

Instruction Register

012293031 ...

Identification Register

012..x ...

Boundary Scan Register

S

election

Circuitr

y

Document #: 38-05096 Rev. *B Page 14 of 32

CY7C1366

B

B

CY7C1367

Instruction Register

Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.

When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(V

SS) when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 71-bit-long
register.

The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.

The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.

TAP Instruction Set

Overview

Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc­tions are described in detail below.

The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.

The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.

Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.

When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (

The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still

t

CS plus tCH).

Document #: 38-05096 Rev. *B Page 15 of 32

CY7C1366

B

B

CY7C1367

possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.

Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.

BYPASS

When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.

Reserved

These instructions are not implemented but are reserved for
future use. Do not use these instructions.

Document #: 38-05096 Rev. *B Page 16 of 32

B

B

TAP Timing

123456

T

Test Clock

(TCK)

est Mode Select

(TMS)

Test Data-In

(TDI)

Test Data-Out

(TDO)

t

TMSS

t

TDIS

t

t

TH

TL

t

TMSH

t

TDIH

DON’T CARE UNDEFINED

t

CYC

t

TDOX

t

TDOV

CY7C1366

CY7C1367

TAP AC Switching Characteristics

Over the operating Range

[10, 11]

Parameter Symbol Min Max Unit

Clock

TCK Clock Cycle Time t

TCK Clock Frequency t

TCK Clock HIGH time t

TCK Clock LOW time t

Output Times

TCK Clock LOW to TDO Valid t

TCK Clock LOW to TDO Invalid t

Setup Times

TMS Set-Up to TCK Clock Rise t

TDI Set-Up to TCK Clock Rise t

Capture Set-Up to TCK Rise t

Hold Times

TMS hold after TCK Clock Rise t

TDI Hold after Clock Rise t

Capture Hold after Clock Rise t

Notes:

t

CS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

10.

11. Test conditions are specified using the load in TAP AC test Conditions. t

R/tF

= 1ns.

TCYC

TF

TH

TL

TDOV

TDOX

TMSS

TDIS

CS

TMSH

TDIH

CH

50 ns

20 MHz

25 ns

25 ns

5ns

0ns

5ns

5ns

5

5ns

5ns

5ns

Document #: 38-05096 Rev. *B Page 17 of 32

CY7C1366

B

B

T

F

T

F

CY7C1367

3.3V TAP AC Test Conditions

Input pulse levels ....... ........................................VSS to 3.3V

Input rise and fall times...................... ..............................1ns

Input timing reference levels ...........................................1.5V

Output reference levels...................................................1.5V

Test load termination supply voltage ...............................1.5V

3.3V TAP AC Output Load Equivalent

1.5V

50Ω

DO

Z = 50Ω

O

20p

TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; V

otherwise noted)

[12]

2.5V TAP AC Test Conditions

Input pulse levels ........................................ V

Input rise and fall time ......................................................1ns

Input timing reference levels................... ......................1.25V

Output reference levels .................. ..............................1.25V

Test load termination supply voltage .................... ........1.25V

2.5V TAP AC Output Load Equivalent

1.25V

50Ω

DO

Z = 50Ω

O

DD

20p

= 3.3V ±0.165V unless

Parameter Description Conditions Min. Max. Unit

V

V

V

V

V

V

V

I

OH1

OH2

OL1

OL2

IH

IL

X

Output HIGH Voltage IOH = –4.0 mA

IOH = –1.0 mA

Output HIGH Voltage IOH = –100 µA

Output LOW Voltage IOL = 8.0 mA

IOL = 8.0 mA

Output LOW Voltage IOL = 100 µA

Input HIGH Voltage

Input LOW Voltage

Input Load Current GND < VIN < V

DDQ

= 3.3V 2.4 V

DDQ

V

= 2.5V 2.0 V

DDQ

V

= 3.3V 2.9 V

DDQ

V

= 2.5V 2.1 V

DDQ

V

= 3.3V 0.4 V

DDQ

V

= 2.5V 0.4 V

DDQ

V

= 3.3V 0.2 V

DDQ

V

= 2.5V 0.2 V

DDQ

V

= 3.3V 2.0 VDD + 0.3 V

DDQ

V

= 2.5V 1.7 VDD + 0.3 V

DDQ

V

= 3.3V –0.5 0.7 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

–5 5 µA

to 2.5V

SS

Identification Register Definitions

Instruction Field

Revision Number (31:29)

Device Depth (28:24)

Device Width (23:18)

Cypress Device ID (17:12)

Cypress JEDEC ID Code (11:1)

ID Register Presence Indicator (0)

Note:

12. All voltages referenced to V

Document #: 38-05096 Rev. *B Page 18 of 32

SS (GND).

(256K x36)

001 001

01010 01010

000000 000000

100110 010110

00000110100 00000110100

11

Cy7c1366B

Cy7c1367B

(512K x18) Description

Describes the version number.

Reserved for Internal Use

Defines memory type and architecture

Defines width and density

Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

CY7C1366

B

B

CY7C1367

Scan Register Sizes

Register Name Bit Size (x36) Bit Size (x18)

Instruction

Bypass

ID

Boundary Scan Order

33

11

32 32

71 71

Identification Codes

INSTRUCTION CODE DESCRIPTION

EXTEST

IDCODE

SAMPLE Z

RESERVED

SAMPLE/PRELOAD

RESERVED

RESERVED

BYPASS

000

001

010

011

100

101

110

111

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.

Do Not Use: This instruction is reserved for future use.

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.

Do Not Use: This instruction is reserved for future use.

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.

119-Ball BGA Boundary Scan Order

CY7C1366B (256K x 36) CY7C1367B (512K x 18)

BALL IDSignal

BIT#

1

K4

2H4 GW

3M4BWE

Name BIT# BALL ID

CLK 37 P4 A0 1

38 N4 A1 2 H4 GW 38 N4 A1

39 R6 A 3 M4 BWE 39 R6 A

4F4 OE40 T5 A 4 F4 OE 40 T5 A

5B4ADSC

6A4ADSP

7G4ADV

41 T3 A 5 B4 ADSC 41 T3 A

42 R2 A 6 A4 ADSP 42 R2 A

43 R3 MODE 7 G4 ADV 43 R3 MODE

8C3 A 44 P2 DQP

9B3 A 45 P1 DQ

10 D6 DQP

11 H7 DQ

12 G6 DQ

13 E6 DQ

14 D7 DQ

15 E7 DQ

16 F6 DQ

17 G7 DQ

18 H6 DQ

46 L2 DQ

B

47 K1 DQ

B

48 N2 DQ

B

49 N1 DQ

B

50 M2 DQ

B

51 L1 DQ

B

52 K2 DQ

B

53 Internal Internal 17 G7 DQ

B

54 H1 DQ

B

Signal

Name BIT# BALL ID

K4

D

D

D

D

D

D

D

D

D

C

8 C3 A 44 Internal Internal

9 B3 A 45 Internal Internal

10 T2 A 46 Internal Internal

11 Internal Internal 47 Internal Internal

12 Internal Internal 48 P2 DQP

13 Internal Internal 49 N1 DQ

14 D6 DQP

15 E7 DQ

16 F6 DQ

18 H6 DQ

Signal

Name BIT# BALL ID

CLK 37 P4 A0

A

A

A

A

A

50 M2 DQ

51 L1 DQ

52 K2 DQ

53 Internal Internal

54 H1 DQ

Signal

Name

B

B

B

B

B

B

Document #: 38-05096 Rev. *B Page 19 of 32

CY7C1366

B

B

CY7C1367

119-Ball BGA Boundary Scan Order (continued)

CY7C1366B (256K x 36) CY7C1367B (512K x 18)

BALL IDSignal

BIT#

Name BIT# BALL ID

19 T7 ZZ 55 G2 DQ

20 K7 DQ

21 L6 DQ

22 N6 DQ

23 P7 DQ

24 N7 DQ

25 M6 DQ

26 L7 DQ

27 K6 DQ

28 P6 DQP

56 E2 DQ

A

57 D1 DQ

A

58 H2 DQ

A

59 G1 DQ

A

60 F2 DQ

A

61 E1 DQ

A

62 D2 DQP

A

63 C2 A 27 Internal Internal 63 C2 A

A

64 A2 A 28 Internal Internal 64 A2 A

A

29 T4 A 65 E4 CE

30 A3 A 66 B2 CE

31 C5 A 67 L3 BW

32 B5 A 68 G3 BW

33 A5 A 69 G5 BW

34 C6 A 70 L5 BW

35 A6 A 71 Internal Internal 35 A6 A 71 Internal Internal

36 B6 A 36 B6 A

Signal

Name BIT# BALL ID

C

C

C

C

C

C

C

C

1

2

D

C

B

A

19 T7 ZZ 55 G2 DQ

20 K7 DQ

21 L6 DQ

22 N6 DQ

23 P7 DQ

24 Internal Internal 60 Internal Internal

25 Internal Internal 61 Internal Internal

26 Internal Internal 62 Internal Internal

29 T6 A 65 E4 CE

30 A3 A 66 B2 CE

31 C5 A 67 Internal Internal

32 B5 A 68 Internal Internal

33 A5 A 69 G3 BW

34 C6 A 70 L5 BW

Signal

Name BIT# BALL ID

A

A

A

A

56 E2 DQ

57 D1 DQ

58 Internal Internal

59 Internal Internal

Signal

Name

B

B

B

1

2

B

A

165-Ball fBGA Boundary Scan Order

CY7C1366B (256K x 36) CY7C1367B (512K x 18)

BIT# BALL ID

Name BIT# BALL ID

1 B6 CLK 37 R6 A0 1 B6 CLK 37 R6 A0

Signal

2B7GW

3A7BWE

4B8OE

5A8ADSC

6B9ADSP

7A9ADV

38 P6 A1 2 B7 GW 38 P6 A1

39 R4 A 3 A7 BWE 39 R4 A

40 P4 A 4 B8 OE 40 P4 A

41 R3 A 5 A8 ADSC 41 R3 A

42 P3 A 6 B9 ADSP 42 P3 A

43 R1 MODE 7 A9 ADV 43 R1 MODE

8B10 A 44 N1 DQP

9A10 A 45 L2 DQ

10 C11 DQP

11 E10 DQ

12 F10 DQ

13 G10 DQ

14 D10 DQ

15 D11 DQ

16 E11 DQ

17 F11 DQ

46 K2 DQ

B

47 J2 DQ

B

48 M2 DQ

B

49 M1 DQ

B

50 L1 DQ

B

51 K1 DQ

B

52 J1 DQ

B

53 Internal Internal 17 F11 DQ

B

Signal

Name BIT# BALL ID

D

D

D

D

D

D

D

D

D

8 B10 A 44 Internal Internal

9 A10 A 45 Internal Internal

10 A11 A 46 Internal Internal

11 Internal Internal 47 Internal Internal

12 Internal Internal 48 N1 DQP

13 Internal Internal 49 M1 DQ

14 C11 DQP

15 D11 DQ

16 E11 DQ

Signal

Name BIT# BALL ID

A

A

A

A

50 L1 DQ

51 K1 DQ

52 J1 DQ

53 Internal Internal

Signal

Name

B

B

B

B

B

Document #: 38-05096 Rev. *B Page 20 of 32

B

B

165-Ball fBGA Boundary Scan Order (continued)

CY7C1366B (256K x 36) CY7C1367B (512K x 18)

BIT# BALL ID

18 G11 DQ

Name BIT# BALL ID

54 G2 DQ

B

19 H11 ZZ 55 F2 DQ

Signal

20 J10 DQ

21 K10 DQ

22 L10 DQ

23 M10 DQ

24 J11 DQ

25 K11 DQ

26 L11 DQ

27 M11 DQ

28 N11 DQP

56 E2 DQ

A

57 D2 DQ

A

58 G1 DQ

A

59 F1 DQ

A

60 E1 DQ

A

61 D1 DQ

A

62 C1 DQP

A

63 B2 A 27 Internal Internal 63 B2 A

A

64 A2 A 28 Internal Internal 64 A2 A

A

29 R11 A 65 A3 CE

30 R10 A 66 B3 CE

31 P10 A 67 B4 BW

32 R9 A 68 A4 BW

33 P9 A 69 A5 BW

34 R8 A 70 B5 BW

35 P8 A 71 A6 CE

36 P11 A 36 P11 A

Signal

Name BIT# BALL ID

C

C

C

C

C

C

C

C

C

1

2

D

C

B

A

3

18 G11 DQ

19 H11 ZZ 55 F2 DQ

20 J10 DQ

21 K10 DQ

22 L10 DQ

23 M10 DQ

24 Internal Internal 60 Internal Internal

25 Internal Internal 61 Internal Internal

26 Internal Internal 62 Internal Internal

29 R11 A 65 A3 CE

30 R10 A 66 B3 CE

31 P10 A 67 Internal Internal

32 R9 A 68 Internal Internal

33 P9 A 69 A4 BW

34 R8 A 70 B5 BW

35 P8 A 71 A6 CE

CY7C1366

CY7C1367

Signal

Name BIT# BALL ID

A

A

A

A

A

54 G2 DQ

56 E2 DQ

57 D2 DQ

58 Internal Internal

59 Internal Internal

Signal

Name

B

B

B

B

1

2

B

A

3

Document #: 38-05096 Rev. *B Page 21 of 32

CY7C1366

B

B

CY7C1367

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Supply Voltage on V

Relative to GND........ –0.5V to +4.6V

DD

DC Voltage Applied to Outputs

in three-state ....................................... –0.5V to V

DC Input Voltage....................................–0.5V to V

DDQ

DD

+ 0.5V

+ 0.5V

Electrical Characteristics Over the Operating Range

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage........................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-up Current..................................................... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
Industrial -40°C to +85°C

[13, 14]

Ambient

Tem per atur e V

DD

V

to V

DDQ

DD

Parameter Description Test Conditions Min. Max. Unit

V

V

V

V

V

V

I

I

I

X

OZ

DD

DD

DDQ

OH

OL

IH

IL

Power Supply Voltage 3.135 3.6 V

I/O Supply Voltage V

Output HIGH Voltage V

Output LOW Voltage V

Input HIGH Voltage

Input LOW Voltage

[13]

[13]

Input Load Current ex­cept ZZ and MODE

Input Current of MODE Input = V

Input Current of ZZ Input = V

Output Leakage Current GND ≤ VI ≤ V

VDD Operating Supply
Current

= 3.3V 3.135 V

DDQ

V

= 2.5V 2.375 2.625 V

DDQ

= 3.3V, VDD = Min., I

DDQ

V

= 2.5V, VDD = Min., IOH= –1.0 mA 2.0 V

DDQ

= 3.3V, VDD = Min., I

DDQ

V

= 2.5V, VDD = Min., I

DDQ

V

= 3.3V 2.0 VDD + 0.3V V

DDQ

V

= 2.5V 1.7 VDD + 0.3V V

DDQ

V

= 3.3V –0.3 0.8 V

DDQ

V

= 2.5V –0.3 0.7 V

DDQ

GND ≤ VI ≤ V

Input = V

Input = V

V

= Max., I

DD

f = f

MAX

SS

DD

SS

DD

= 1/t

DDQ

Output Disabled –5 5 µA

DDQ,

= 0 mA,

OUT

CYC

= –4.0 mA 2.4 V

OH

= 8.0 mA 0.4 V

OL

= 1.0 mA 0.4 V

OL

–5 5 µA

–30 µA

–5 µA

30 µA

4.4-ns cycle, 225 MHz 250 mA

5-ns cycle, 200 MHz 220 mA

DD

5 µA

6-ns cycle, 166 MHz 180 mA

I

SB1

I

SB2

I

SB3

I

SB4

Shaded areas contain advance information.

Notes:

13. Overshoot: V

14. TPower-up: Assumes a linear ramp from 0v to V

Automatic CE
Power-down
Current—TTL Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—CMOS Inputs

Automatic CE
Power-down
Current—TTL Inputs

(AC) < VDD +1.5V (Pulse width less than t

IH

V

DD

V

≥ VIH or VIN ≤ V

IN

f = f

MAX

V

DD

≤ 0.3V or VIN > V

V

IN

f = 0

V

DD

V

≤ 0.3V or VIN > V

IN

f = f

MAX

V

DD

V

≥ VIH or VIN ≤ VIL, f = 0

IN

DD

= Max, Device Deselected,

= 1/t

IL

CYC

= Max, Device Deselected,

– 0.3V,

DDQ

= Max, Device Deselected, or

– 0.3V

= 1/t

CYC

DDQ

= Max, Device Deselected,

/2), undershoot: VIL(AC) > -2V (Pulse width less than t

CYC

(min.) within 200ms. During this time VIH < VDD and V

All speeds 50 mA

All speeds 30 mA

All speeds 50 mA

All Speeds 40 mA

DDQ

< V

DD\

CYC

/2).

V

Document #: 38-05096 Rev. *B Page 22 of 32

CY7C1366

B

B

CY7C1367

Thermal Resistance

[15]

Parameter Description Test Conditions

Θ

JA

Θ

JC

Capacitance

Thermal Resistance
(Junction to Ambient)

Thermal Resistance
(Junction to Case)

[15]

Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.

Parameter Description Test Conditions

C

Input Capacitance TA = 25°C, f = 1 MHz,

IN

C

CLK

C

I/O

Clock Input Capacitance 5 5 5 pF

Input/Output Capacitance 5 7 7 pF

V
V

= 3.3V.

DD
DDQ

= 2.5V

AC Test Loads and Waveforms

3.3V I/O Test Load

= 50Ω

3.3V

OUTPUT

INCLUDING

5pF

JIG AND

SCOPE

(b)

OUTPUT

Z

2.5V I/O Test Load

= 50Ω

0

VL= 1.5V

(a)

R

L

R = 317Ω

R = 351Ω

TQFP

Package

BGA

Package

fBGA

Package Unit

25 25 27 °C/W

966°C/W

TQFP

Package

BGA

Package

fBGA

Package Unit

555pF

V

GND

DD

≤ 1ns

ALL INPUT PULSES

10%

90%

90%

10%

≤ 1ns

(c)

OUTPUT

= 50Ω

Z

0

= 1.25V

V

L

R

L

(a)

Note:

15. Tested initially and after any design or process change that may affect these parameters.

2.5V

OUTPUT

= 50Ω

5pF

INCLUDING

JIG AND

SCOPE

R = 1667Ω

R =1538Ω

(b)

V

DD

GND

≤ 1ns

ALL INPUT PULSES

10%

90%

90%

10%

≤ 1ns

(c)

Document #: 38-05096 Rev. *B Page 23 of 32

CY7C1366

B

B

CY7C1367

Switching Characteristics Over the Operating Range

[20, 21]

225 MHz 200 MHz 166 MHz

Parameter Description

t

POWER

VDD(Typical) to the first Access

[16]

Min. Max Min. Max Min. Max

1 1 1ms

Clock

t

CYC

t

CH

t

CL

Clock Cycle Time 4.4 5.0 6.0 ns

Clock HIGH 1.8 2.0 2.4 ns

Clock LOW 1.8 2.0 2.4 ns

Output Times

t

CO

t

DOH

t

CLZ

t

CHZ

t

OEV

t

OELZ

t

OEHZ

Data Output Valid After CLK Rise 2.8 3.0 3.5 ns

Data Output Hold After CLK Rise 1.25 1.25 1.25 ns

Clock to Low-Z

Clock to High-Z

OE

LOW to Output Val id

LOW to Output Low-Z

OE

OE HIGH to Output High-Z

[17, 18, 19]

[17, 18, 19]

[17, 18, 19]

[17, 18, 19]

1.25 1.25 1.25 ns

1.25 2.8 1.25 3.0 1.25 3.5 ns

2.8 3.0 3.5 ns

0 0 0ns

2.8 3.0 3.5 ns

Set-up Times

t

AS

t

ADS

t

ADVS

t

WES

t

DS

t

CES

Address Set-up Before CLK Rise 1.4 1.5 1.5 ns

,

ADSC

Set-up Before CLK Rise

ADSP

ADV Set-up Before CLK Rise

GW, BWE, BWX

Set-up Before CLK Rise 1.4 1.5 1.5 ns

1.4 1.5 1.5 ns

1.4 1.5 1.5 ns

Data Input Set-up Before CLK Rise 1.4 1.5 1.5 ns

Chip Enable Set-Up Before CLK Rise 1.4 1.5 1.5 ns

Hold Times

t

AH

t

ADH

t

ADVH

t

WEH

t

DH

t

CEH

Shaded areas contain advance information.

Notes:

16. This part has a voltage regulator internally; t
can be initiated.

, t

17. t

CHZ

CLZ,tOELZ

18. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions

19. This parameter is sampled and not 100% tested.

20. Timing reference level is 1.5V when V

21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

Address Hold After CLK Rise 0.4 0.5 0.5 ns

,

ADSP

ADV

Hold After CLK Rise

,

GW

BWE, BW

Hold After CLK Rise

ADSC

Hold After CLK Rise

X

0.4 0.5 0.5 ns

0.4 0.5 0.5 ns

0.4 0.5 0.5 ns

Data Input Hold After CLK Rise 0.4 0.5 0.5 ns

Chip Enable Hold After CLK Rise 0.4 0.5 0.5 ns

is the time that the power needs to be supplied above VDD( minimum) initially before a read or write operation

POWER

, and t

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

OEHZ

is less than t

OEHZ

= 3.3V and is 1.25V when V

DDQ

OELZ

and t

is less than t

CHZ

DDQ

= 2.5V.

to eliminate bus contention between SRAMs when sharing the same

CLZ

Unit

Document #: 38-05096 Rev. *B Page 24 of 32

B

B

Switching Waveforms

Read Cycle Timing

[22]

t

CYC

CY7C1366

CY7C1367

CLK

ADSP

ADSC

ADDRESS

GW, BWE,BW

X

CE

ADV

OE

Data Out (DQ)

t

ADS

t

AS

t

CES

A1

t

ADH

t

t

t

t

CL

CH

t

t

ADH

ADS

AH

A2 A3

t

t

WEH

WES

CEH

t

t

ADVH

ADVS

ADV suspends burst

High-Z

t

CLZ

t

OEHZ

t

OELZ

t

Q(A1)

t

CO

OEV

t

DOH

Q(A2)

t

CO

Q(A2 + 1)

Single READ BURST READ

Q(A2 + 2)

Q(A2 + 3)

Burst continued with
new base address

Deselect
cycle

Q(A2)

Q(A2 + 1)

Q(A3)

Burst wraps around
to its initial state

t

CHZ

DON’T CARE

Notes:

22. On this diagram, when CE

is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05096 Rev. *B Page 25 of 32

UNDEFINED

B

B

Switching Waveforms (continued)

Write Cycle Timing

[22, 23]

t

CYC

CY7C1366

CY7C1367

CLK

ADSP

ADSC

ADDRESS

BWE,
BW

X

GW

CE

ADV

OE

t

t

CL

CH

t

t

ADH

ADS

t

t

ADH

ADS

t

t

AH

AS

A1

Byte write signals are ignored for first cycle when
ADSP initiates burst

t

t

CEH

CES

t

DS

A2 A3

t

DH

t

WES

t

WEH

ADSC extends burst

ADV suspends burst

t

ADS

t

ADH

t

WES

t

ADVS

t

WEH

t

ADVH

Data in (D)

High-Z

t

OEHZ

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

Data Out (Q)

BURST READ BURST WRITE

Single WRITE

Extended BURST WRITE

DON’T CARE UNDEFINED

Note:

23.

Full width write can be initiated by either GW

Document #: 38-05096 Rev. *B Page 26 of 32

LOW; or by GW HIGH, BWE LOW and BWX LOW.

B

B

Switching Waveforms (continued)

t

D

Read/Write Cycle Timing

[22, 24, 25]

CYC

CY7C1366

CY7C1367

CLK

ADSP

ADSC

ADDRESS

BWE, BW

X

CE

ADV

OE

Data In (D)

t

t

CL

CH

t

t

ADH

ADS

t

t

AH

AS

t

CES

High-Z

A2

t

CEH

t

CLZ

A3

t

WES

t

t

CO

t

OEHZ

t

DS

D(A3)

A1

A4 A5 A6

t

WEH

DH

t

OELZ

D(A5) D(A6)

ata Out (Q)

High-Z

Back-to-Back READs

Q(A2)Q(A1)

Single WRITE

Q(A4)

Q(A4+1) Q(A4+2)

BURST READ

Q(A4+3)

Back-to-Back

WRITEs

DON’T CARE

Notes:

24.

The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by

is HIGH.

25. GW

UNDEFINED

ADSP

or ADSC

.

Document #: 38-05096 Rev. *B Page 27 of 32

B

B

Switching Waveforms (continued)

A

Z

[26, 27]

Z Mode Timing

CLK

CY7C1366

CY7C1367

t

ZZ

t

ZZREC

ZZ

I

SUPPLY

LL INPUTS

(except ZZ)

Outputs (Q)

t

ZZI

I

DDZZ

High-Z

DON’T CARE

t

RZZI

DESELECT or READ Only

Ordering Information

Speed

(MHz) Ordering Code

225 CY7C1366B-225AC

CY7C1367B-225AC

CY7C1366B-225AI
CY7C1367B-225AI

CY7C1366B-225BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

CY7C1367B-225BGC

CY7C1366B-225BGI Industrial

CY7C1367B-225BGI

CY7C1366B-225BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

CY7C1367B-225BZC

CY7C1366B-225BZI Industrial

CY7C1367B-225BZI

200 CY7C1366B-200AC

CY7C1367B-200AC

CY7C1366B-200AI
CY7C1367B-200AI

CY7C1366B-200BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

CY7C1367B-200BGC

CY7C1366B-200BGI Industrial

CY7C1367B-200BGI

CY7C1366B-200BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

CY7C1367B-200BZC

CY7C1366B-200BZI Industrial

CY7C1367B-200BZI

Notes:

26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

27. DQs are in high-Z when exiting ZZ sleep mode.

Package

Name Part and Package Type

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

JTAG

3 Chip Enables with JTAG

A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

3 Chip Enables

JTAG

3 Chip Enables with JTAG

Operating

Range

Commercial

Industrial

Commercial

Commercial

Commercial

Industrial

Commercial

Commercial

Document #: 38-05096 Rev. *B Page 28 of 32

B

B

Ordering Information (continued)

Speed

(MHz) Ordering Code

166 CY7C1366B-166AC A101 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)

CY7C1367B-166AC

CY7C1366B-166AI Industrial

CY7C1367B-166AI

CY7C1366B-166BGC BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with

CY7C1367B-166BGC

CY7C1366B-166BG Industrial

ICY7C1367B-166BGI

CY7C1366B-166BZC BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)

CY7C1367B-166BGC

CY7C1366B-166BZI Industrial

CY7C1367B-166BGI

Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.

Package

Name Part and Package Type

3 Chip Enables

JTAG

3 Chip Enables with JTAG

Package Diagrams

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

CY7C1366

CY7C1367

Operating

Range

Commercial

Commercial

Commercial

GAUGE PLANE

R 0.08 MIN.

0.20 MAX.

0.25

0°-7°

0.60±0.15

1.00 REF.

20.00±0.10

22.00±0.20

16.00±0.20

14.00±0.10

100

1

30

31 50

0° MIN.

R0.08MIN.

0.20 MAX.

0.20 MIN.

A

DETAIL

81

80

0.30±0.08

0.65
TYP.

51

STAND-OFF

0.05 MIN.

0.15 MAX.

DIMENSIONS ARE IN MILLIMETERS.

12°±1°

(8X)

SEATING PLANE

1.40±0.05

0.20 MAX.

1.60 MAX.

0.10

SEE DETAIL

A

51-85050-*A

Document #: 38-05096 Rev. *B Page 29 of 32

B

B

Package Diagrams (continued)

CY7C1366

CY7C1367

119-Lead PBGA (14 x 22 x 2.4 mm) BG119

51-85115-*B

Document #: 38-05096 Rev. *B Page 30 of 32

Package Diagrams (continued)

CY7C1366B

CY7C1367B

165-Ball FBGA (13 x 15 x 1.2 mm) BB165A

51-85122-*C

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05096 Rev. *B Page 31 of 32

© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other r ights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C1366

B

B

CY7C1367

Document History Page

Document Title: CY7C1366B/CY7C1367B 9-Mb (256K x 36/512K x 18) Pipelined DCD Sync SRAM
Document Number: 38-05096

REV. ECN NO. Issue Date

** 117903 08/28/02 RCS New Data Sheet

*A 121066 11/13/02 DSG Updated package drawings 51-85115 (BG 119) to *B and 51-85122

*B 206401 See ECN NJY Removed Preliminary Status(All Pages).

Orig. of
Change Description of Change

(BB165A) to *C.

Updated Pin Definitions.
Removed 250MHz Speed bin and added 225 MHz speed bin.
Added JTAG boundary scan orders.
Added BGA and fBGA packages to the capacitance table.

Document #: 38-05096 Rev. *B Page 32 of 32