Cypress CY7C1365C User Manual

CY7C1365C

9-Mbit (256K x 32) Flow-Through Sync SRAM

Features

• 256K x 32 common I/O

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 6.5 ns (133-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Supports 3.3V I/O level

• Available in JEDEC-standard lead-free 100-Pin TQFP
package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode option

DD

)

DDQ

)

®

Functional Description

[1]

The CY7C1365C is a 256K x 32 synchronous cache RAM
designed to interface with high-speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automati­cally for the rest of the burst access. All synchronous inputs
are gated by registers controlled by a positive-edge-trigg ered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE

1

Control inputs (ADSC
(BW

[A:D], and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE

, ADSP, and ADV), Write Enables

) and the ZZ pin

[2]

3

), Burst

.

The CY7C1365C allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects
an interleaved burst sequence, while a LOW selects a linear
burst sequence. Burst accesses can be initiated with the
Processor Address Strobe (ADSP
Address Strobe (ADSC

) inputs. Address advancement is

controlled by the Address Advancement (ADV

) or the cache Controller

) input.

Addresses and Chip Enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV).

The CY7C1365C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 250 180 mA
Maximum Standby Current 40 40 mA

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is not available on 2 Chip Enable TQFP package.

2.

CE

3

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05690 Rev . *E Revised September 14, 2006

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s

A

Logic Block Diagram-CY7C1365C (256K x 32)

CY7C1365C

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

BW

BW

BW

A

BWE

GW
CE1

CE2
CE3

OE

ADDRESS
REGISTER

BURST

COUNTER

AND LOGIC

CLR

DQ

D

C

B

D

BYTE

BYTE

WRITE REGISTER

WRITE REGISTER

DQ

C

BYTE

WRITE REGISTER

DQ

B

BYTE

WRITE REGISTER

DQ

A

BYTE

WRITE REGISTER

ENABLE

REGISTER

Q1

Q0

A

[1:0]

DQ

D

BYTE

WRITE REGISTER

DQ

C

BYTE

WRITE REGISTER

DQ

B

BYTE

WRITE REGISTER

DQ

A

BYTE

WRITE REGISTER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT
BUFFERS

INPUT

REGISTERS

DQ

ZZ

SLEEP

CONTROL

Document #: 38-05690 Rev. *E Page 2 of 18

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Pin Configurations

100-Pin TQFP Pinout (2 Chip Enable) (AJ version)

C

BWSBBWS

A

DDVSS

A

V

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

A

100

CE

CE

BWSDBWS

99989796959493929190898887868584838281

2

1

A

CY7C1365C

A

BYTE C

BYTE D

V
V

V
V

V
V

V
V

DQ
DQ

DDQ
SSQ

DQ
DQ
DQ
DQ

SSQ
DDQ

DQ
DQ

V
NC

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

SS

NC

1
2

C

3

C

4
5
6

C

7

C

8

C

9

C

10
11
12

C

13

C

14
15

CY7C1365C

16
17
18

D

19

D

20
21
22

D

23

D

24

D

25

D

26
27
28

D

29

D

30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
NC

B
B

B
B
B
B

B
B

A
A

A
A
A
A

A
A

BYTE B

BYTE A

31323334353637383940414243444546474849

AAAAA1A

0

NC

NC

SS

DD

NC

NC

V

V

AAAAA

50

A

A

MODE

Document #: 38-05690 Rev. *E Page 3 of 18

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Pin Configurations (continued)

100-Pin TQFP Pinout (3 Chip Enable) (A version)

A

100

C

BWSBBWS

A

3

CE

VDDV

SS

CLK

GW

BWE

OE

ADSC

ADSP

ADV

A

2

1

A

CE

CE

BWSDBWS

99989796959493929190898887868584838281

CY7C1365C

A

BYTE C

BYTE D

V
V

V
V

V
V

V
V

DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

V

NC

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

SS

NC

1
2

C

3

C

4
5
6

C

7

C

8

C

9

C

10
11
12

C

13

C

14
15

CY7C1365C

16
17
18

D

19

D

20
21
22

D

23

D

24

D

25

D

26
27
28

D

29

D

30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
V

SS

NC
V

DD

ZZ
DQ

DQ
V

DDQ

V

SSQ

DQ
DQ
DQ
DQ
V

SSQ

V

DDQ

DQ
DQ
NC

B
B

B
B
B
B

B
B

A
A

A
A
A
A

A
A

BYTE B

BYTE A

31323334353637383940414243444546474849

AAAAA1A

0

NC

NC

SS

DD

A

NC

V

V

AAAAA

50

A

A

MODE

Document #: 38-05690 Rev. *E Page 4 of 18

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CY7C1365C

Pin Descriptions

Name TQFP I/O Description

A0, A1, A 37,36,32,33,34,35,44,45,46,

47,48,49,50,81,82,99,100
92 (for 2 Chip Enable Version)
43 (for 3 Chip Enable Version)

BW
BW

A, BWB,
C, BWD

93,94,
95,96

GW 88 Input-

BWE 87 Input-

CLK 89 Input-Clock Clock Input. Used to capture all synchronous inputs to the device.

CE

CE

CE

OE

ADV

1

2

3

98 Input-

97 Input-

92 (for 3 Chip Enable Version) Input-

86 Input-

83 Input-

ADSP 84 Input-

ADSC

85 Input-

ZZ 64 Input-

DQs 52,53,56, 57,58,59, 62,63,68,

69,72,73,74,75,78,79,2,3,6,7,
8,9,12,13,18,19,22,23,24,25,
28,29

Input-

Synchronous

Input-

Synchronous

Synchronous

Synchronous

Synchronous

Synchronous

Synchronous

Asynchronous

Synchronous

Synchronous

Synchronous

Asynchronous

I/O-

Synchronous

Address Inputs used to select one of the 256K address
locations. Sampled at the rising edge of the CLK if ADSP

is active LOW, and CE
the 2-bit counter.

, and CE3 are sampled active. A

1, CE2

or ADSC

feed

[1:0]

Byte Write Select Inputs, active LOW. Qualified with BWE to
conduct Byte Writes to the SRAM. Sampled on the rising edge of
CLK.

Global Write Enable Input, active LOW. When asserted LOW on
the rising edge of CLK, a global write is conducted (ALL bytes are
written, regardless of the values on BW

and BWE).

[A:D]

Byte Write Enable Input, active LOW. Sampled on the rising edge
of CLK. This signal must be asserted LOW to conduct a Byte Write.

Also used to increment the burst counter when ADV

is asserted LOW,

during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of

CLK. Used in conjunction with CE
device. ADSP

is ignored

if CE

a new external address is loaded.

and CE3 to select/deselect the

2

is HIGH.

1

is sampled only when

CE

1

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of
CLK. Used in conjunction with CE
device. CE

is sampled only when a new external address is loaded.

2

and CE3 to select/deselect the

1

Chip Enable 3 Input, active LOW. Sampled on the rising edge of
CLK. Used in conjunction with CE
device. CE
CE

is sampled only when a new external address is loaded.

3

is assumed active throughout this document for BGA.

3

and CE2 to select/deselect the

1

Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE

is masked during the first clock of a Read cycle when

emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When

asserted, it automatically increments the address in a burst cycle.

Address Strobe from Processor, sampled on the rising edge of
CLK, active LOW. When asserted LOW , addresses presented to the

device are captured in the address registers. A
into the burst counter. When ADSP
only ADSP

is recognized. ASDP is ignored when

and ADSC are both asserted,

HIGH.

are also loaded

[1:0]

is deasserted

CE

1

Address Strobe from Controller, sampled on the rising edge of
CLK, active LOW. When asserted LOW , addresses presented to the

device are captured in the address registers. A
into the burst counter. When ADSP
only ADSP

is recognized.

and ADSC are both asserted,

are also loaded

[1:0]

ZZ “sleep” Input, active HIGH. When asserted HIGH places the
device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip
data register that is triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory location specified by
the addresses presented during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE

. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs are
placed in a tri-state condition.

Document #: 38-05690 Rev. *E Page 5 of 18

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Pin Descriptions (continued)

Name TQFP I/O Description

V

DD

V

SS

V

DDQ

V

SSQ

MODE 31 Input-

NC 1,30,51,80,14,16,38,39,42,66

15,41,65, 91 Power Supply Power supply inputs to the core of the device.
17,40,67,90 Ground Ground for the core of the device.
4,1 1,20,27,54,61,70,77

5,10,21,26,55,60,71,76 I/O Ground Ground for the I/O circuitry.

43 (for 2 Chip Enable Version)

,

I/O Power

Supply

Static

Power supply for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst

sequence. When tied to V
sequence. This is a strap pin and should remain static during device
operation. Mode Pin has an internal pull-up.

No Connects. Not Internally connected to the die.

or left floating selects interleaved burst

DD

CY7C1365C

Document #: 38-05690 Rev. *E Page 6 of 18

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