Cypress CY7C1364C User Manual

A

s

CY7C1364C

9-Mbit (256K x 32) Pipelined Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• 256K × 32 common I/O architecture

• 3.3V core power supply (V

• 2.5V/3.3V I/O power supply (V

• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel
Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Available in JEDEC-standard lead-free 100-Pin TQFP
package

• TQFP Available with 3-Chip Enable and 2-Chip Enable

• “ZZ” Sleep Mode Option

DD

)

DDQ

)

®

Functional Description

[1]

The CY7C1364C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE

), depth-expansion Chip Enables (CE2 and CE

1

Control inputs (ADSC
(BW
inputs include the Output Enable (OE

, and BWE), and Global Write (GW). Asynchronous

[A:D]

, ADSP, and ADV), Write Enables

) and the ZZ pin.

[2]

3

), Burst

Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC

) are active. Subsequent

) or

burst addresses can be internally generated as controlled by
the Advance pin (ADV

).

Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW

causes all bytes to be written.

LOW

when active

The CY7C1364C operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.

Logic Block Diagram-CY7C1364C (256K x 32)

0, A1, A

MODE

ADV

CLK

ADSC
ADSP

BW

D

BW

BW

BW

BWE

GW

C

B

A

CE

1

CE

2

CE

3

OE

ZZ

SLEEP

CONTROL

Notes:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is not available on 2 Chip Enable TQFP package.

2. CE

3

ADDRESS
REGISTER

D

DQ

BYTE

WRITE REGISTER

C

DQ
BYTE

WRITE REGISTER

B

DQ

BYTE

WRITE REGISTER

DQA

BYTE

WRITE REGISTER

ENABLE

REGISTER

2

BURST

COUNTER

AND

CLR

LOGIC

PIPELINED

ENABLE

A

[1:0]

Q1

Q0

D

DQ

BYTE

WRITE DRIVER

C

DQ

BYTE

WRITE DRIVER

B

DQ

BYTE

WRITE DRIVER

A

DQ

BYTE

WRITE DRIVER

MEMORY

ARRAY

SENSE
AMPS

OUTPUT

REGISTERS

OUTPUT
BUFFERS

E

INPUT

REGISTERS

DQ

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05689 Rev . *E Revised September 14, 2006

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CY7C1364C

Selection Guide

250 MHz 200 MHz 166 MHz Unit

Maximum Access Time 2.8 3.0 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current 40 40 40 mA

Pin Configuration

100-Pin TQFP Pinout (2 Chip Enables) (AJ version)

BYTE C

BYTE D

V

V

V

V

V

V

V

V

DQ
DQ

DDQ
SSQ

DQ
DQ
DQ
DQ

SSQ
DDQ

DQ
DQ

V

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

NC

SS

NC

AACE1CE2BWDBWCBWBBWAA

100999897969594939291908988878685848382

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15
16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

VDDVSSCLKGWBWEOEADSC

CY7C1364C

ADSP

ADVAA

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

81

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SSQ

SSQ
DDQ

SS

DD

DDQ
SSQ

SSQ
DDQ

B
B

B

BYTE B

B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

1

AAA

0

A

A

A

NC

NC

SS

DD

V

V

NC

NC

AAA

A

50

AAA

MODE

Document #: 38-05689 Rev. *E Page 2 of 18

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Pin Configuration (continued)

CY7C1364C

100-Pin TQFP Pinout (3 Chip Enables) (A version)

BYTE C

BYTE D

V

V

V

V

V

V

V

V

DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

V

V
DQ
DQ

DDQ

SSQ

DQ
DQ
DQ
DQ

SSQ

DDQ

DQ
DQ

NC

NC

DD

NC

SS

NC

AACE1CE2BWDBWCBWBBWACE3VDDVSSCLKGWBWEOEADSC

100999897969594939291908988878685848382

1

C
C

2
3
4
5

C
C
C
C

6
7
8
9
10
11

C
C

12
13
14
15

CY7C1364C

16
17

D
D

18
19
20
21

D
D
D
D

22
23
24
25
26
27

D
D

28
29
30

ADSP

ADVAA

81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
V
NC
V
ZZ
DQ
DQ
V
V
DQ
DQ
DQ
DQ
V
V
DQ
DQ
NC

DDQ
SSQ

SSQ
DDQ

SS

DD

DDQ
SSQ

SSQ
DDQ

B
B

B

BYTE B

B
B
B

B
B

A
A

A
A

BYTE A

A
A

A
A

31323334353637383940414243444546474849

1

AAA

0

A

A

A

NC

NC

SS

V

A

NC

AAA

DD

V

A

50

AAA

MODE

Document #: 38-05689 Rev. *E Page 3 of 18

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Pin Definitions

Name TQFP I/O Description

, A1, A 37, 36, 32, 33, 34, 35, 43,

A

0

44, 45, 46, 47, 48, 49, 50,

Input-

Synchronous

81, 82, 99, 100

BW
BW

, BWB

A

, BW

C

D

93, 94, 95, 96 Input-

Synchronous

GW 88 Input-

Synchronous

BWE

87 Input-

Synchronous

CLK 89 Input-

Clock

CE

CE

CE

OE

1

2

3

(for 3 Chip Enable Version)

98 Input-

Synchronous

97 Input-

Synchronous

92

Input-

Synchronous

86 Input-

Asynchronous

ADV 83 Input-

Synchronous

ADSP

84 Input-

Synchronous

ADSC

85 Input-

Synchronous

ZZ 64 Input-

Asynchronous

DQs 52, 53, 56, 57, 58, 59, 62,

63, 68, 69, 72, 73, 74, 75,

I/O-

Synchronous
78, 79, 2, 3, 6, 7, 8, 9, 12,
13, 18, 19, 22, 23, 24, 25,
28, 29

V

DD

V

SS

15, 41, 65, 91 Power Supply Power supply inputs to the core of the device.
17, 40, 67, 90 Ground Ground for the core of the device.

Address Inputs used to select one of the 256K address locations.
Sampled at the rising edge of the CLK if ADSP
and CE

, CE2, and CE3 are sampled active. A

1

Byte Write Select In puts, active L OW. Qualified with BWE to conduct
byte writes to the SRAM. Sampled on the rising edge of CLK.

Global Write Enable Input, active LOW. When asserted LOW on the
rising edge of CLK, a global Write is conducted (ALL bytes are written,
regardless of the values on BW

[A:D]

Byte Write Enable Input, active LOW. Sampled on the rising edge of
CLK. This signal must be asserted LOW to conduct a Byte Write.

Clock Input. Used to capture all synchronous inputs to the device. Also
used to increment the burst counter when ADV
a burst operation.

Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK.
Used in conjunction with CE

is ignored if CE1 is HIGH. CE1 is sampled only when a new

ADSP

and CE3 to select/deselect the device.

2

external address is loaded.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK.

Used in conjunction with

is sampled only when a new external address is loaded.

CE

2

CE

and

1

Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK.
Used in conjunction with CE
device.CE
is sampled only when a new external address is loaded.

is assumed active throughout this document for BGA. CE3

3

and CE2 to select/deselect the

1

Output Enable, asynchronous input, active LOW. Controls the
direction of the I/O pins. When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE

is masked during the first clock of a Read cycle when emerging

from a deselected state.

Advance Input signal, sampled on the rising edge of CLK, active
LOW. When asserted, it automatically increments the address in a burst

cycle.

Address Strobe from Processor, sampled on the rising edge of
CLK, active LOW. When asserted LOW, A is captured in the address

registers. A

are both asserted, only ADSP is recognized. ASDP is ignored

ADSC
when CE

are also loaded into the burst counter. When

[1:0]

is deasserted HIGH.

1

Address Strobe from Controller, sampled on the rising edge of
CLK, active LOW. When asserted LOW, A is captured in the address

registers. A
ADSC

are both asserted, only ADSP is recognized.

are also loaded into the burst counter. When ADSP and

[1:0]

ZZ “sleep” Input, active HIGH. This input, when High places the
device in a non-time-critical “sleep” condition with data integrity
preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data
register that is triggered by the rising edge of CLK. As outputs, they
deliver the data contained in the memory location specified by “A”
during the previous clock rise of the Read cycle. The direction of the
pins is controlled by OE

. When OE is asserted LOW, the pins behave

as outputs. When HIGH, DQ are placed in a tri-state condi ti on.

CY7C1364C

or ADSC is active LOW,

feed the 2-bit counter.

[1:0]

and BWE).

is asserted LOW , during

to select/deselect the device.

CE

3

ADSP

and

Document #: 38-05689 Rev. *E Page 4 of 18

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Pin Definitions (continued)

Name TQFP I/O Description

V

DDQ

V

SSQ

MODE 31 Input-

NC 1, 14, 16, 30, 38, 39, 42,

4, 1 1, 20, 27, 54, 61, 70, 77 I/O Power

Power supply for the I/O circuitry.

Supply

5, 10, 21, 26, 55, 60, 71, 76 I/O Ground Ground for the I/O circuitry.

Selects Burst Order. When tied to GND selects linear burst sequence.

Static

When tied to V
This is a strap pin and should remain static during device operation.

or left floating selects interleaved burst sequence.

DD

Mode pin has an internal pull-up.
No Connects. Not internally connected to the die

51, 66, 80

CY7C1364C

Functional Overview

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.

The CY7C1364C supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.

Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.

Single Read Accesses

This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
(2) CE

1

signals (GW
if CE

is HIGH. The address presented to the address inputs

1

(A) is stored into the address advancement logic and the
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output re gister and
onto the data bus within t
exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE
Consecutive single Read cycles are supported. Once the
SRAM is deselected at clock rise by the chip select and either
ADSP

or ADSC signals, its output will tri-state immediately.

) or the Controller Address Strobe (ADSC).

) inputs. A Global Write

) overrides all Byte Write inputs and writes data to

[A:D]

) provide for easy bank

is ignored if CE

or ADSC is asserted LOW,

, CE2, CE3 are all asserted active, and (3) the Write

, BWE) are all deasserted HIGH. ADSP is ignored

if OE is active LOW. The only

CO

signal.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE

, CE2, CE3 are all asserted active. The address

1

presented to A is loaded into the address register and the

is asserted LOW, and

address advancement logic while being delivered to the RAM
array. The Write signals (GW
inputs are ignored during this first cycle.

ADSP

-triggered Write accesses require two clock cycles to

complete. If GW

is asserted LOW on the second clock rise, the

, BWE, and BW

[A:D]

data presented to the DQ inputs is written into the corre­sponding address location in the memory array. If GW is HIGH ,
then the Write operation is controlled by BWE

and BW
signals. The CY7C1364C provides Byte Write capability that
is described in the Write Cycle Descriptions table. Asserting
the Byte Write Enable input (BWE
Write ( BW
bytes. Bytes not selected during a Byte Write operation will

) input, will selectively write to only the desired

[A:D]

) with the selected Byte

remain unaltered. A synchronous self-timed Write mechanism
has been provided to simplify the Write operations.

Because the CY7C1364C is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQ are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

1

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi­tions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW

, and BW

BWE
the desired byte(s). ADSC

) are asserted active to conduct a Write to

[A:D]

is asserted LOW, (2) ADSP is

, CE2, CE3 are all asserted active,

1

-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the m emory array .
The ADV

input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.

Because the CY7C1364C is a common I/O device, the Output
Enable (OE

) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will tri-state the output drivers. As
a safety precaution, DQs are automatically tri-stated whenever
a Write cycle is detected, regardless of the state of OE

) and ADV

[A:D]

.

,

.

Document #: 38-05689 Rev. *E Page 5 of 18

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CY7C1364C

Burst Sequences

The CY7C1364C provides a two-bit wraparound counter, fed
by A
sequence. The interleaved burst sequence is designed specif­ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.

Asserting ADV
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.

, that implements either an interleaved or linear burst

[1:0]

LOW at clock rise will automatically increment

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW

.

, CE2, CE3, ADSP, and ADSC must

1

after the ZZ input

ZZREC

Interleaved Burst Address Table
(MODE = Floating or V

First

Address

A

[1:0]

Second

Address

A

[1:0]

DD

)

Third

Address

A

[1:0]

00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A

[1:0]

00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10

Second

Address

A

[1:0]

Third

Address

A

[1:0]

ZZ Mode Electrical Characteristics

Parameter Description T est Conditions Min. Max. Unit

I

DDZZ

t

ZZS

t

ZZREC

t

ZZI

t

RZZI

Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ Active to Sleep current This parameter is sampled 2t

CYC

CYC

ZZ Inactive to exit Sleep current This parameter is sampled 0 ns

Fourth

Address

A

[1:0]

Fourth

Address

A

[1:0]

ns
ns
ns

Document #: 38-05689 Rev. *E Page 6 of 18

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