Cypress CY7C1361C, CY7C1363C User Manual
CY7C1361C
CY7C1363C
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Features
• Supports 100, 133-MHz bus operations
• Supports 100-MHz bus operations (Automo tiv e )
• 256K × 36/512K × 18 common I/O
• 3.3V –5% and +10% core power supply (V
• 2.5V or 3.3V I/O power supply (V
• Fast clock-to-output times
— 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
•“ZZ” Sleep Mode option
®
interleaved or linear burst sequences
DDQ
)
DD
)
®
Functional Description
The CY7C1361C/CY7C1363C is a 3 . 3V, 256K x 3 6 / 5 1 2K x 1 8
Synchronous Flow-through SRAMs, respectively designed to
interface with high-speed microprocessors with minimum glue
logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE2 and CE
1
Control inputs (ADSC
and BWE
include the Output Enable (OE
The CY7C1361C/CY7C1363C allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP
cache Controller Address Strobe (ADSC
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1361C/CY7C1363C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
), and Global Write (GW). Asynchronous inputs
, ADSP, and ADV), W rite Enables (BWx,
[1]
) and the ZZ pin.
) inputs. Address
) are active. Subsequent
[2]
), Burst
3
) or the
) or
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 250 180 mA
Maximum CMOS Standby Current Comm/Ind’l 40 40 mA
Automotive
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
2. CE
3
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05541 Rev . *F Revised September 14, 2006
60 mA
[+] Feedback
s
A
B
C
D
A
Logic Block Diagram – CY7C1361C (256K x 36)
A
A
B
CY7C1361C
CY7C1363C
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BW
BW
BWE
GW
CE1
CE2
CE3
ADDRESS
REGISTER
BURST
COUNTER
AND LOGIC
CLR
D
,
DQP
D
D
C
B
A
OE
ZZ
SLEEP
CONTROL
DQ
BYTE
BYTE
WRITE REGISTER
WRITE REGISTER
C
,
DQP
DQ
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
BYTE
WRITE REGISTER
ENABLE
REGISTER
C
A
A
[1:0]
Q1
Q0
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
BYTE
WRITE REGISTER
MEMORY
ARRAY
A
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQ
DQP
DQP
DQP
DQP
Logic Block Diagram – CY7C1363C (512K x 18)
0,A1,A
MODE
ADV
CLK
ADSC
ADSP
B
BW
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ZZ
ADDRESS
REGISTER
DQB,DQP
A
,DQP
DQ
ENABLE
REGISTER
SLEEP
CONTROL
B
A
WRITE REGISTER
WRITE REGISTER
A[1:0]
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
DQB,DQP
B
WRITE DRIVER
DQ
A
,DQP
A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
INPUT
REGISTERS
DQs
DQP
DQP
Document #: 38-05541 Rev. *F Page 2 of 31
[+] Feedback
Pin Configurations
100-Pin TQFP Pinout (3 Chip Enables) (A version)
CY7C1361C
CY7C1363C
DQP
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
VSS/DNU
V
DD
NC
V
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
1CE2
A
A
BWD
BWC
CE
100999897969594939291908988878685848382
C
1
C
2
C
3
4
5
C
6
C
7
C
8
C
9
10
11
C
12
C
13
14
15
16
SS
17
D
18
D
19
20
21
D
22
D
23
D
24
D
25
26
27
D
28
D
29
D
30
BWB
CY7C1361C
(256K x 36)
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
BWA
NC
CE3VDDV
SS
NC
V
SS
CLKGWBWEOEADSC
A
DD
NC
V
ADSP
AAAAA
A
A
ADV
81
DQP
80
DQ
79
DQ
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
B
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
VSS/DNU
V
DD
NC
V
SS
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQP
NC
V
SSQ
V
DDQ
NC
NC
NC
B
B
B
B
B
B
B
B
B
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1363C
(512K x 18)
CE3VDDV
SS
CLKGWBWEOEADSC
ADSP
31323334353637383940414243444546474849
MODE
AAA
1A0
A
A
NC
NC
A
DD
V
NC
AAAAA
SS
V
A
A
ADV
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
50
A
A
Document #: 38-05541 Rev. *F Page 3 of 31
[+] Feedback
Pin Configurations (continued)
100-Pin TQFP Pinout (2 Chip Enables) (AJ Version)
CY7C1361C
CY7C1363C
DQP
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
VSS/DNU
V
DD
NC
V
SS
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
1CE2
A
A
BWD
BWC
CE
BWB
SS
BWA
A
VDDV
100999897969594939291908988878685848382
C
1
C
2
C
3
4
5
C
6
C
7
C
8
C
9
10
11
C
12
C
13
14
15
16
17
D
18
D
19
20
21
D
22
D
23
D
24
D
25
26
27
D
28
D
29
D
30
CY7C1361C
(256K x 36)
31323334353637383940414243444546474849
MODE
AAA
1A0
A
A
NC
NC
SS
DD
V
V
CLKGWBWEOEADSC
AAAAA
NC
NC
ADSP
ADV
A
A
81
DQP
80
DQ
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
DQP
B
B
B
B
B
B
B
B
A
A
A
A
A
A
A
A
B
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
VSS/DNU
V
DD
NC
V
SS
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
DQP
NC
V
SSQ
V
DDQ
NC
NC
NC
B
B
B
B
B
B
B
B
B
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1363C
(512K x 18)
31323334353637383940414243444546474849
1A0
A
A
MODE
AAA
NC
NC
A
VDDV
SS
V
SS
CLKGWBWEOEADSC
AAAAA
DD
NC
NC
V
ADSP
ADV
A
A
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQ
DQ
V
SSQ
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SSQ
DQ
DQ
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
50
A
A
Document #: 38-05541 Rev. *F Page 4 of 31
[+] Feedback
Pin Configurations (continued)
119-Ball BGA Pinout (2 Chip Enables with JTAG)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC/288M
NC/144M
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
NC
NC
V
DDQ
CY7C1361C
CY7C1363C
CY7C1361C (256K x 36)
2345671
AA AA
CE
2
A
AA
DQP
C
DQ
C
DQ
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
DQ
D
DQP
D
A
V
C
C
C
C
C
V
V
BW
V
SS
SS
SS
SS
NC V
V
BW
V
V
V
SS
SS
SS
SS
D
D
D
D
D
MODE
AAA
ADSP
A
AA
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
A
SS
SS
SS
B
SS
SS
A
SS
SS
SS
ADSC
V
DD
NC
CE
1
OE
ADV
C
GW
DD
CLK
D
NC
BWE
A1
A0
V
DD
NC/36MNC/72M
TDOTCKTDITMS
NC
B
B
B
B
B
A
A
A
A
A
V
DDQ
NC/512M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC/72M
V
DDQ
CY7C1363C (512K x 18)
2
AA AA
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
A
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
ADSC
V
DD
NC
CE
1
OE
ADV
B
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A NC/36M A
V
V
V
V
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
A
SS
SS
SS
SS
SS
SS
SS
SS
SS
A
AA
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DDQ
NC/512M
NC/1G
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document #: 38-05541 Rev. *F Page 5 of 31
[+] Feedback
Pin Configurations (continued)
234 5671
V
V
V
V
V
V
V
V
V
V
CE
CE
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/288M
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
165-Ball FBGA Pinout (3 Chip Enable)
CY7C1361C (256K x 36)
BW
1
BW
2
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
A
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
A0
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
CY7C1361C
CY7C1363C
891011
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC/576M
NC/1G DQP
DQ
DQ
DQ
DQ
NC
DQ
DQ
DQ
DQ
NC
A
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
AA
B
B
B
B
B
A
A
A
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1363C (512K x 18)
2345671
NC/288M
NC/144M
NC
NC
NC V
NC
NC
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
ACE
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
BW
1
2
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
3
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
891011
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
A
NC/576M
NC/1G DQP
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
DQ
DQ
DQ
DQ
ZZ
A
A
A
A
NCV
NC
NC
NC
NC
A
AA
A
A
A
A
A
Document #: 38-05541 Rev. *F Page 6 of 31
[+] Feedback
Pin Definitions
Name I/O Description
, A1, A Input-
A
0
,BW
BW
A
BWC,BW
B
D
Synchronous
Input-
Synchronous
GW Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
1
2
[2]
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
OE Input-
Asynchronous
ADV Input-
Synchronous
ADSP Input-
Synchronous
ADSC
Input-
Synchronous
BWE
Input-
Synchronous
ZZ Input-
Asynchronous
DQ
DQP
s
X
I/O-
Synchronous
I/O-
Synchronous
MODE Input-
Static
V
V
DD
DDQ
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Address Inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP
active. A
feed the 2-bit counter.
[1:0]
or ADSC is active LOW, and CE1, CE2, and CE
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BW
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment
the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
HIGH. CE
is sampled only when a new external address is loaded.
1
and CE
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
a new external address is loaded.
and CE
1
[2]
to select/deselect the device. ADSP is ignored if CE1 is
3
[2]
to select/deselect the device. CE2 is sampled only when
3
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
new external address is loaded.
and CE2 to select/deselect the device.CE3 is sampled only when a
1
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
is recognized. ASDP is ignored when
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A
asserted, only ADSP
are also loaded into the burst counter. When ADSP and ADSC are both
[1:0]
is recognized.
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines . As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE
the pins behave as outputs. When HIGH, DQ
condition.The outputs ar e au to matically tri-stated during the data portion of a write
sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE
Bidirectional Data Parity I/O Lines . Functionally, these signals are identical to DQs.
During write sequences, DQPX is controlled by BWX correspondingly.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
CY7C1361C
CY7C1363C
[2]
are sampled
3
and BWE).
X
is deasserted HIGH.
CE
1
and DQPX are placed in a tri-state
s
.
. When OE is asserted LOW,
DD
Document #: 38-05541 Rev. *F Page 7 of 31
[+] Feedback
CY7C1361C
CY7C1363C
Pin Definitions (continued)
Name I/O Description
V
SS
V
SSQ
TDO JTA G serial output
TDI JTAG serial input
TMS JTAG serial input
TCK JTAG-
NC – No Connects. Not internally connected to the die. 18M, 36M, 72M, 144M, 288M, 576M
/DNU Ground/DNU This pin can be connected to Ground or should be left floating.
V
SS
Ground Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
Synchronous
Synchronous
Synchronous
Clock
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to V
up resistor. This pin is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to V
is not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
and 1G are address expansion pins and are not internally connected to the die.
. This pin is not available on TQFP packages.
SS
through a pull
DD
. This pin
DD
Document #: 38-05541 Rev. *F Page 8 of 31
[+] Feedback
CY7C1361C
CY7C1363C
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access d elay from
the clock rise (t
The CY7C1361C/CY7C1363C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is
user-selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP
). Address advancement through the burst sequence is
(ADSC
controlled by the ADV
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
selection and output tri-state control. ADSP
is HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
asserted active, and (2) ADSP
the access is initiated by ADSC
deasserted during this first cycle). The address presented to
the address inputs is latched into the address register and the
burst counter/control logic and presented to the memory core.
If the OE input is asserted LOW, the requested data will be
available at the data outputs a maximum to t
rise. ADSP
is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
active, and (2) ADSP
presented are loaded into the address register and the burst
inputs (GW
, BWE, and BWX)are ignored during this first clock
cycle. If the write inputs are asserted active (see Write Cycle
Descriptions table for appropriate states that indicate a write)
on the next clock rise, the appropriate data will be latched and
written into the device.Byte writes are allowed. All I/Os are
tri-stated during a byte write.Since this is a common I/O
device, the asynchronous OE input signal must be deasserted
and the I/Os must be tri-stated prior to the presentation of data
to DQs. As a safety precaution, the data lines are tri -stated
once a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
) is 6.5 ns (133-MHz device).
CDV
) or the Controller Address Strobe
input. A two-bit on-chip wraparound
) overrides all byte write inputs and writes data to
, CE2, CE
1
) provide for easy bank
[2]
) and an
3
is ignored if CE
, CE2, and CE
1
or ADSC is asserted LOW (if
[2]
3
are all
, the write inputs must be
after clock
CDV
, CE2, CE
1
is asserted LOW. The addresses
, CE2, and CE
1
[2]
are all asserted
3
[2]
are all asserted
3
active, (2) ADSC
HIGH, and (4) the write input signals (GW
indicate a write access. ADSC
is asserted LOW, (3) ADSP is deasserted
, BWE, and BWX)
is ignored if ADSP is active
LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the
memory core. The information presented to DQ
written into the specified address location. Byte writes are
allowed. All I/Os are tri-stated when a write is detected, even
a byte write. Since this is a common I/O device, the
asynchronous OE input signal must be deasserted and the
I/Os must be tri-stated prior to the presentation of data to DQ
As a safety precaution, the data lines are tri-stated once a writ e
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1361C/CY7C1363C provides an on-chip two-bit
wraparound burst counter inside the SRAM. The burst counter
is fed by A
burst order. The burst order is determined by the state of the
, and can follow either a linear or interleaved
[1:0]
MODE input. A LOW on MODE will select a linear burst
sequence. A HIGH on MODE will select an interleaved burst
order. Leaving MODE unconnected will cause the device to
default to a interleaved burst sequence.
Interleaved Burst Address Table
1
(MODE = Floating or V
First
Address
A1: A0
Second
Address
A1: A0
DD
)
Third
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
Second
Address
A1: A0
, CE2, CE
1
Third
Address
A1: A0
[2]
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
will be
[A:D]
Fourth
Address
A1: A0
Fourth
Address
A1: A0
.
s
Document #: 38-05541 Rev. *F Page 9 of 31
[+] Feedback
CY7C1361C
CY7C1363C
ZZ Mode Electrical Characteristics
Parameter De scription Test Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Sleep mode standby current ZZ > VDD – 0.2V Comm/ind’l 50 mA
Automotive 60 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[3, 4, 5, 6, 7]
ns
ns
ns
Cycle Description
Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power-down None H X X L X L X X X L-H Tri-state
Deselected Cycle, Power-down None L L X L L X X X X L-H Tri-state
Deselected Cycle, Power-down None L X H L L X X X X L-H Tri-state
Deselected Cycle, Power-down None L L X L H L X X X L-H Tri-state
Deselected Cycle, Power-down None X X X L H L X X X L-H Tri-state
Sleep Mode, Power-down None X X X H X X X X X X Tri-state
Read Cycle, Begin Burst External L H L L L X X X L L-H Q
Address
Read Cycle, Begin Burst External L H L L L X X X H L-H
Write Cycle, Begin Burst External L H L L H L X L X L-H
Read Cycle, Begin Burst External L H L L H L X H L L-H
Read Cycle, Begin Burst External L H L L H L X H H L-H
Read Cycle, Continue Burst Next X X X L H H L H L L-H
Read Cycle, Continue Burst Next X X X L H H L H H L-H
Tri-state
D
Q
Tri-state
Q
Tri-state
Read Cycle, Continue Burst Next H X X L X H L H L L-H Q
Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-state
Write Cycle, Continue Burst Next X X X L H H L L X L-H D
Write Cycle, Continue Burst Next H X X L X H L L X L-H D
Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q
Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-state
Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q
Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-state
Write Cycle, Suspend Burst Current X X X L H H H L X L-H D
Write Cycle, Suspend Burst Current H X X L X H H L X L-H D
Notes:
3. X=”Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
5. The DQ pins are controlled by the current cycle and the OE
6. The SRAM always initiates a read cycle when ADSP
7. OE
= L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
the ADSP
care for the remainder of the write cycle.
inactive or when the device is deselected, and all data bits behave as output when OE
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
signal. OE is asynchronous and is not sampled with the clock.
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
is active (LOW).
Document #: 38-05541 Rev. *F Page 10 of 31
[+] Feedback
Loading...