Cypress CY7C1362C, CY7C1360C User Manual
A
A
B
CY7C1360C
CY7C1362C
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
Features
• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply (VDD)
• 2.5V/3.3V I/O operation (V
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium
®
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Single Cycle Chip Deselect
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• TQFP Available with 3-Chip Enable and 2-Chip Enable
• IEEE 1149.1 JTAG-Compatible Boundary Scan
DDQ
)
®
Functional Description
The CY7C1360C/CY7C1362C SRAM integrates 256K x 36
and 512K x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
address-pipelining Chip Enable (CE
Enables (CE
ADV
and
(GW
). Asynchronous inputs include the Output Enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
Address Strobe Controller (ADSC
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW cause
The CY7C1360C/CY7C1362C operates from a +3.3V core
and CE
2
), Write Enables (BWX, and BWE), and Global Write
3
s all bytes to be written.
[1]
), depth-expansion Chip
[2]
), Burst Control inputs (ADSC, ADSP,
1
) are active. Subsequent
) or
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Logic Block Diagram – CY7C1362C (512K x 18)
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BWE
GW
CE
CE2
CE3
OE
B
A
1
ADDRESS
REGISTER
DQB,DQP
B
WRITE REGISTER
DQA,DQP
A
WRITE REGISTER
ENABLE
REGISTER
A[1:0]
2
Q1
BURST
COUNTER AND
LOGIC
CLR
Q0
PIPELINED
ENABLE
DQB,DQP
B
WRITE DRIVER
DQA,DQP
A
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP
DQP
INPUT
REGISTERS
ZZ
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
is for A version of TQFP (3 Chip Enable option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
2. CE
3
SLEEP
CONTROL
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05540 Rev . *H Revised September 14, 2006
[+] Feedback
.
A
Logic Block Diagram – CY7C1360C (256K x 36)
0, A1, A
MODE
ADV
CLK
ADSC
ADSP
BW
BW
BW
BW
BWE
GW
CE
CE
CE
OE
D
C
B
A
1
2
3
ADDRESS
REGISTER
D ,
DQPD
DQ
BYTE
WRITE REGISTER
C ,
DQPC
DQ
BYTE
WRITE REGISTER
B ,
DQPB
DQ
BYTE
WRITE REGISTER
DQ
A ,
DQPA
BYTE
WRITE REGISTER
ENABLE
REGISTER
2
BURST
COUNTER
AND
CLR
LOGIC
PIPELINED
ENABLE
A
[1:0]
Q1
Q0
D
,DQP
D
DQ
BYTE
WRITE DRIVER
C ,
DQPC
DQ
BYTE
WRITE DRIVER
B ,
DQPB
DQ
BYTE
WRITE DRIVER
DQ
A ,
DQPA
BYTE
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
CY7C1360C
CY7C1362C
OUTPUT
BUFFERS
E
INPUT
REGISTERS
DQs
DQP
DQP
DQP
DQP
A
B
C
D
ZZ
SLEEP
CONTROL
Selection Guide
250 MHz 200 MHz 166 MHz Unit
Maximum Access Time 2.8 3.0 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current 40 40 40 mA
Document #: 38-05540 Rev. *H Page 2 of 31
[+] Feedback
Pin Configurations
100-Pin TQFP Pinout (3 Chip Enables) (A Version)
CY7C1360C
CY7C1362C
DQP
DQC
DQc
V
DDQ
V
SSQ
DQC
DQC
DQC
DQC
V
SSQ
V
DDQ
DQC
DQC
NC
V
NC
V
DQD
DQD
V
DDQ
V
SSQ
DQD
DQD
DQD
DQD
V
SSQ
V
DDQ
DQD
DQD
DQPD
1CE2
A
A
BWD
BWC
CE
100999897969594939291908988878685848382
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DD
15
16
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
BWB
CY7C1360C
(256K X 36)
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
BWA
NC/72M
CE3VDDV
SS
V
NC/36M
SS
CLKGWBWEOEADSC
A
DD
V
NC/18M
ADSP
AAAAA
A
A
ADV
81
DQPB
80
DQB
79
DQB
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
DQB
DQB
DQB
DQB
V
SSQ
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
DQPA
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQB
V
SSQ
V
DDQ
DQB
DQB
NC
V
NC
V
DQB
DQB
V
DDQ
V
SSQ
DQB
DQB
DQPB
NC
V
SSQ
V
DDQ
NC
NC
NC
B
DD
SS
50
A
A
1CE2
A
A
NCNCBWBBWA
CE
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1362C
(512K x 18)
CE3VDDV
SS
CLKGWBWEOEADSC
ADSP
31323334353637383940414243444546474849
AAA
MODE
1A0
A
A
NC/72M
NC/36M
A
DD
V
AAAAA
SS
V
NC/18M
ADV
A
A
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
50
A
A
Document #: 38-05540 Rev. *H Page 3 of 31
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Pin Configurations (continued)
100-Pin TQFP Pinout (2 Chip Enables) (AJ Version)
CY7C1360C
CY7C1362C
DQPC
DQC
DQC
V
DDQ
V
SSQ
DQC
DQC
DQC
DQC
V
SSQ
V
DDQ
DQC
DQC
NC
V
NC
V
DQD
DQD
V
DDQ
V
SSQ
DQD
DQD
DQD
DQD
V
SSQ
V
DDQ
DQD
DQD
DQPD
1CE2
A
A
BWD
BWC
CE
BWB
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DD
15
16
SS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1360C
(256K X 36)
31323334353637383940414243444546474849
AAA
1A0
A
A
MODE
SS
BWA
A
VDDV
CLKGWBWEOEADSC
ADSP
ADV
A
A
81
DQPB
80
DQB
79
DQB
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
DQB
DQB
DQB
DQB
V
SSQ
V
DDQ
DQB
DQB
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
DQPA
A
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ
DQB
V
SSQ
V
DDQ
DQB
DQB
NC
V
NC
V
DQB
DQB
V
DDQ
V
SSQ
DQB
DQB
DQPB
NC
V
SSQ
V
DDQ
NC
NC
NC
B
DD
SS
50
A
DD
V
NC
NC/18M
AAAAA
SS
V
NC/36M
NC/72M
A
1CE2
A
A
NCNCBWBBWA
CE
A
VDDV
SS
CLKGWBWEOEADSC
ADSP
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1362C
(512K x 18)
31323334353637383940414243444546474849
AAA
MODE
1A0
A
A
SS
V
NC/72M
NC/36M
DD
V
NC
NC/18M
AAAAA
A
A
ADV
81
A
80
NC
79
NC
78
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
V
SSQ
NC
DQP
DQA
DQA
V
SSQ
V
DDQ
DQA
DQA
V
SS
NC
V
DD
ZZ
DQ
DQA
V
DDQ
V
SSQ
DQA
DQA
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
A
A
50
A
A
Document #: 38-05540 Rev. *H Page 4 of 31
[+] Feedback
Pin Configurations (continued)
119-Ball BGA Pinout (2 Chip Enables with JTAG)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC/288M
NC/144M
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
NC
NC
V
DDQ
CY7C1360C
CY7C1362C
CY7C1360C (256K x 36)
2345671
AA AA
CE
2
A
AA
C
D
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
BW
V
SS
V
SS
V
SS
MODE
DQP
C
DQ
C
C
C
D
D
D
D
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
C
C
C
C
D
D
D
D
A
AAA
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
C
GW
DD
CLK
D
NC
BWE
A1
A0
V
DD
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
SS
SS
SS
B
SS
SS
A
SS
SS
SS
A
AA
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
A
NC/36MNC/72M
TDOTCKTDITMS
NC
B
B
B
B
B
A
A
A
A
A
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC
NC/72M
V
DDQ
CY7C1362C (512K x 18)
2
AA AA
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
ADSP
A
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
ADSC
V
DD
NC
CE
1
OE
ADV
B
GW
DD
CLK
NC
BWE
A1
A0
V
DD
A NC/36M A
V
V
V
V
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
V
DDQ
NC/576M
NC/1G
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC
ZZ
V
DDQ
Document #: 38-05540 Rev. *H Page 5 of 31
[+] Feedback
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip Enable with JTAG)
2345671
NC/288M
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
A
A
NC
DQ
DQ
DQ
DQ
V
SS
DQ
DQ
DQ
DQ
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
C
C
C
C
V
V
V
DDQ
DDQ
DDQ
DDQ
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
D
D
D
D
A
A
CY7C1360C
CY7C1362C
CY7C1360C (256K x 36)
891011
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
C
BW
D
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
B
A
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
A0
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCK
ADSC
ADV
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC/1G DQP
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
NC
NC/576M
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1362C (512K x 18)
2345671
NC/288M
NC/144M
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
3
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
891011
ADSC
ADV
OE ADSP
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
V
V
V
V
V
V
V
V
V
V
A
A
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
A
NC/1G DQP
NC
NC
NC
NC
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
NC/576M
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
A
AA
A
A
A
A
A
Document #: 38-05540 Rev. *H Page 6 of 31
[+] Feedback
Pin Definitions
Name I/O Description
A0, A1, A Input-
Synchronous
BW
, BW
A
BWC, BW
B
D
Input-
Synchronous
GW Input-
Synchronous
BWE
Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
[2]
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
ADV
Input-
Synchronous
ADSP Input-
Synchronous
ADSC
Input-
Synchronous
ZZ Input-
Asynchronous
DQs, DQP
V
DD
V
SS
V
SSQ
V
DDQ
X
I/O-
Synchronous
Power Supply Power supply inputs to the core of the device.
Ground Ground for the core of the device.
I/O Ground Ground for the I/O circuitry.
I/O Power Supply Power supply for the I/O circuitry.
MODE Input-
Static
TDO JTAG serial
output
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP
are fed to the two-bit counter.
or ADSC is active LOW, and CE1, CE2, and CE
.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the
SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global Write is conducted (ALL bytes are written, regardless of the values on BW
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a Byte Write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.
and CE
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
and CE
1
is asserted LOW, during a burst operation.
[2]
to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is
3
[2]
to select/deselect the device. CE2 is sampled only when a new external
3
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
connected for BGA. Where referenced, CE
BGA. CE
and CE2 to select/deselect the device. Not available for AJ package version. Not
1
is sampled only when a new external address is loaded.
3
3
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW . When
asserted LOW, addresses presented to the device are captured in the address registers. A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
A
0
is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
A
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
0
is recognized.
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE
When HIGH, DQs and DQP
are placed in a tri-state condition.
X
. When OE is asserted LOW, the pins behave as outputs.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
left floating selects interleaved burst sequence. This is a strap pin and should remain static
during device operation. Mode pin has an internal pull-up.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP
packages.
CY7C1360C
CY7C1362C
[2]
are sampled active. A1, A0
3
and BWE).
X
[2]
is assumed active throughout this document for
DD
1
1
or
,
,
Document #: 38-05540 Rev. *H Page 7 of 31
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Pin Definitions (continued)
Name I/O Description
TDI JT AG serial input
Synchronous
TMS JT AG serial input
Synchronous
TCK JTAG-
Clock
NC – No Connects. Not internally connected to the die
NC (18,36,
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
72, 144, 288,
576, 1G)
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature is
not being utilized, this pin can be disconnected or connected to VDD. This pin is not available
on TQFP packages.
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature is
not being utilized, this pin can be disconnected or connected to V
on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be
connected to V
. This pin is not available on TQFP packages.
SS
288M, 576M, and 1G densities.
CY7C1360C
CY7C1362C
. This pin is not available
DD
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).
The CY7C1360C/CY7C1362C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486™
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP
) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE
) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW
) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE
, CE2, CE
1
) provide for easy bank
selection and output tri-state control. ADSP
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP
CE
, CE2, CE
1
signals (GW
is HIGH. The address presented to the address inputs
if CE
1
(A) is stored into the address advancement logic and the
[2]
are all asserted active, and (3) the Write
3
, BWE) are all deasserted HIGH. ADSP is ignored
or ADSC is asserted LOW, (2)
address register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the outp ut register and
onto the data bus within 2.8 ns (250-MHz device) if OE
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always tri-stated during the first cycle of the
) is 2.8 ns
CO
[2]
) and an
3
is ignored if CE
is
access. After the first cycle of the access, the outputs are
controlled by the OE
signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP
or ADSC signals, its output
will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP
(2) CE
, CE2, CE
1
presented to A is loaded into the address register and the
[2]
are all asserted active. The address
3
is asserted LOW, and
address advancement logic while being delivered to the
memory array. The Write signals (GW
ADV
inputs are ignored during this first cycle.
ADSP
-triggered Write accesses require two clock cycles to
complete. If GW
is asserted LOW on the second clock rise, the
, BWE, and BWX) and
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HI GH,
then the Write operation is controlled by BWE
signals. The CY7C1360C/CY7C1362C provides Byte Write
capability that is described in the Write Cycle Descriptions
table. Asserting the Byte Write Enable input (BWE
selected Byte Write (BW
the desired bytes. Bytes not selected during a Byte Write
) input, will selectively write to only
X
operation will remain unaltered. A synchronous self-timed
Write mechanism has been provided to simplify the Write
operations.
Because the CY7C1360C/CY7C1362C is a common I/O
1
device, the Output Enable (OE
) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless
of the state of OE
.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW
BWE
, and BWX) are asserted active to conduct a Write to the
desired byte(s). ADSC
is asserted LOW, (2) ADSP is
, CE2, CE
1
[2]
are all asserted active,
3
-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded into the address register and the address
advancement logic while being delivered to the m emory array .
The ADV
input is ignored during this cycle. If a global Write is
and BW
) with the
X
,
Document #: 38-05540 Rev. *H Page 8 of 31
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CY7C1360C
CY7C1362C
conducted, the data presented to the DQs is written into the
corresponding address location in the memory core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1360C/CY7C1362C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQs inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless
of the state of OE
.
Burst Sequences
The CY7C1360C/CY7C1362C provides a two-bit wraparound
counter, fed by A
or linear burst sequence. The interleaved burst sequence is
, A0, that implements either an interleaved
1
designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input.
Asserting ADV
LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
, CE2, CE
1
returns LOW.
[2]
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
First
Address
A1, A
0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
A1, A
)
DD
Third
Address
0
A1, A
0
Fourth
Address
A1, A
0
Linear Burst Address Table (MODE = GND)
First
Address
A1, A
0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1, A
0
Third
Address
A1, A
0
Fourth
Address
A1, A
0
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Operation
Deselect Cycle, Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle, Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle, Power Down None L X H L H L X X X L-H Tri-State
Sleep Mode, Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE
5. The DQ pins are controlled by the current cycle and the OE
6. CE
7. The SRAM always initiates a read cycle when ADSP
8. OE
= L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.
, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2.
1
after the ADSP
don't care for the remainder of the Write cycle.
is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE
Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ Active to sleep current This parameter is sampled 2t
CYC
CYC
ns
ns
ns
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[3, 4, 5, 6, 7, 8]
Address
Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
signal. OE is asynchronous and is not sampled with the clock.
or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a
is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks
is active (LOW).
Document #: 38-05540 Rev. *H Page 9 of 31
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CY7C1360C
CY7C1362C
Truth Table
[3, 4, 5, 6, 7, 8]
(continued)
Address
Operation
Used CE
CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ
1
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State
WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D
WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D
Partial Truth Table for Read/Write
Function (CY7C1360C) GW BWE BW
[5, 9]
D
BW
C
BW
B
BW
A
Read HHXXXX
Read HLHHHH
Write Byte A – (DQ
Write Byte B – (DQ
and DQPA) HLHHHL
A
and DQPB)HLHHLH
B
Write Bytes B, A H L H H L L
Write Byte C – (DQ
and DQPC) HLHLHH
C
Write Bytes C, A H L H L H L
Write Bytes C, B H L H L L H
Write Bytes C, B, A H L H L L L
Write Byte D – (DQ
and DQPD) HLLHHH
D
Write Bytes D, A H L L H H L
Write Bytes D, B H L L H L H
Write Bytes D, B, A H L L H L L
Write Bytes D, C H L L L H H
Write Bytes D, C, A H L L L H L
Write Bytes D, C, B HLLLLH
Write All Bytes HLLLLL
Write All Bytes LXXXXX
Note:
9. Table only lists a partial listing of the byte write combinations. A ny combination of BW
is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05540 Rev. *H Page 10 of 31
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