Cypress CY7C1355C, CY7C1357C User Manual
CY7C1355C
CY7C1357C
9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with ze ro
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply (V
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard and lead-free 100-Pin
TQFP, lead-free and non lead-free 119-Ball BGA
package and 165-Ball FBGA package
• Three chip enables for simple depth expansion.
• Automatic Power-down feature avail able using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby powe r
) pin to enable clock and suspend
DDQ
)
Functional Description
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The
CY7C1355C/CY7C1357C is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified b y
the Clock Enable (CEN
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
[1]
) signal, which when deasserted
, CE2, CE3) and an
1
) provide for easy bank
Selection Guide
133 MHz 100 MHz Unit
Maximum Access Time 6.5 7.5 ns
Maximum Operating Current 250 180 mA
Maximum CMOS Standby Cur rent 40 40 mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05539 Rev . *E Revised September 14, 2006
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1
A
B
C
D
C
C
A
B
C
C
Logic Block Diagram – CY7C1355C (256K x 36)
A0, A1, A
MODE
LK
EN
2
C
ADV/LD
BW
BW
BW
BW
WE
CE1
CE2
CE3
ZZ
A
B
C
D
OE
CE
ADDRESS
REGISTER
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
D1
D0
Logic Block Diagram – CY7C1357C (512K x 18)
BURST
LOGIC
CY7C1355C
CY7C1357C
A1'
Q1
A0'
Q0
O
U
T
P
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
G
E
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
MEMORY
ARRAY
REGISTER
INPUT
S
E
N
S
E
A
M
P
S
E
ADDRESS
REGISTER
ADV/LD
C
A1
A0
D1
D0
BURST
LOGIC
Q1
Q0
A1'
A0'
LK
EN
A0, A1, A
MODE
C
CE
WRITE ADDRESS
REGISTER
O
U
T
P
ADV/LD
BW
A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
D
U
A
T
T
A
B
U
S
F
T
F
E
E
E
R
R
S
I
N
E
DQs
DQP
DQP
G
CE1
CE2
CE3
ZZ
OE
READ LOGIC
SLEEP
CONTROL
INPUT
REGISTER
E
Document #: 38-05539 Rev. *E Page 2 of 28
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Pin Configurations
100-Pin TQFP Pinout
CY7C1355C
CY7C1357C
BYTE C
BYTE D
DQP
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
Vss/DNU
V
NC
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQ
DQ
V
V
DDQ
DQ
DQ
DQP
SS
SS
DD
SS
SS
SS
1CE2
A
CE
A
1009998979695949392919089888786
1
C
2
C
3
C
4
5
6
C
7
C
8
C
9
C
10
11
12
C
13
C
14
15
16
17
18
D
19
D
20
21
22
D
23
D
24
D
25
D
26
27
28
D
29
D
30
D
C
BWDBW
BWBBWACE3VDDV
CY7C1355C
SS
CLKWECEN
OE
ADV/LD
NC/18M
85
A
A
848382
A
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
DQ
DQ
V
SS
V
DDQ
DQ
DQ
DQP
B
B
B
B
BYTE B
B
B
B
B
B
A
A
A
A
BYTE A
A
A
A
A
A
31323334353637
A
A
A
A
MODE
383940414243444546
A1
A0
NC/288M
SS
V
NC/144M
DD
V
NC/72M
A
NC/36M
474849
A
A
A
50
A
A
A
Document #: 38-05539 Rev. *E Page 3 of 28
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Pin Configurations (continued)
100-Pin TQFP Pinout
CY7C1355C
CY7C1357C
BYTE B
NC
NC
NC
V
DDQ
V
NC
NC
DQ
DQ
V
V
DDQ
DQ
DQ
Vss/DNU
V
NC
V
DQ
DQ
V
DDQ
V
DQ
DQ
DQP
NC
V
V
DDQ
NC
NC
NC
SS
SS
DD
SS
SS
SS
1CE2
A
A
100
99989796959493929190898887868584838281
CE
NC
1
2
3
4
5
6
7
8
B
9
B
10
11
12
B
13
B
14
15
16
17
18
B
19
B
20
21
22
B
23
B
24
B
25
26
27
28
29
30
NC
BBWA
BW
CE3VDDV
CY7C1357C
SS
CLKWECEN
OE
ADV/LD
A
NC/18M
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DQP
DQ
DQ
V
SS
V
DDQ
DQ
DQ
V
SS
NC
V
DD
ZZ
DQ
DQ
V
DDQ
V
SS
DQ
DQ
NC
NC
V
SS
V
DDQ
NC
NC
NC
A
A
A
A
A
BYTE A
A
A
A
A
31323334353637383940414243
A
A
A
A
A1
A0
MODE
NC/288M
NC/144M
SS
DD
V
V
44454647484950
A
A
A
NC/72M
NC/36M
A
A
A
A
Document #: 38-05539 Rev. *E Page 4 of 28
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Pin Configurations (continued)
119-Ball BGA Pinout (3 Chip Enables with JTAG)
V
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
DDQ
NC/576M
NC/1G
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
V
DDQ
DQ
DQ
NC/144M
NC
V
DDQ
CY7C1355C
CY7C1357C
CY7C1355C (256K x 36)
2345671
AA AANC/18M V
CE
2
DQP
DQ
DQ
DQ
DQ
V
DD
DQ
DQ
DQ
DQ
DQP
C
C
C
C
C
D
D
D
D
D
C
C
C
C
D
D
D
D
A
A
AA
V
SS
V
SS
V
SS
BW
C
V
SS
NC V
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
ADV/LD
V
DD
NC
CE
1
OE
A
WE
DD
CLK
NC
CEN
A1
A0
V
DD
AAA
A
V
V
V
BW
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
CE
3
AA
DQP
DQ
B
DQ
B
DQ
DQ
V
DQ
DQ
DQ
DQ
B
B
DD
A
A
A
A
B
A
DQP
A
NC/36MNC/72M
NC
B
A
DDQ
NC
NC
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC/288M
ZZ
V
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
B
NC
V
DDQ
NC
DQ
B
V
DDQ
NC
DQ
B
V
DDQ
DQ
B
NC
NC/144M
NC/72M
V
DDQ
CY7C1357C (512K x 18)
2
AA AANC/18M V
CE
2
NCDQ
DQ
B
NC
DQ
B
NC
V
DD
DQ
B
NC
DQ
B
NC
DQP
B
A
345671
A
ADV/LD
AA
V
SS
V
SS
V
SS
BW
V
SS
NC V
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
V
DD
NC
CE
1
OE
B
A
WE
DD
CLK
NC
CEN
A1
A0
V
DD
A NC/36M A
A
V
V
V
V
V
NC
V
BW
V
V
V
NC
TDOTCKTDITMS
SS
SS
SS
SS
SS
SS
SS
SS
SS
CE
3
AA
DQP
A
NC
DQ
A
NC
DQ
A
V
DD
NC
DQ
A
A
NC
DQ
A
NC
A
AA
NC
DDQ
NC
NC
NC
DQ
A
V
DDQ
DQ
A
NC
V
DDQ
DQ
A
NC
V
DDQ
NC
DQ
A
NC/288M
ZZ
V
DDQ
Document #: 38-05539 Rev. *E Page 5 of 28
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Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip enable with JTAG)
2345671
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/576M
NC/1G
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC/144M
MODE
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
CY7C1355C
CY7C1357C
CY7C1355C (256K x 36)
891011
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
B
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
C
D
NC
TDI
TMS
CE
CLK
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
NC/18M
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC
NC
NC DQP
DQ
DQ
DQ
DQ
DQ
B
DQ
B
DQ
B
DQ
B
NC
A
A
A
A
DQ
DQ
DQ
DQ
DQP
NC/288M
DQ
DQ
DQ
DQ
NC
A
B
B
B
B
B
ZZ
A
A
A
A
A
AA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CY7C1357C (512K x 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
B
DQ
B
DQ
B
DQ
B
DQP
B
NC/144M
MODE
A
A
NC
DQ
B
DQ
B
DQ
B
DQ
B
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
B
NC BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
A
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
891011
A
A
NC
NC DQP
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
A
A
A
A
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
NC/288M
A
A
A
A
A
A
AA
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCK
A
NC/18M
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
Document #: 38-05539 Rev. *E Page 6 of 28
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CY7C1355C
CY7C1357C
Pin Definitions
Name I/O Description
, A1, A Input-
A
0
, BW
BW
A
BWC, BW
WE
B
D
Synchronous
Input-
Synchronous
Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
OE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN Input-
Synchronous
ZZ Input-
Asynchronous
DQ
DQP
s
X
I/O-
Synchronous
I/O-
Synchronous
MODE Input Strap Pin Mode Input. Selects th e burst order of t he device. When tied to Gnd selects linear burst
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
Ground Ground for the device.
TDO JTAG serial output
Synchronous
TDI JT AG serial input
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled
on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW .
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
. CLK is only recognized if CEN is active LOW.
CEN
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
, and CE3 to select/deselect the device.
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE2 to select/deselect the device.
1
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE
is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by
the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, CEN
can be used to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integri ty preserved. For norm al operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
Read cycle. The direction of the pins is controlled by OE
pins behave as outputs. When HIGH, DQ
outputs are automatically tri-stated during the data portion of a Write sequence, during the
and DQPX are placed in a tri-state condition.The
s
. When OE is asserted LOW, the
clock rise of the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE
.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During
Write sequences, DQP
sequence. When tied to V
is controlled by BWX correspondingly.
X
or left floating selects interleaved burst sequence.
DD
Power supply for the I/O circuitry.
Serial data-out to the JT AG circuit. Delivers data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be left unconnected. This pin is not available on
TQFP packages.
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature
is not being utilized, this pin can be left floating or connected to V
This pin is not available on TQFP packages.
through a pull up resistor.
DD
Document #: 38-05539 Rev. *E Page 7 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Pin Definitions (continued)
Name I/O Description
TMS JT AG serial input
Synchronous
TCK JTAG
Clock
NC – No Connects. Not internally connected to the die. 18 Mbit, 36 Mbit, 72 Mbit, 144 Mbit, 288
/DNU Ground/DNU This pin can be connected to Ground or should be left floating.
V
SS
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN
nized and all internal states are maintained. All synchronous
operations are qualified with CEN
from the clock rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
1
Enable (CEN
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
writes are simplified with on-chip synchronous self-timed Writ e
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory arra y
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 7.5
ns (133-MHz device) provided OE
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
). If CEN is HIGH, the clock signal is not recog-
) is 6.5 ns (133-MHz device).
CDV
, CE2, CE3) active at the rising edge of the clock. If Clock
) is active LOW and ADV/LD is asserted LOW,
should be driven LOW once the device has been
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and 4) ADV/LD is asserted
Serial data-In to the JT AG circuit. Sampled on the rising edge of TCK. If the JT AG feature
is not being utilized, this pin can be disconnected or connected to V
available on TQFP packages.
. This pin is not
DD
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
. This pin is not available on TQFP packages.
SS
Mbit, 576 Mbit and 1G are address expansion pins and are not internally connected to the
die.
Burst Read Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD
must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter i s
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
. Maximum access delay
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
). BWX can be used to
). All
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to the address bus
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
is loaded into the address register. The write signals are
latched into the Control Logic block. The data lines are
) simplify depth expansion.
automatically tri-stated regardless of the state of the OE
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQP
(or a subset for byte write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
is asserted LOW, (2) CE1, CE2,
The data written during the Write operation is controlled by
BW
signals. The CY7C1355C/CY7C1357C provides byte
X
write capability that is described in the Truth Table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
is active LOW. After the first
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1355C/CY7C1357C is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE
) can be deasserted
HIGH before presenting data to the DQs and DQP
Doing so will tri-state the output drivers. As a safety
input
inputs.
X
X
Document #: 38-05539 Rev. *E Page 8 of 28
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CY7C1355C
CY7C1357C
precaution, DQs and DQ PX are automatically tri-stat ed during
the data portion of a write cycle, regardless of the state of OE
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE
inputs are ignored and the burst counter is incremented.
WE
The correct BW
burst write, in order to write the correct bytes of data.
inputs must be driven in each cycle of the
X
, CE2, and CE3) and
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
Interleaved Burst Address Table
.
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
A1: A0
Third
Address
A1: A0
guaranteed. The device must be deselected prior to e ntering
the “sleep” mode. CE
for the duration of t
.
.
, CE2, and CE3, must remain inactive
1
after the ZZ input returns LOW.
ZZREC
ZZ Mode Electrical Characteristics
Parameter Description T est Conditions Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Sleep mode standby current ZZ > VDD – 0.2V 50 mA
Device operation to ZZ ZZ > VDD – 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This parameter is sampled 2t
CYC
CYC
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[2, 3, 4, 5, 6, 7, 8]
Fourth
Address
A1: A0
Fourth
Address
A1: A0
ns
ns
ns
Operation
Used CE1CE2CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H Tri-State
Deselect Cycle None X X H L L X X X L L->H Tri-State
Deselect Cycle None X L X L L X X X L L->H Tri-State
Continue Deselect Cycle None X X X L H X X X L L->H Tri-State
READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Tri-State
DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Tri-State
WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
Address
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BW
Selects are asserted, see Truth Table for details.
3. Write is defined by BW
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQP
6. CEN
= H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
8. OE
is asynchronous and is not sampled with the clock rise. It is masked internally during W rite cycles. During a Read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
, and WE. See Truth Table for Read/Write.
X
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
X
x = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
.
= data when OE is active.
X
Document #: 38-05539 Rev. *E Page 9 of 28
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