Cypress CY7C1356CV25, CY7C1354CV25 User Manual
p
CY7C1354CV25
a
b
c
d
C
CY7C1356CV25
9-Mbit (256K x 36/512K x 18)
elined SRAM with NoBL™ Architecture
Pi
Features
• Pin-compatible with and functionally equivalent to
ZBT™
• Supports 250-MHz bus operations with zero wait states
• Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply (V
• Fast clock-to-output times
— 2.8 ns (for 250-MHz device)
• Clock Enable (CEN
) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
DD
)
Functional Description
[1]
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354CV25 and
CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354CV25
and CY7C1356CV25 are pin-compatible with and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN
) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
–BWd for CY7C1354CV25 and BWa–BWb for
a
CY7C1356CV25) and a Write Enable (WE
) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE
, CE2, CE3) and an
1
) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Logic Block Diagram–CY7C1354CV25 (256K x 36)
A0, A1, A
MODE
C
CLK
EN
ADV/LD
BW
a
BW
b
BW
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
c
BW
d
WE
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05537 Rev . *H Revised September 14, 2006
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
ADV/LD
REGISTER 2
C
A1
D1D0Q1
A0
BURST
LOGIC
A1'
A0'
Q0
WRITE
DRIVERS
MEMORY
ARRAY
INPUT
REGISTER 1
O
S
U
T
E
P
N
U
T
S
E
R
E
G
A
I
M
S
T
P
E
S
R
S
E
E
REGISTER 0
INPUT
O
D
U
T
A
P
T
U
A
T
B
S
T
E
E
R
I
N
G
E
DQs
U
DQP
F
DQP
F
DQP
E
DQP
R
S
E
[+] Feedback
a
b
C
Logic Block Diagram–CY7C1356CV25 (512K x 18)
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
A0
ADV/LD
C
WRITE ADDRESS
REGISTER 2
D1D0Q1
BURST
LOGIC
A1'
A0'
Q0
CLK
A0, A1, A
MODE
C
EN
CY7C1354CV25
CY7C1356CV25
O
U
T
P
S
U
INPUT
E
T
N
S
R
E
E
G
A
I
M
S
P
T
S
E
R
S
E
E
REGISTER 0
ADV/LD
BW
a
BW
b
WE
OE
CE1
CE2
CE3
ZZ
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
WRITE
DRIVERS
MEMORY
ARRAY
REGISTER 1
INPUT
O
U
T
P
D
U
A
T
T
A
B
DQs
U
S
F
T
E
E
R
I
N
G
E
DQP
F
DQP
E
R
S
E
Selection Guide
250 MHz 200 MHz 166 MHz Unit
Maximum Access Time 2.8 3.2 3.5 ns
Maximum Operating Current 250 220 180 mA
Maximum CMOS Standby Current 40 40 40 mA
Document #: 38-05537 Rev. *H Page 2 of 28
[+] Feedback
Pin Configurations
a
CY7C1354CV25
CY7C1356CV25
100-pin TQFP Pinout
DQPc
DQc
DQc
V
DDQ
V
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
V
DDQ
DQd
DQd
DQPd
1CE2
A
A
CE
BWa
BWd
BWc
BWb
SS
CE3VDDV
CLKWECENOENC(18M)
100999897969594939291908988878685848382
1
2
3
4
5
SS
6
7
8
9
10
11
12
13
14
15
16
CY7C1354CV25
(256K × 36)
17
18
19
20
21
22
23
24
25
SS
26
27
28
29
30
31323334353637383940414243444546474849
ADV/LD
A
A
A
81
DDQ
SS
SS
DDQ
SS
DD
DDQ
SS
SS
DDQ
NC
NC
NC
V
DDQ
V
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
DQb
DQb
V
DDQ
V
DQb
DQb
DQPb
NC
V
V
DDQ
NC
NC
NC
SS
SS
SS
SS
DQPb
80
DQb
79
DQb
78
V
77
V
76
DQb
75
DQb
74
DQb
73
DQb
72
V
71
V
70
DQb
69
DQb
68
V
67
NC
66
V
65
ZZ
64
DQa
63
DQa
62
V
61
V
60
DQa
59
DQa
58
DQa
57
DQa
56
V
55
V
54
DQa
53
DQa
52
DQPa
51
50
1CE2
A
A
CE
NC
BWa
BWb
NC
CE3VDDVSSCLKWECENOENC(18M)
ADV/LD
A
100999897969594939291908988878685848382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CY7C1356CV25
(512K × 18)
18
19
20
21
22
23
24
25
26
27
28
29
30
31323334353637383940414243444546474849
A
A
81
A
80
NC
79
NC
78
V
77
DDQ
V
SS
76
NC
75
DQP
74
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
AAA
MODE
0
A
A1A
SS
DD
V
V
NC(144M)
NC(288M)
AAA
A
NC(72M)
NC(36M)
A
A
A
A
AAA
MODE
1A0
A
AAA
A
DD
SS
V
V
NC(144M)
NC(288M)
A
NC(72M)
NC(36M)
A
A
Document #: 38-05537 Rev. *H Page 3 of 28
[+] Feedback
Pin Configurations (continued)
V
A
NC/576M
B
NC/1G
C
D
E
V
F
G
H
V
J
K
L
V
M
N
P
NC/144M
R
T
V
U
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
DDQ
DQ
DQ
NC
DDQ
CY7C1354CV25
CY7C1356CV25
119-Ball BGA Pinout
CY7C1354CV25 (256K × 36)
2345671
AA AANC/18M V
CE
2
A
DQP
c
c
c
c
d
d
DQ
DQ
DQ
DQ
V
DQ
DQ
c
c
c
c
c
DD
d
d
DQd
DQ
d
d
DQP
d
d
A
NC/72M
TMS
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
BW
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC DQP
CE
1
OE
c
A
WE
V
DD
CLK
NC
d
CEN
A1
A0 V
V
DD
A NC/36M
TCK
DDQ
ACE3NC
AANC
V
SS
V
SS
V
SS
BW
b
V
SS
NC V
V
SS
BW
a
V
SS
V
SS
SS
NC
A
DQ
DQ
DQ
DQ
DD
DQ
DQ
DQ
DQ
DQP
A
NCTDI TDO V
b
b
b
b
b
a
a
a
a
a
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC/288M
ZZ
DDQ
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/576M
NC/1G
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC/144M
NC/72M
V
DDQ
CY7C1356CV25 (512K x 18)
2345671
AA AANC/18M V
CE
A
NCDQ
DQ
NC
DQ
NC
V
DD
DQ
NC
DQ
NC
DQP
A
A
TMS
2
b
b
b
b
b
A
A
V
SS
V
SS
V
SS
BW
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
ADV/LD
V
DD
NC NCDQP
CE
1
OE
b
AVSSNC
WE
V
DD
CLK
NC NC
CEN
A1
A0 V
V
DD
NC/36M
A
AANC
V
SS
V
SS
V
SS
V
SS
NC V
SS
BW
a
V
SS
V
SS
SS
NC
A
TCK
CE
3
a
NC
DQ
a
DQ
a
DD
NCV
DQ
a
NC V
DQ
a
NC
A
A
NCTDI TDO V
DDQ
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
DDQ
NC
DQ
a
NC/288M
ZZ
DDQ
Document #: 38-05537 Rev. *H Page 4 of 28
[+] Feedback
Pin Configurations (continued)
CY7C1354CV25
CY7C1356CV25
165-Ball FBGA Pinout
CY7C1354CV25 (256K × 36)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
234 5671
NC/576M
NC/1G
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
NC/144M
MODE
A
A
NC
DQ
c
DQ
c
DQ
c
DQ
c
NC
DQ
d
DQ
d
DQ
d
DQ
d
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
BW
1
BW
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
A
A
BW
BW
V
V
V
V
V
V
V
V
V
V
b
a
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
c
d
NC
TDI
TMS
CY7C1356CV25 (512K × 18)
2345671
NC/576M
NC/1G
NC
NC
NC V
NC
NC
NC
DQ
b
DQ
b
DQ
b
DQ
b
DQP
b
NC/144M
MODE
A
A
NC
DQ
b
DQ
b
DQ
b
DQ
b
NC
NC
NC
NC
NC
NC
NC/72M
NC/36M
CE
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
BW
1
b
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
BW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
a
891011
V
V
V
V
V
V
V
V
V
V
A AADV/LD
DDQ
DDQ
DDQ
DDQ
DDQ
NC
DDQ
DDQ
DDQ
DDQ
DDQ
A
A
A
NC DQP
DQ
b
DQ
b
DQ
b
DQ
b
NC
DQ
a
DQ
a
DQ
a
DQ
a
NC
A
CE
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
CEN
3
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDO
TCKA0
OE NC/18M
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
NC
NC
b
DQ
b
DQ
b
DQ
b
DQ
b
ZZ
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
NC/288M
AA
891011
CE
CLK
V
SS
V
SS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
DD
V
DD
V
DD
V
DD
V
SS
A
A
CEN
3
WE
V
V
V
V
V
V
V
V
V
V
NC
TDO
TCKA0
A A
NC/18M
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
NC
NC DQP
a
a
a
a
DQ
DQ
DQ
DQ
ZZ
NCV
NC
NC
NC
NC
NC/288M
NC
NC
NC
NC
NC
DQ
DQ
DQ
DQ
NC
A
A
a
a
a
a
a
AA
Document #: 38-05537 Rev. *H Page 5 of 28
[+] Feedback
CY7C1354CV25
CY7C1356CV25
Pin Definitions
Pin Name I/O Type Pin Description
A0
A1
Input-
Synchronous
A
BW
a,BWb,
BWc,BW
WE
d,
Input-
Synchronous
Input-
Synchronous
ADV/LD Input-
Synchronous
CLK Input-
Clock
CE
CE
CE
1
2
3
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
OE Input-
Asynchronous
CEN
Input-
Synchronous
DQ
DQP
S
X
I/O-
Synchronous
I/O-
Synchronous
MODE Input Strap Pin Mode Input. Selects the burst order of the device. T ied HIGH selects the interleaved burst order .
TDO JT AG serial output
Synchronous
TDI JT AG serial input
Synchronous
TMS Test Mode Select
Synchronous
TCK JTAG-Clock Clock input to the JTAG circu itry.
V
V
V
DD
DDQ
SS
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground Ground for the device. Should be connected to ground of the system.
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
controls DQc and DQPc, BWd controls DQd and DQPd.
BW
c
controls DQa and DQPa, BWb controls DQb and DQPb,
a
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW . This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN
new address can be loaded into the device for an access. After being deselected, ADV/LD
is asserted LOW) the internal burst counter is advanced. When LOW, a
should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
and CE3 to select/deselect the device.
CE
2
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE3 to select/deselect the device.
1
Chip Enable 3 Input, active LOW . Sampled on the rising edge of CLK. Used in conjunction with
CE
and CE2 to select/deselect the device.
1
Output Enable, active LOW . Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a Write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
deselect the device, CEN
can be used to extend the previous cycle when required.
does not
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE
as outputs. When HIGH, DQ
cally tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ
write sequences, DQP
BW
, and DQPd is controlled by BWd.
c
and the internal control logic. When OE is asserted LOW, the pins can behave
–DQd are placed in a tri-state condition. The outputs are automati-
a
.
During
is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
a
[a:d].
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Serial data-In to the JTAG circuit. Sampled on the risi ng edge of TCK.
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Document #: 38-05537 Rev. *H Page 6 of 28
[+] Feedback
Pin Definitions (continued)
Pin Name I/O Type Pin Description
NC – No connects. This pin is not connected to the die.
NC (18,
36, 72,
144, 288,
576, 1G
ZZ Input-
– These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
288M, 576M, and 1G densities.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous
with data integrity preserved. For normal operation, this pin has to be LOW or left floating.
ZZ pin has an internal pull-down.
CY7C1354CV25
CY7C1356CV25
Functional Overview
The CY7C1354CV25 and CY7C1356CV25 are
synchronous-pipelined Burst NoBL SRAMs desig ned specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
) is 2.8 ns (250-MHz device).
CO
Accesses can be initiated by asserting all three Chip Enables
, CE2, CE3) active at the rising edge of the clock. If Clock
(CE
1
Enable (CEN
) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD
should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
signal WE
are ALL asserted active, (3) the Write Enable input
3
is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(250-MHz device) provided OE
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
). If CEN is HIGH, the clock
). BW
can be used to
[d:a]
). All
) simplify depth expansion.
is asserted LOW, (2) CE1, CE2,
is active LOW. After the first
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1354CV25 and CY7C1356CV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter i s
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN
and CE
is asserted LOW. The address presented to A0∠A16 is loaded
are ALL asserted active, and (3) the Write signal WE
3
is asserted LOW, (2) CE1, CE2,
into the Address Register. The write signals are latched into
the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE
allows the external logic to present the data on DQ
(DQ
for CY7C1356CV25). In addition, the address for the subse-
a,b,c,d
/DQP
for CY7C1354CV25 and DQ
a,b,c,d
input signal. This
and DQP
/DQP
a,b
a,b
quent access (Read/Write/Deselect) is latched into the
address register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
(DQ
for CY7C1356CV25) (or a subset for byte write operations,
a,b,c,d
/DQP
for CY7C1354CV25 and DQ
a,b,c,d
and DQP
/DQP
a,b
a,b
see Write Cycle Description table for details) inputs is latched
into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BW
CY7C1356CV25) signals. The CY7C1354CV25/56CV25
for CY7C1354CV25 and BW
a,b,c,d
a,b
for
provides Byte Write capability that is described in the Write
Cycle Description table. Asserting the Write Enable input (WE
with the selected Byte Write Select (BW
) input will selectively
write to only the desired bytes. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
)
Document #: 38-05537 Rev. *H Page 7 of 28
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CY7C1354CV25
CY7C1356CV25
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple Byte Write operations.
Because the CY7C1354CV25 and CY7C1356CV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE
deasserted HIGH before presenting data to the DQ
(DQ
for CY7C1356CV25) inputs. Doing so will tri-state the output
a,b,c,d
/DQP
for CY7C1354CV25 and DQ
a,b,c,d
drivers. As a safety precaution, DQ
(DQ
for CY7C1356CV25) are automatically tri-stated during the
a,b,c,d
/DQP
for CY7C1354CV25 and DQ
a,b,c,d
data portion of a write cycle, regardless of the state of OE
) can be
and DQP
/DQP
a,b
and DQP
/DQP
a,b
.
Burst Write Accesses
The CY7C1354CV25/56CV25 has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD
must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD
quent clock rise, the chip enables (CE
WE
inputs are ignored and the burst counter is incremented.
The correct BW
CY7C1356CV25) inputs must be driven in each cycle of the
(BW
a,b,c,d
is driven HIGH on the subse-
, CE2, and CE3) and
1
for CY7C1354CV25 and BW
a,b
for
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
the duration of t
a,b
, CE2, and CE3, must remain inactive for
1
after the ZZ input returns LOW.
ZZREC
Interleaved Burst Address Table
(MODE = Floating or V
a,b
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Second
Address
DD
)
Third
Address
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0 A1,A0 A1,A0 A1,A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Second
Address
Third
Address
Fourth
Address
Fourth
Address
places the SRAM in a power conservation “sleep” mode. Two
ZZ Mode Electrical Characteristics
Parameter Description Test Conditi on s Min. Max. Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Truth Table
Deselect Cycle None H L L X X X L L-H Tri-State
Continue Deselect Cycle None X L H X X X L L-H Tri-State
Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q)
Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q)
NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State
Dummy Read (Continue Burst) Next X L H X X H L L-H Tri-State
Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D)
Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D)
Sleep mode standby current ZZ > VDD − 0.2V 50 mA
Device operation to ZZ ZZ > VDD − 0.2V 2t
ZZ recovery time ZZ < 0.2V 2t
CYC
ZZ active to sleep current This p arameter is sampled 2t
ZZ Inactive to exit sleep current This parameter is sampled 0 ns
[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ
CYC
CYC
ns
ns
ns
Notes:
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE
Valid si gnifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE
4. When a write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE
= H inserts wait states.
6. CEN
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a re ad cycle DQs a nd DQPX = Tri-state when OE
8. OE
is inactive or when the device is deselected, and DQs = data when OE
and BWX. See Write Cycle Description table for details.
stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
signal.
.
is active.
Document #: 38-05537 Rev. *H Page 8 of 28
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CY7C1354CV25
CY7C1356CV25
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Address
Operation
Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ
NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-St ate
WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State
IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H –
SLEEP MODE None X H X X X X X X Tri-State
Partial Write Cycle Description
Function (CY7C1354CV25)
[2, 3, 4, 9]
WE
BW
d
BW
c
BW
b
BW
a
Read H X X X X
Write –No bytes written L H H H H
Write Byte a– (DQ
Write Byte b – (DQ
and DQP
a
and DQP
b
a)
b)
LHHHL
LHHLH
Write Bytes b, a L H H L L
Write Byte c – (DQ
and DQP
c
c)
LHLHH
Write Bytes c, a L H L H L
Write Bytes c, b L H L L H
Write Bytes c, b, a L H L L L
Write Byte d – (DQ
and DQP
d
d)
LLHHH
Write Bytes d, a L L H H L
Write Bytes d, b LLHLH
Write Bytes d, b, a L L H L L
Write Bytes d, c L L L H H
Write Bytes d, c, a L L L H L
Write Bytes d, c, b L L L L H
Write All Bytes L L L L L
Partial Write Cycle Description
[2, 3, 4, 9]
Function (CY7C1356CV25) WE BW
b
BW
a
Read Hxx
Write – No Bytes Written L H H
Write Byte a − (DQ
Write Byte b – (DQ
and DQP
a
and DQP
b
a)
b)
LHL
LLH
Write Both Bytes L L L
Note:
9. Table only lists a partial listin g of the byte write combinat ions. Any combination of BW
is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05537 Rev. *H Page 9 of 28
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